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1 RFIC2017 MO2B-2 A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits M. Baraani Dastjerdi and H. Krishnaswamy CoSMIC Lab, Columbia University, New York, United States MO2B-2

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Page 1: PowerPoint Presentationharish/uploads/2/6/9/...(4-phase) 4dB* (8-phase) Single switch simulation time(s)** 0.298 1.2 Mixer first receiver simulation time(min) 56*** Not feasible *This

1

RFIC2017

MO2B-2

A Simplified CMOS FET Model using Surface

Potential Equations For Inter-modulation

Simulations of Passive-Mixer-Like Circuits

M. Baraani Dastjerdi and H. Krishnaswamy

CoSMIC Lab,

Columbia University, New York, United States

MO2B-2

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RFIC2017

• Motivation and Prior Art

• Simplified Surface Potential Model

• Short-Channel Effects

• Simulation and Measurement Results

• Conclusion

MO2B-2

Outline

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RFIC2017

• Motivation and Prior Art

• Simplified Surface Potential Model

• Short-Channel Effects

• Simulation and Measurement Results

• Conclusion

MO2B-2

Outline

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MO2B-2

Circuits That Use FETs As Switches

Integrated Circulators

Passive-Mixers and

Mixer-First Receivers

[Reiskarimian Nature

Comm.‘16]

[Andrews JSSC‘10]

N-Path Filters

[Ghaffari

JSSC’13]

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Mixer-First Receiver Design Challenges

• Increasing switch FETs size improves linearity at the cost of power consumption.

• Increasing series resistance RM improves linearity at the cost of NF.

Linearity simulations are critical during the design phase for the

optimization of passive mixer-like circuits.

Out-of-band IIP3 is calculated using [Yang TCASI’15]. Power

consumption is calculated for an operating frequency of 1GHz.

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FET Operation As a Switch

MOSFET switches are symmetric devices and typically experience

source-drain reversal during AC operation.

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Gummel Symmetry Test In BSIM4

In BSIM4 models, the 2nd derivative of IDS shows discontinuity

around VDS=0.

65nm CMOS;

FET size: 96𝜇𝑚

65𝑛𝑚;

VGB = 1.2V and Vb=0.3V.

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Two-Tone Test Using BSIM4 Model

The IM3 predicted by BSIM4 models shows unphysical

characteristics (slope of 2dB/dB).

65nm CMOS;

FET size: 96𝜇𝑚

65𝑛𝑚;

VGB = 1.2V.

Vout

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Transistor Models Comparison

Source-referenced models

E.g. BSIM

Body-referenced models

E.g. PSP

✓ Physical driving forces are VGS

and VDS .

✓ VT appears in the equations.

✓ Velocity saturation is easy to

handle.

× Asymmetric around the

source-drain reversal point.

✓ Symmetry is appealing.

✓ Effective mobility is well

handled.

✓ It is easy to make the drain

current continuous at VDS=0.

× Not provided by most digitally-

driven foundries.

✓ Physical driving forces are VGS

and VDS .

✓ VT appears in the equations.

✓ Velocity saturation is easy to

handle.

× Asymmetric around the

source-drain reversal point.

✓ Symmetry is appealing.

✓ Effective mobility is well

handled.

✓ It is easy to make the drain

current continuous at VDS=0.

× Not provided by most digitally-

driven foundries.

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Prior Work

• Break the transistor into 2n+1 transistors in parallel with small offset voltages in

VDS.

[Yuksel RFIC ‘14]

× High processing load (if n=32, 1 FET is replaced by 65 FET).

× Predicts 3dB/dB for IM3 only for ΔV <VDS< nΔV.

× Need measurements to extract value of ΔV.

3dB/dB

slope over

limited

region

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Prior Work

• Break the transistor into 2n+1 transistors in parallel with small offset voltages in

VDS.

[Yuksel RFIC ‘14]

× High processing load (if n=32, 1 FET is replaced by 65 FET).

× Predicts 3dB/dB for IM3 only for ΔV <VDS< nΔV.

× Need measurements to extract value of ΔV.

3dB/dB

slope over

limited

region

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• Motivation and Prior Art

• Simplified Surface Potential Model

• Short-Channel Effects

• Simulation and Measurement Results

• Conclusion

MO2B-2

Outline

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Simplified Surface Potential Model

• Simple Verilog-A code is employed to define the IDS based on FET terminal

voltages using simplified surface potential (SSP) equations.

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Simplified Surface Potential Model

• Foundry provided model is used to take into account the 2nd order parasitics

• Gate-source and gate-drain capacitance.

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Simplified Surface Potential Model

• Foundry provided model is used to take into account the 2nd order parasitics

• Body-source and body-drain capacitance.

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Simplified Surface Potential Model

• Foundry provided model is used to take into account the 2nd order parasitics

• Gate and body leakage currents.

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Surface Potential Equations

• Surface potential at source and drain ends can be described by*:

𝑉𝐹𝐵: Flat-band voltage

𝛾: Body coefficient

𝜙𝐹: Fermi voltage

𝜙𝑡: Thermal voltage

* Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor. Oxford Univ.

Press, 2011.

𝜓𝑠0 = 𝑉𝐺𝐵 − 𝑉𝐹𝐵 − 𝛾 𝜓𝑠0 + 𝜙𝑡𝑒(𝜓𝑠0−2𝜙𝐹−𝑉𝑆𝐵)/𝜙𝑡

𝜓𝑠𝐿 = 𝑉𝐺𝐵 − 𝑉𝐹𝐵 − 𝛾 𝜓𝑠𝐿 + 𝜙𝑡𝑒(𝜓𝑠𝐿−2𝜙𝐹−𝑉𝐷𝐵)/𝜙𝑡

𝝍𝒔𝟎 𝝍𝒔𝑳

0 L

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Surface Potential Along The Channel

• Surface Potential along the channel can be approximated linearly.

0 L

𝝍𝒔𝟎

𝝍𝒔𝑳

Position

along

channel

Surface

Potential

𝝍𝒔𝒎

𝜓𝑠𝑚 =𝜓𝑠0 + 𝜓𝑠𝐿

2

0 L

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Drain-Source Current Equation

• The drain-source current is a combination of drift and diffusion currents and can

be approximated by*:

W : Width

L : Length

𝜇 : Mobility of electron

𝑉𝐹𝐵: Flat-band voltage

𝛾: Body coefficient

𝜑𝐹: Fermi voltage

Completely symmetric at VDS=0.

𝐼𝐷𝑆,𝑑𝑟𝑖𝑓𝑡 =𝑊

𝐿𝜇𝐶𝑜𝑥(𝑉𝐺𝐵 − 𝑉𝐹𝐵 − 𝜓𝑠𝑚 − 𝛾 𝜓𝑠𝑚)(𝜓𝑠𝐿 − 𝜓𝑠0)

𝐼𝐷𝑆,𝑑𝑖𝑓𝑓. =𝑊

𝐿𝜇𝐶𝑜𝑥𝛼𝑚𝜙𝑡 (𝜓𝑠𝐿 − 𝜓𝑠0)

𝐼𝐷𝑆,𝑡𝑜𝑡𝑎𝑙 = 𝐼𝐷𝑆,𝑑𝑟𝑖𝑓𝑡 + 𝐼𝐷𝑆,𝑑𝑖𝑓𝑓.

𝛼𝑚 = 1 +𝛾

2 𝜓𝑠𝑚

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Effective Mobility

• The mobility of electrons is reduced by the transverse field in the channel*.

𝜇0, 𝑎0 and 𝜂𝐸 can be treated as curve

fitting parameters.

𝜇𝑒𝑓𝑓 =𝜇0

1 −𝑎0𝜖𝑠(𝑄′

𝐵 + 𝜂𝐸𝑄′𝐼)

𝑄′𝐵 = −𝐶𝑜𝑥𝛾 𝜓𝑠𝑚

𝑄′𝐼 = −𝐶𝑜𝑥 𝑉𝐺𝐵 − 𝑉𝐹𝐵 − 𝜓𝑠𝑚 − 𝑄′

𝐵

0 L

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• Motivation and Prior Art

• Simplified Surface Potential Model

• Short-Channel Effects

• Simulation and Measurement Results

• Conclusion

MO2B-2

Outline

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Charge Sharing

• The extension of the drain and source depletion charge into the channel reduces

the gate control over the channel charge.

𝛾1 = 𝛾𝑄𝐵𝑄𝐵

𝑄𝐵

𝑄𝐵= 1 −

𝑑𝑗

𝐿(−1 + 1 + 2

𝑑𝐵

𝑑𝑗)

Depletion region is not necessarily same around the source and

drain.

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Completely symmetric at VDS=0.

Δ𝑆/𝐷 = 𝑑𝑗 −1 + 1 + 2𝑑𝐵𝑆/𝐷

𝑑𝑗

𝑑𝐵 =𝑑𝐵𝑆 + 𝑑𝐵𝐷

2𝑑𝑗: Junction depth

MO2B-2

Charge Sharing

• The extension of the drain and source depletion charge into the channel reduces

the gate control over the channel charge.

𝛾1 = 𝛾𝑄𝐵𝑄𝐵

𝑄𝐵

𝑄𝐵= 1 −

Δ𝑆

𝐿(1 −

𝑑𝐵𝑆

2𝑑𝐵) −

Δ𝐷

𝐿(1 −

𝑑𝐵𝐷

2𝑑𝐵)

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Velocity Saturation

• Velocity of carriers can saturate even with device operating in triode.

𝐼𝐷𝑆,𝑤 𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛 =𝐼𝐷𝑆,𝑤/𝑜 𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛

1 +𝑉𝐷𝑆𝐿𝜖𝑐

Second order derivatives are discontinuous.

0 L

EX

Carrier velocity

𝜖𝑐

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Velocity Saturation

• Velocity of carriers can saturate even with device operating in triode.

0 L

𝐼𝐷𝑆,𝑤 𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛 =𝐼𝐷𝑆,𝑤/𝑜 𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛

0.5(1 + 1 + 2𝑉𝐷𝑆𝐿𝜖𝑐

2

)

Accurately models the current and its derivatives.

EX

Carrier velocity

𝜖𝑐

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Channel Length Modulation

• Channel length modulation can be described as:

𝐿𝑒𝑓𝑓 = 𝐿 − 𝑙𝑝

𝑙𝑝 = 𝑙𝑎 × ln 1 +𝑉𝐷𝑆𝑋 − 𝑉𝐷𝑆,𝑒𝑓𝑓

𝑉𝑒, 𝑙𝑎 = 3𝑡𝑜𝑥𝑑𝑗

𝑡𝑜𝑥: gate oxide thickness

𝑑𝑗: source and drain junction depth

𝑉𝑒: Early voltage

• Smoothing functions are employed to ensure about the continuity of the current

around VDS=0*:

𝑉𝐷𝑆,𝑒𝑓𝑓 =𝑉𝐷𝑆

(1+(𝑉𝐷𝑆𝑉′𝐷𝑆

)10)0.1, 𝑉𝐷𝑆𝑋 = 𝑉𝐷𝑆

2 + 0.01 − 0.1

*X. Li et al., “PSP 102.3,” NXP Semiconductors, Tech. Rep. 2008.

𝑉′𝐷𝑆: Smoothing function constant

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Model Parameter Extraction

Foundry provided model

Simulator

Curve-fitting using MATLAB

SSP model parameters

Foundry provided model

Curve-fitting using MATLAB

SSP model parameters

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PSP Model Versus SSP Model

SSP Model PSP

✓ less than 20 parameters

× Ignoring the temperature

variation and process corners

× simulate transistors operating

as a switch

× hundreds of parameters

✓ Include the temperature

variation and process corners

✓ all regions of the operation

✓ Less than 20 parameters

× Ignores temperature variation

and process corners

× Only used for transistors

operating as a switch

× Hundreds of parameters

✓ Includes temperature

variations and process corners

✓ All regions of operation

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PSP Model Versus SSP Model

Only transistors operating as a switch are replaced with the SSP

model.

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• Motivation and Prior Art

• Simplified Surface Potential Model

• Short-Channel Effects

• Simulation and Measurement Results

• Conclusion

MO2B-2

Outline

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Measured Gummel Symmetry Test

The SSP model accurately predicts IDS and its derivatives.

65nm CMOS;

FET size: 96𝜇𝑚

65𝑛𝑚;

VGB = 1.2V and Vb=0.3V.

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Terminal Capacitance Simulation

The SSP model fixes the discontinuity in the terminal

capacitances.

All capacitors: 1F

All Inductors: 1H

65nm CMOS;

FET size: 96𝜇𝑚

65𝑛𝑚;

VGB = 1.2V and Vb=0.3V.

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FET IIP3 Simulation

The model predicts 3dB/dB slope for IM3 for a wide range of drain-

source voltage across the FET.

65nm CMOS;

FET size: 96𝜇𝑚

65𝑛𝑚;

Vg = 1.2V.

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65nm CMOS Mixer-First Receiver

4-Path 0.15-2.5GHz

passive-mixer-first receiver

in 65nm CMOS.

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Mixer-First Receiver Gain

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Mixer-First Receiver Out-of-Band IIP3

The SSP model predicts IIP3 with better than 3dB precision.

The LO frequency is 300MHz and input tones are applied at 500MHz and 699MHz.

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Comparison Table

This work [Yuksel 14]

Mixer-first receiver

OOB-IIP3 simulation

accuracy

3dB

(4-phase)

4dB*

(8-phase)

Single switch

simulation time(s)**

0.298 1.2

Mixer first receiver

simulation time(min)

56*** Not feasible

*This is an 8-phase mixer-first receiver reported in [Andrews JSSC’10].

**The computer is equipped with quad-core i7 CPU and 32GB physical

memory, and simulations are performed on schematic level.

***Simulation is performed with the PSS-shooting method with number of

harmonics equal to 175, the LO frequency is 300MHz and tones are

applied at 500MHz and 680MHz and simulation is done for 3 power level

point.

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• Motivation and Prior Art

• Simplified Surface Potential Model

• Short-Channel Effects

• Simulation and Measurement Results

• Conclusion

MO2B-2

Outline

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Conclusion

• Digitally-driven foundries typically provide BSIM4 models that yield

unphysical results when simulating passive mixer-like circuits.

• A simplified surface potential model is introduced that does not require

measurements for model fitting, and leverages the foundry-provided

models for capturing second-order parasitics.

• The SSP model is more computationally relaxed than prior art, and

shows greater accuracy in simulating linearity of passive-mixer-like

circuits.

• The model is available at cosmic.ee.columbia.edu for download.