pre-release schematic do not copy · 2020-04-20 · pre-release schematic a 11 / 12 / 2017 all...
TRANSCRIPT
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DESCRIPTIONREV DATE PAGES
A 11 / 12 / 2017 All InitialPre-Release Schematic DO NOT COPY
NOTES:
Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework
100-0330648-A1110-0330648-A1120-0330648-A1130-0330648-A1140-0330648-A1150-0330648-A1160-0330648-A1170-0330648-A1180-0330648-A1210-0330648-A1220-0330648-A1320-0330648-A1
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PAGE
FPGA BANK 3L 3K
FPGA BANK UIB 6A/6C 7A/7C
FPGA Power 1
FPGA Power 2
FPGA Gnd 1
FPGA Gnd 2
Clock 2
PWR VCCERAM
Blank
Power Connection Chart
MAX10 Power Control -1
MAX10 Power Control -2
Power inputs
MAX10 - USB Blaster II - 1
Clock 1
Title, Notes, Rev. History
Power Tree
Power Sequence Timing
Clock Tree Diagram
JTAG & I2C Diagram
Blank
DDR4/DDRT Single DIMM
FPGA BANK 3J 3I 3C
DDR4 Component 1
DDR4 Component 2
HiLo Connector Map
HiLo Connector
FPGA BANK 2N 2K 2F
FPGA BANK 2L 2M
FPGA BANK 2B 2C
FPGA BANK 2A
FPGA BANK 4C 4D 4E 4F XCVR
zQSFP1
PCIe End Point Edge Connector
FPGA BANK 3A
FPGA BANK 3B
PWR 12V to 5V
Block Diagram
PWR 12V to 3.3V
PWR VCC - 1
PWR VCC - 2
PWR VCCRL_GXB
PWR VCCRR_GXB
DESCRIPTION
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PAGE DESCRIPTION
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I2C and PMBUS
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FPGA Config SDM
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38
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54
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56
57
58
59
60
61
62
63
64
65
66
67
MAX10 - USB Blaster II -2XCVR Connection Diagram
PWR - Decouping Caps 3
PWR - Decouping Caps 2
PWR - Decouping Caps 1
PWR - Power Discharge
PWR - 2.5V DDR4
PWR - HiLo VDD
PWR - HiLo VDDQ
PWR - DDR4_VTT
PWR - VCCM
PWR VCCIO_1.2V_DDR4
PWR VCCIO_UIB
PWR 1p8V
PWR VCCT_GXB
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69
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LEDs and Push Buttons
FPGA Gnd 3
FPGA Power 3
PCIe Root Port Connector
zQSFP0
FPGA BANK 4K 4L 4M 4N XCVR
FPGA BANK 1C 1D 1E 1F XCVR
FPGA BANK 1K 1L 1M 1N XCVR
DDR4 Component Termination
Blank
Board BOM : 6XX - 44584R
MECHNICAL PARTS
Enclosure Part Numbers PCIe Front Bracket Top Edge Stiffener Lower Edge Stiffener FAN Mounting Bracket Cooling Fan Cooling Fan Finger Guard FPGA Heatsink FPGA Heatsink Backplate Top Cover
P12-27345RP12-27346RP12-27347RP12-27349RP12-27365RP12-27363RP12-27364RP12-27350RP12-27348R
Title
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A0
Stratix 10 MX FPGA Dev Kit
B
1 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
1 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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Date: Sheet o f
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Stratix 10 MX FPGA Dev Kit
B
1 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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System Block Diagram
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Stratix 10 MX FPGA Dev Kit
B
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150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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Date: Sheet o f
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Stratix 10 MX FPGA Dev Kit
B
2 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
2 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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Power Tree Diagram
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3 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
3 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
3 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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Power Sequence Timing
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Stratix 10 MX FPGA Dev Kit
B
4 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
4 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
4 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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Clock Tree
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Stratix 10 MX FPGA Dev Kit
B
5 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
5 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
5 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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I2C Diagram
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Stratix 10 MX FPGA Dev Kit
B
6 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
6 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
6 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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XCVR Connection JTAG Block Diagrram
Title
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
7 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
7 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
7 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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DDR4/DDR-T DIMM Pin Map
DDR-T DIMM Pin Map is Identicalto standard DDR4 DIMM Pin Mapexcept the DDR-T protocolrepurposes five of these pins:
CS1# (pin 89) : Grant, GNT# <0> Input
CKE1 (pin 203) : Request, REQ# <0> Output
ODT1 (pin 91) : Error, ERR# Output
CLK1 (pin 218):Early Read ID, ERID<0> Output
CLK1# (pin 219):Early Read ID, ERID<1> Output
Title
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Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
8 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
8 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
8 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
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C C
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DDR4 DIMM IF
DDR4/DDRT Single DIMM
Put caps on VDD pins which are close to DIMM A/C pins
DDR4_DIMM_DQ63
DDR4_DIMM_A11
DDR4_DIMM_A10
DDR4_DIMM_TDQS_N9
DDR4_DIMM_TDQS_N11
DDR4_DIMM_TDQS_N10
DDR4_DIMM_TDQS_N14
DDR4_DIMM_TDQS_N13
DDR4_DIMM_TDQS_N12
DDR4_DIMM_TDQS_N17
DDR4_DIMM_TDQS_N16
DDR4_DIMM_TDQS_N15
DDR4D_SAVE_N
DDR4_DIMM_SA0DDR4_DIMM_SA1
DDR4_DIMM_DBI_N0
DDR4_DIMM_DQS_N8DDR4_DIMM_DQS_P8
DDR4_DIMM_DQS_P6
DDR4_DIMM_CK_N1DDR4_DIMM_CK_P1
DDR4_DIMM_DQ51
DDR4_DIMM_DQ55
DDR4_DIMM_CS_N0
DDR4_DIMM_CKE1
DDR4D_SAVE_N
DDR4D_EVENT_N
DDR4_DIMM_ACT_N
DDR4_DIMM_ALERT_N
DDR4_DIMM_PAR
DDR4_DIMM_CK_N0DDR4_DIMM_CK_P0
DDR4_DIMM_CKE0
DDR4_DIMM_RESET_N
DDR4_DIMM_BG1
DDR4_DIMM_A3DDR4_DIMM_A2DDR4_DIMM_A1
DDR4_DIMM_BG0
DDR4_DIMM_A0
DDR4_DIMM_A12DDR4_DIMM_A9
DDR4_DIMM_A8DDR4_DIMM_A5DDR4_DIMM_A4
DDR4_DIMM_DQ3DDR4_DIMM_DQ2
DDR4_DIMM_DQ1DDR4_DIMM_DQ0
DDR4_DIMM_DQ9DDR4_DIMM_DQ8
DDR4_DIMM_DQ7DDR4_DIMM_DQ6
DDR4_DIMM_DQ5DDR4_DIMM_DQ4
DDR4_DIMM_DQ14
DDR4_DIMM_DQ13DDR4_DIMM_DQ12
DDR4_DIMM_DQ11DDR4_DIMM_DQ10
DDR4_DIMM_DQ19DDR4_DIMM_DQ18
DDR4_DIMM_DQ17DDR4_DIMM_DQ16
DDR4_DIMM_DQ15
DDR4_DIMM_DQ24
DDR4_DIMM_DQ23DDR4_DIMM_DQ22
DDR4_DIMM_DQ21DDR4_DIMM_DQ20
DDR4_DIMM_DQ29DDR4_DIMM_DQ28
DDR4_DIMM_DQ27DDR4_DIMM_DQ26
DDR4_DIMM_DQ25
DDR4_DIMM_DQ35DDR4_DIMM_DQ34
DDR4_DIMM_DQ33DDR4_DIMM_DQ32
DDR4_DIMM_DQ31DDR4_DIMM_DQ30
DDR4_DIMM_DQ40
DDR4_DIMM_DQ39DDR4_DIMM_DQ38
DDR4_DIMM_DQ37DDR4_DIMM_DQ36
DDR4_DIMM_DQ45DDR4_DIMM_DQ44
DDR4_DIMM_DQ43DDR4_DIMM_DQ42
DDR4_DIMM_DQ41
DDR4_DIMM_DQ61
DDR4_DIMM_DQ50
DDR4_DIMM_DQS_N6
DDR4_DIMM_DQ48
DDR4_DIMM_DQ47DDR4_DIMM_DQ46
DDR4_DIMM_DQ49
DDR4_DIMM_DQ56
DDR4_DIMM_DQ54
DDR4_DIMM_DQ53DDR4_DIMM_DQ52
DDR4_DIMM_DQ62
DDR4_DIMM_DQ57
DDR4_DIMM_DQ60
DDR4_DIMM_DQ59DDR4_DIMM_DQ58
DDR4_DIMM_SA0
DDR4_DIMM_SA2
DDR4_DIMM_DQS_P0DDR4_DIMM_DQS_N0
DDR4_DIMM_DQS_P2DDR4_DIMM_DQS_N2
DDR4_DIMM_DQS_P1DDR4_DIMM_DQS_N1
DDR4_DIMM_DQS_P5DDR4_DIMM_DQS_N5
DDR4_DIMM_DQS_N4DDR4_DIMM_DQS_P4
DDR4_DIMM_DQS_P3DDR4_DIMM_DQS_N3
DDR4_DIMM_SA1
DDR4_DIMM_DBI_N2
DDR4_DIMM_DBI_N1
DDR4_DIMM_DQS_P7DDR4_DIMM_DQS_N7
DDR4_DIMM_DBI_N7
DDR4_DIMM_DBI_N6
DDR4_DIMM_DBI_N5
DDR4_DIMM_DBI_N4
DDR4_DIMM_DBI_N3
DDR4_DIMM_CKE1
DDR4_DIMM_RESET_N
DDR4D_SCL
DDR4_DIMM_CKE0
DDR4_DIMM_DQ65DDR4_DIMM_DQ64
DDR4_DIMM_DBI_N8
DDR4D_SDADDR4D_SCLDDR4D_EVENT_N
DDR4_DIMM_DQ68
DDR4_DIMM_DQ67DDR4_DIMM_DQ66
DDR4_DIMM_DQ71DDR4_DIMM_DQ70
DDR4_DIMM_DQ69
DDR4_DIMM_A7
DDR4_DIMM_A6
DDR4_DIMM_ODT1
DDR4_DIMM_ODT0
DDR4_DIMM_BA0
DDR4_DIMM_CS_N1
DDR4_DIMM_CS_N3DDR4_DIMM_CS_N2
DDR4_DIMM_BA1
DDR4_DIMM_A16
DDR4_DIMM_A15
DDR4_DIMM_A13
DDR4_DIMM_A17
DDR4_DIMM_A14
DDR4D_SDA
DDR4_DIMM_SA2
DDR4D_EVENT_N
DDR4D_SCLDDR4D_SDA
DDR4_DIMM_EVENT_N
DDR4_DIMM_SDADDR4_DIMM_SCLDDR4_DIMM_SAVE_NDDR4D_SAVE_NDDR4_DIMM_C2
1p2V_DDR4
1p2V_DDR4
1p2V_DDR4
1p2V_DDR4
2p5V
12V_G1
2p5V
2p5V
0p6V_DDR4_DIMM_VTT
2p5V
0p6V_DDR4_DIMM_VREF
0p6V_DDR4_DIMM_VREF 0p6V_DDR4_DIMM_VTT2p5V
1p2V_DDR4
0p6V_DDR4_DIMM_VTT
0p6V_DDR4_DIMM_VTT
1p2V_DDR41p2V_DDR4
1p8V
1p8V
2p5V
DDR4_DIMM_DQ[71:0]10,11
DDR4_DIMM_DQS_P[8:0]10,11
DDR4_DIMM_DBI_N[8:0]10,11
DDR4_DIMM_A[17:0]10
DDR4_DIMM_DQS_N[8:0]10,11
DDR4_DIMM_CK_P[1:0]10
DDR4_DIMM_CKE[1:0]10DDR4_DIMM_CK_N[1:0]10
DDR4_DIMM_RESET_N10
DDR4_DIMM_ODT[1:0]10DDR4_DIMM_ACT_N10
DDR4_DIMM_BA[1:0]10DDR4_DIMM_BG[1:0]10
DDR4_DIMM_CS_N[3:0]10
DDR4_DIMM_ALERT_N10DDR4_DIMM_PAR10
DDR4_DIMM_SCL16
DDR4_DIMM_TDQS_N[17:9]10,11
DDR4_DIMM_SAVE_N16DDR4_DIMM_EVENT_N16DDR4_DIMM_SDA16
DDR4_DIMM_C210
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
9 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
9 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
9 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.C32 0.1uF
R8 0
R13 DNI
C3
0.1uF
C6
10nF
R4 10.0K
C10
10nF
C14
10nF
C26
0.1uF
R9 0
C4
10nF
C7
0.1uF
C20 0.1uFC21100uF12066.3VX6T
R6 10.0K
C13
0.1uF
C17
100uF
R14 DNI
C35
0.1uF
R3 DNI
C19 0.1uF
C2
0.1uF
C28
10nF
C29 10nFC36
10nF
C22100uF12066.3VX6T
C25 0.1uFC34
10uF
C15
0.1uF
C24
10uF
C12
10nF
J1A
DDR4x72x288
Vss2
DQ43
Vss4
DQ05
Vss6
DQS9_t/DM0_n/DBI0_n7
DQS9_c8
Vss9
DQ610
Vss11
Vss13
Vss15
Vss17
Vss20
Vss22
Vss24
Vss26
Vss28
Vss31
Vss33
Vss35
Vss37
DQ212
DQ1214
DQ816
DQ1421
DQ1023
DQ2025
DQ1627
DQ2232
DQ1834
DQ2836
DQS10_t/DM1_n/DBI1_n18
DQS10_c19
DQS11_t/DM2_n/DBI2_n29
DQS11_c30
DQ2438
DQ3043
DQ2645
Vss39
Vss42
DQS12_t/DM3_n/DBI3_n40
DQS12_c41
Vss44
Vss46
Vss48
Vss50
Vss53
Vss55
Vss57
Vdd59
Vdd61
CB4/NC47
CB0/NC49
DQS17_t/DM8_n/DBI8_n51
DQS17_c52
CB6/NC54
CB2/NC56
RESET_n58
Vdd64
Vdd67
Vdd70
Vdd73
CKE060
ACT_n62
BG063
A1265
A966
A868
A669
A371
A172
CK0_t74
CK0_c75
Vdd76
Vtt77
Vrefca146
Vss147
Vss149
Vss151
Vss154
Vss156
Vss158
Vss160
Vss162
Vss165
DQ5148
DQ1150
DQ7155
DQ3157
DQ13159
DQ9161
DQ15166
DQS0_c152
DQS0_t153
DQS1_c163
DQS1_t164
Vss167
Vss169
Vss171
Vss173
Vss176
Vss178
Vss180
DQ11168
DQ21170
DQ17172
DQS2_c174
DQS2_t175
DQ23177
DQ19179
DQ29181
Vss182
Vss184
Vss187
Vss189
Vss191
Vss193
Vss195
DQ25183
DQ31188
DQ27190
CB5/NC192
CB1/NC194
Vss198
Vss200
Vss202
Vdd204
Vdd206
Vdd209
Vdd212
Vdd215
Vdd217
CB7/NC199
CB3/NC201
CKE1203
RFU2205
BG1207
ALERT_n208
A11210
A7211
A5213
A4214
A2216
Vdd220
CK1_t218
CK1_c219
Vtt221
DQS3_c185
DQS3_t186
DQS8_c196
DQS8_t197
12V/NC1
12V/NC145
C9
0.1uF
C18
1uF
C1
1uF
R12 DNI
C8
10nF
C31 0.1uF
R5 10.0K
C5
0.1uF
U1
MAX3378E
VL1
IOVL12
IOVL23
IOVL34
IOVL45
NC06
GND7
TSn8 NC19 IOVCC4
10 IOVCC311 IOVCC212 IOVCC113 VCC14
R7 0
J1B
DDR4x72x288
EVENT_n78
A079
Vdd80
BA081
RAS_n/A1682
Vdd83
S0_n84
Vdd85
Vdd88
Vdd90
Vdd92
Vss94
Vss98
Vss101
Vss103
Vss105
Vss107
Vss109
CAS_n/A1586
ODT087
S1_n89
ODT191
S2_n/C093
DQ3695
DQ3297 Vss96
DQS13_t/DM4_n/DBI4_n99
DQS13_c100
DQ38102
DQ34104
DQ44106
DQ40108
DQS14_t/DM5_n/DBI5_n110
DQS14_c111
Vss112
Vss114
Vss116
Vss118
Vss120
Vss123
Vss125
Vss127
Vss129
Vss131
Vss134
Vss136
Vss138
Vpp142
Vpp143
RFU1144
DQ46113
DQ42115
DQ52117
DQ48119
DQS15_t/DM6_n/DBI6_n121
DQS15_c122
DQ54124
DQ50126
DQ60128
DQ56130
DQS16_t/DM7_n/DBI7_n132
DQS16_c133
DQ62135
DQ58137
SA0139
SA1140
SCL141
PARITY222
Vdd223
BA1224
A10/AP225
Vdd226
Vdd229
Vdd231
Vdd233
Vdd236
Vss239
Vss241
Vss243
Vss246
Vss248
Vss250
Vss252
Vss254
RFU3227
WE_n/A14228
SAVE_n/NC230
A13232
A17/NC234
C2/NC235
S3_n/C1237
SA2/RFU238
DQ37240
DQ33242
DQS4_c244
DQS4_t245
DQ39247
DQ35249
DQ45251
DQ41253
Vss257
Vss259
Vss261
Vss263
Vss265
DQS6_t267
Vss270
Vss272
Vss274
Vss276
Vss279
Vss281
Vss283
Vpp286
Vpp287
Vpp288
DQS5_c255
DQS5_t256
DQ47258
DQ43260
DQ53262
DQ49264
DQS6_c266
Vss268
DQ55269
DQ51271
DQ61273
DQ57275
DQS7_c277
DQS7_t278
DQ63280
DQ59282
Vddspd284
SDA285
C37 0.1uF
C27
0.1uF
R11 DNIR10 DNI
R2 0
C33100uF12066.3VX6T
C11
0.1uF
C23
10uF
C30
10nF
R1 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4/T INTERFACE -- FPGA SIDE 3L/3K
DDRT:ERID0 DDRT:ERID1
DDRT:REQ
DDRT:GNT0
DDRT:ERR
DDRT:C0DDRT:C1DDRT:C2
DDRT:NC
DDR4_DIMM_DBI_N6DDR4_DIMM_TDQS_N15
DDR4_DIMM_DQ49
DDR4_DIMM_DQ52
DDR4_DIMM_DQ53DDR4_DIMM_DQS_N6DDR4_DIMM_DQS_P6DDR4_DIMM_DQ51DDR4_DIMM_DQ55
DDR4_DIMM_DQ48
DDR4_DIMM_DQ54DDR4_DIMM_DQ50
DDR4_DIMM_DBI_N7DDR4_DIMM_TDQS_N16
DDR4_DIMM_DQ60
DDR4_DIMM_DQ61
DDR4_DIMM_DQ63DDR4_DIMM_DQS_N7DDR4_DIMM_DQS_P7DDR4_DIMM_DQ56DDR4_DIMM_DQ62
DDR4_DIMM_DQ57
DDR4_DIMM_DQ59DDR4_DIMM_DQ58
DDR4_DIMM_DBI_N2DDR4_DIMM_TDQS_N11
DDR4_DIMM_DQ16
DDR4_DIMM_DQ18
DDR4_DIMM_DQ23DDR4_DIMM_DQS_N2DDR4_DIMM_DQS_P2DDR4_DIMM_DQ17DDR4_DIMM_DQ19
DDR4_DIMM_DQ22
DDR4_DIMM_DQ20DDR4_DIMM_DQ21
DDR4_DIMM_DBI_N5DDR4_DIMM_TDQS_N14
DDR4_DIMM_DQ43
DDR4_DIMM_DQ44
DDR4_DIMM_DQ47
DDR4_DIMM_DQ45DDR4_DIMM_DQS_N5DDR4_DIMM_DQS_P5DDR4_DIMM_DQ46DDR4_DIMM_DQ42DDR4_DIMM_DQ41DDR4_DIMM_DQ40 DDR4_DIMM_BG1
DDR4_DIMM_RESET_NDDR4_DIMM_CS_N0DDR4_DIMM_ACT_NDDR4_DIMM_ODT0DDR4_DIMM_ODT1DDR4_DIMM_CKE0DDR4_DIMM_CKE1DDR4_DIMM_CK_P0DDR4_DIMM_CK_N0DDR4_DIMM_CS_N1DDR4_DIMM_PARDDR4_DIMM_A0DDR4_DIMM_A1DDR4_DIMM_A2DDR4_DIMM_A3DDR4_DIMM_A4DDR4_DIMM_A5DDR4_DIMM_A6DDR4_DIMM_A7DDR4_DIMM_A8DDR4_DIMM_A9DDR4_DIMM_A10
DDR4_DIMM_A12DDR4_DIMM_A13DDR4_DIMM_A14DDR4_DIMM_A15DDR4_DIMM_A16DDR4_DIMM_A17DDR4_DIMM_BA0DDR4_DIMM_BA1DDR4_DIMM_BG0DDR4_DIMM_CS_N2DDR4_DIMM_CS_N3
DDR4_DIMM_CK_P1DDR4_DIMM_CK_N1
DDR4_DIMM_RZQ
DDR4_DIMM_ALERT_N
CLK_DDR4_DIMM_NCLK_DDR4_DIMM_P
DDR4_DIMM_C2
DDR4_DIMM_A11CLK_DDR4_DIMM_P 41CLK_DDR4_DIMM_N 41
DDR4_DIMM_DQ[71:0]9,11
DDR4_DIMM_DQS_P[8:0]9,11
DDR4_DIMM_DBI_N[8:0]9,11
DDR4_DIMM_DQS_N[8:0]9,11
DDR4_DIMM_TDQS_N[17:9]9,11
DDR4_DIMM_CK_P[1:0]9DDR4_DIMM_CK_N[1:0]9
DDR4_DIMM_CKE[1:0]9
DDR4_DIMM_A[17:0]9DDR4_DIMM_ODT[1:0]9DDR4_DIMM_BG[1:0]9DDR4_DIMM_BA[1:0]9DDR4_DIMM_CS_N[3:0]9
DDR4_DIMM_RESET_N9DDR4_DIMM_ACT_N9DDR4_DIMM_PAR9DDR4_DIMM_ALERT_N9
DDR4_DIMM_C29Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
10 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
10 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
10 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R16 100
IO BANK 3L
1SM210H_UF53
U2L
IO, LVDS3L_1N, DQ32M20
IO, LVDS3L_1P, DQ32N20
IO, LVDS3L_2N, DQ32P19
IO, LVDS3L_2P, DQ32N19
IO, LVDS3L_3N, DQ32K21
IO, LVDS3L_3P, DQ32J21
IO, LVDS3L_4N, DQSN32K20
IO, LVDS3L_4P, DQS32L20
IO, LVDS3L_5N, DQ32J22
IO, LVDS3L_5P, DQ32K22
IO, LVDS3L_6N, DQ32J23
IO, LVDS3L_6P, DQ32H23
IO, LVDS3L_7N, DQ33G22
IO, LVDS3L_7P, DQ33F22
IO, LVDS3L_8N, DQ33F23
IO, LVDS3L_8P, DQ33G23
IO, LVDS3L_9N, DQ33C23
IO, LVDS3L_9P, DQ33D23
IO, PLL_3L_CLKOUT1N, LVDS3L_10N, DQSN33B21
IO, PLL_3L_CLKOUT1P, PLL_3L_CLKOUT1, PLL_3L_FBN, LVDS3L_10P, DQS33B22
IO, LVDS3L_11N, DQ33A22
IO, RZQ_3L, LVDS3L_11P, DQ33A23
IO, CLK_3L_1N, LVDS3L_12N, DQ33B23
IO, CLK_3L_1P, LVDS3L_12P, DQ33A24
IO, CLK_3L_0N, LVDS3L_13N, DQ34A25
IO, CLK_3L_0P, LVDS3L_13P, DQ34B25
IO, LVDS3L_14N, DQ34H24
IO, LVDS3L_14P, DQ34J24
IO, PLL_3L_CLKOUT0N, LVDS3L_15N, DQ34F24
IO, PLL_3L_CLKOUT0P, PLL_3L_CLKOUT0, PLL_3L_FBP, PLL_3L_FB0, LVDS3L_15P, DQ34E24
IO, LVDS3L_16N, DQSN34C24
IO, LVDS3L_16P, DQS34D24
IO, LVDS3L_17N, DQ34H25
IO, LVDS3L_17P, DQ34G25
IO, LVDS3L_18N, DQ34E25
IO, LVDS3L_18P, DQ34F25
IO, LVDS3L_19N, DQ35G26
IO, LVDS3L_19P, DQ35G27
IO, LVDS3L_20N, DQ35H26
IO, LVDS3L_20P, DQ35J26
IO, LVDS3L_21N, DQ35E26
IO, LVDS3L_21P, DQ35D26
IO, LVDS3L_22N, DQSN35E27
IO, LVDS3L_22P, DQS35F27
IO, LVDS3L_23N, DQ35B26
IO, LVDS3L_23P, DQ35B27
IO, LVDS3L_24N, DQ35C25
IO, LVDS3L_24P, DQ35C26
IO BANK 3K
1SM210H_UF53
U2M
IO, LVDS3K_1N, DQ36E22
IO, LVDS3K_1P, DQ36D22
IO, LVDS3K_2N, DQ36E21
IO, LVDS3K_2P, DQ36D21
IO, LVDS3K_3N, DQ36C21
IO, LVDS3K_3P, DQ36C20
IO, LVDS3K_4N, DQSN36G21
IO, LVDS3K_4P, DQS36H21
IO, LVDS3K_5N, DQ36H20
IO, LVDS3K_5P, DQ36G20
IO, LVDS3K_6N, DQ36F20
IO, LVDS3K_6P, DQ36E20
IO, LVDS3K_7N, DQ37A19
IO, LVDS3K_7P, DQ37A18
IO, LVDS3K_8N, DQ37B20
IO, LVDS3K_8P, DQ37A20
IO, LVDS3K_9N, DQ37D19
IO, LVDS3K_9P, DQ37C19
IO, PLL_3K_CLKOUT1N, LVDS3K_10N, DQSN37F19
IO, PLL_3K_CLKOUT1P, PLL_3K_CLKOUT1, PLL_3K_FBN, LVDS3K_10P, DQS37E19
IO, LVDS3K_11N, DQ37A17
IO, RZQ_3K, LVDS3K_11P, DQ37B17
IO, CLK_3K_1N, LVDS3K_12N, DQ37C18
IO, CLK_3K_1P, LVDS3K_12P, DQ37B18
IO, CLK_3K_0N, LVDS3K_13N, DQ38D18
IO, CLK_3K_0P, LVDS3K_13P, DQ38D17
IO, LVDS3K_14N, DQ38E16
IO, LVDS3K_14P, DQ38E17
IO, PLL_3K_CLKOUT0N, LVDS3K_15N, DQ38F17
IO, PLL_3K_CLKOUT0P, PLL_3K_CLKOUT0, PLL_3K_FBP, PLL_3K_FB0, LVDS3K_15P, DQ38G17
IO, LVDS3K_16N, DQSN38F18
IO, LVDS3K_16P, DQS38G18
IO, LVDS3K_17N, DQ38K19
IO, LVDS3K_17P, DQ38L19
IO, LVDS3K_18N, DQ38H19
IO, LVDS3K_18P, DQ38J19
IO, LVDS3K_19N, DQ39H18
IO, LVDS3K_19P, DQ39J18
IO, LVDS3K_20N, DQ39J17
IO, LVDS3K_20P, DQ39K17
IO, LVDS3K_21N, DQ39L17
IO, LVDS3K_21P, DQ39M17
IO, LVDS3K_22N, DQSN39L18
IO, LVDS3K_22P, DQS39M18
IO, LVDS3K_23N, DQ39N18
IO, LVDS3K_23P, DQ39P18
IO, LVDS3K_24N, DQ39P17
IO, LVDS3K_24P, DQ39R17
R15240
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4/T INTERFACE -- FPGA SIDE 3J/3I/3C
DDR4_DIMM_DBI_N0DDR4_DIMM_TDQS_N9
DDR4_DIMM_DQ2
DDR4_DIMM_DQ3
DDR4_DIMM_DQ6DDR4_DIMM_DQS_N0DDR4_DIMM_DQS_P0DDR4_DIMM_DQ5DDR4_DIMM_DQ4
DDR4_DIMM_DQ7
DDR4_DIMM_DQ0DDR4_DIMM_DQ1
DDR4_DIMM_DBI_N8DDR4_DIMM_TDQS_N17
DDR4_DIMM_DQ70
DDR4_DIMM_DQ66
DDR4_DIMM_DQ71DDR4_DIMM_DQS_N8DDR4_DIMM_DQS_P8DDR4_DIMM_DQ65DDR4_DIMM_DQ69
DDR4_DIMM_DQ67
DDR4_DIMM_DQ64DDR4_DIMM_DQ68
DDR4_DIMM_DBI_N1DDR4_DIMM_TDQS_N10
DDR4_DIMM_DQ15
DDR4_DIMM_DQ10
DDR4_DIMM_DQ14DDR4_DIMM_DQS_N1DDR4_DIMM_DQS_P1DDR4_DIMM_DQ8DDR4_DIMM_DQ9
DDR4_DIMM_DQ11
DDR4_DIMM_DQ12DDR4_DIMM_DQ13
DDR4_DIMM_DBI_N4DDR4_DIMM_TDQS_N13
DDR4_DIMM_DQ37
DDR4_DIMM_DQ38
DDR4_DIMM_DQ32DDR4_DIMM_DQS_N4DDR4_DIMM_DQS_P4DDR4_DIMM_DQ34DDR4_DIMM_DQ35
DDR4_DIMM_DQ33
DDR4_DIMM_DQ36DDR4_DIMM_DQ39
DDR4_DIMM_DBI_N3DDR4_DIMM_TDQS_N12
DDR4_DIMM_DQ31
DDR4_DIMM_DQ25
DDR4_DIMM_DQ27DDR4_DIMM_DQS_N3DDR4_DIMM_DQS_P3DDR4_DIMM_DQ26DDR4_DIMM_DQ28
DDR4_DIMM_DQ29
DDR4_DIMM_DQ30DDR4_DIMM_DQ24
CLK_CORE_BAK_NCLK_CORE_BAK_P
DDR4_DIMM_DQ[71:0]9,10
DDR4_DIMM_DQS_P[8:0]9,10
DDR4_DIMM_DBI_N[8:0]9,10
DDR4_DIMM_DQS_N[8:0]9,10
DDR4_DIMM_TDQS_N[17:9]9,10
S10_LED043S10_LED143S10_LED243S10_LED343
CLK_CORE_BAK_N41CLK_CORE_BAK_P41
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
11 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
11 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
11 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
IO BANK 3C, 3I
1SM210H_UF53
U2O
IO, LVDS3I_1N, DQ44A10
IO, LVDS3I_1P, DQ44A9
IO, LVDS3I_2N, DQ44B10
IO, LVDS3I_2P, DQ44C10
IO, LVDS3I_3N, DQ44D11
IO, LVDS3I_3P, DQ44C11
IO, LVDS3I_4N, DQSN44E11
IO, LVDS3I_4P, DQS44E10
IO, LVDS3I_5N, DQ44G10
IO, LVDS3I_5P, DQ44F10
IO, LVDS3I_6N, DQ44H11
IO, LVDS3I_6P, DQ44H10
IO, LVDS3I_7N, DQ45G12
IO, LVDS3I_7P, DQ45G11
IO, LVDS3I_8N, DQ45J13
IO, LVDS3I_8P, DQ45H13
IO, LVDS3I_9N, DQ45V13
IO, LVDS3I_9P, DQ45V14
IO, PLL_3I_CLKOUT1N, LVDS3I_10N, DQSN45M13
IO, PLL_3I_CLKOUT1P, PLL_3I_CLKOUT1, PLL_3I_FBN, LVDS3I_10P, DQS45L13
IO, LVDS3I_11N, DQ45P13
IO, RZQ_3I, LVDS3I_11P, DQ45N13
IO, CLK_3I_1N, LVDS3I_12N, DQ45T13
IO, CLK_3I_1P, LVDS3I_12P, DQ45U13
IO, CLK_3C_0N, LVDS3C_13N, DQ54AU13
IO, CLK_3C_0P, LVDS3C_13P, DQ54AT13
IO, LVDS3C_14N, DQ54AT14
IO, LVDS3C_14P, DQ54AR14
IO, PLL_3C_CLKOUT0N, LVDS3C_15N, DQ54BB13
IO, PLL_3C_CLKOUT0P, PLL_3C_CLKOUT0, PLL_3C_FBP, PLL_3C_FB0, LVDS3C_15P, DQ54BA13
IO, LVDS3C_16N, DQSN54AV13
IO, LVDS3C_16P, DQS54AW13
IO, LVDS3C_17N, DQ54BD13
IO, LVDS3C_17P, DQ54BC13
IO, LVDS3C_18N, DQ54BB12
IO, LVDS3C_18P, DQ54BC11
IO, LVDS3C_19N, DQ55BD11
IO, LVDS3C_19P, DQ55BE11
IO, LVDS3C_20N, DQ55BE12
IO, LVDS3C_20P, DQ55BD12
IO, LVDS3C_21N, DQ55BG12
IO, LVDS3C_21P, DQ55BF12
IO, LVDS3C_22N, DQSN55BG11
IO, LVDS3C_22P, DQS55BH11
IO, LVDS3C_23N, DQ55BK11
IO, LVDS3C_23P, DQ55BJ11
IO, LVDS3C_24N, DQ55BL12
IO, LVDS3C_24P, DQ55BK12
R17 100
IO BANK 3J
1SM210H_UF53
U2N
IO, LVDS3J_1N, DQ40D16
IO, LVDS3J_1P, DQ40C16
IO, LVDS3J_2N, DQ40B16
IO, LVDS3J_2P, DQ40B15
IO, LVDS3J_3N, DQ40C15
IO, LVDS3J_3P, DQ40C14
IO, LVDS3J_4N, DQSN40A15
IO, LVDS3J_4P, DQS40A14
IO, LVDS3J_5N, DQ40F15
IO, LVDS3J_5P, DQ40E15
IO, LVDS3J_6N, DQ40G15
IO, LVDS3J_6P, DQ40H15
IO, LVDS3J_7N, DQ41H16
IO, LVDS3J_7P, DQ41G16
IO, LVDS3J_8N, DQ41K16
IO, LVDS3J_8P, DQ41J16
IO, LVDS3J_9N, DQ41K15
IO, LVDS3J_9P, DQ41L15
IO, PLL_3J_CLKOUT1N, LVDS3J_10N, DQSN41N15
IO, PLL_3J_CLKOUT1P, PLL_3J_CLKOUT1, PLL_3J_FBN, LVDS3J_10P, DQS41M15
IO, LVDS3J_11N, DQ41N16
IO, RZQ_3J, LVDS3J_11P, DQ41M16
IO, CLK_3J_1N, LVDS3J_12N, DQ41R16
IO, CLK_3J_1P, LVDS3J_12P, DQ41P16
IO, CLK_3J_0N, LVDS3J_13N, DQ42A12
IO, CLK_3J_0P, LVDS3J_13P, DQ42A13
IO, LVDS3J_14N, DQ42E14
IO, LVDS3J_14P, DQ42D14
IO, PLL_3J_CLKOUT0N, LVDS3J_15N, DQ42C13
IO, PLL_3J_CLKOUT0P, PLL_3J_CLKOUT0, PLL_3J_FBP, PLL_3J_FB0, LVDS3J_15P, DQ42B13
IO, LVDS3J_16N, DQSN42B11
IO, LVDS3J_16P, DQS42B12
IO, LVDS3J_17N, DQ42E12
IO, LVDS3J_17P, DQ42F12
IO, LVDS3J_18N, DQ42D12
IO, LVDS3J_18P, DQ42D13
IO, LVDS3J_19N, DQ43H14
IO, LVDS3J_19P, DQ43J14
IO, LVDS3J_20N, DQ43F14
IO, LVDS3J_20P, DQ43F13
IO, LVDS3J_21N, DQ43N14
IO, LVDS3J_21P, DQ43P14
IO, LVDS3J_22N, DQSN43K14
IO, LVDS3J_22P, DQS43L14
IO, LVDS3J_23N, DQ43R15
IO, LVDS3J_23P, DQ43T15
IO, LVDS3J_24N, DQ43T14
IO, LVDS3J_24P, DQ43R14
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 COMPONENT #1/#2
16Gb ,0.750ns@CL=19 (DDR4-2666)
DDR4_COMP_A0DDR4_COMP_A1DDR4_COMP_A2DDR4_COMP_A3DDR4_COMP_A4DDR4_COMP_A5DDR4_COMP_A6DDR4_COMP_A7DDR4_COMP_A8DDR4_COMP_A9DDR4_COMP_A10DDR4_COMP_A11DDR4_COMP_A12DDR4_COMP_A13DDR4_COMP_A14
DDR4_COMP_CLK_PDDR4_COMP_CLK_N
DDR4_COMP_CS_N
DDR4_COMP_DBI_N0
DDR4_COMP_DQS_P0DDR4_COMP_DQS_N0
DDR4_COMP_DQ0DDR4_COMP_DQ1DDR4_COMP_DQ2DDR4_COMP_DQ3DDR4_COMP_DQ4DDR4_COMP_DQ5DDR4_COMP_DQ6DDR4_COMP_DQ7
DDR4_COMP_A15DDR4_COMP_A16
DDR4_COMP_BA0DDR4_COMP_BA1
DDR4_COMP_RESET_N
DDR4_COMP_DQ9DDR4_COMP_DQ10
DDR4_COMP_DQ8
DDR4_COMP_DQ11DDR4_COMP_DQ12DDR4_COMP_DQ13DDR4_COMP_DQ14DDR4_COMP_DQ15
DDR4_COMP_DQS_P1DDR4_COMP_DQS_N1
DDR4_COMP_DBI_N1
DDR4_COMP_TEN
DDR4_COMP_ALERT_N
DDR4_COMP_ODT
DDR4_COMP_CKEDDR4_COMP_PARDDR4_COMP_ACT_N
DDR4_COMP_A15DDR4_COMP_A16
DDR4_COMP_BA0DDR4_COMP_BA1
DDR4_COMP_RESET_N
DDR4_COMP_DQ25DDR4_COMP_DQ26
DDR4_COMP_DQ24
DDR4_COMP_DQ27DDR4_COMP_DQ28DDR4_COMP_DQ29DDR4_COMP_DQ30DDR4_COMP_DQ31
DDR4_COMP_DQS_P3DDR4_COMP_DQS_N3
DDR4_COMP_DBI_N3
DDR4_COMP_TEN
DDR4_COMP_ALERT_N
DDR4_COMP_ODT
DDR4_COMP_CKEDDR4_COMP_PARDDR4_COMP_ACT_N
DDR4_COMP_CLK_PDDR4_COMP_CLK_N
DDR4_COMP_CS_N
DDR4_COMP_DBI_N2
DDR4_COMP_DQS_P2DDR4_COMP_DQS_N2
DDR4_COMP_DQ16DDR4_COMP_DQ17DDR4_COMP_DQ18DDR4_COMP_DQ19DDR4_COMP_DQ20DDR4_COMP_DQ21DDR4_COMP_DQ22DDR4_COMP_DQ23
DDR4_COMP_A0DDR4_COMP_A1DDR4_COMP_A2DDR4_COMP_A3DDR4_COMP_A4DDR4_COMP_A5DDR4_COMP_A6DDR4_COMP_A7DDR4_COMP_A8DDR4_COMP_A9DDR4_COMP_A10DDR4_COMP_A11DDR4_COMP_A12DDR4_COMP_A13DDR4_COMP_A14
DDR4_COMP_BG0DDR4_COMP_BG1
DDR4_COMP_BG0DDR4_COMP_BG1
1p2V_DDR4
1p2V_DDR4
1p2V_DDR4
1p2V_DDR4
0p6V_DDR4_COMP_VREF
2p5V
2p5V 2p5V
1p2V_DDR4
0p6V_DDR4_COMP_VREF
2p5V
DDR4_COMP_BG0 13,14,15
DDR4_COMP_CS_N 13,14,15DDR4_COMP_ODT 13,14,15
DDR4_COMP_PAR 13,14,15
DDR4_COMP_BA[1:0] 13,14,15
DDR4_COMP_A[16:0] 13,14,15
DDR4_COMP_CKE 13,14,15
DDR4_COMP_RESET_N 13,14,15DDR4_COMP_ACT_N 13,14,15
DDR4_COMP_DQS_P[8:0] 13,14,15,16
DDR4_COMP_DQS_N[8:0] 13,14,15,16
DDR4_COMP_DQ[71:0] 13,14,15,16
DDR4_COMP_DBI_N[8:0] 13,14,15,16
DDR4_COMP_ALERT_N 13,14,15
DDR4_COMP_CLK_P 13,14,15DDR4_COMP_CLK_N 13,14,15
DDR4_COMP_TEN 13,14
DDR4_COMP_BG1 13,14,15
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
12 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
12 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
12 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.C76
0.47uF
C74
0.1uF
C58
4.7nF
C62
0.47uF
C81
0.47uF
C61
0.47uF
C54
2.2nF
C49
2.2nF
C72
0.1uF
C63
0.47uF
C56
3.3nF
C43
22uF
U4
MT40A1G16KNR-075:E
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
LDQS_tG3
LDQS_cF3
NF_LDM_n_LDBI_nE7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
UDQS_tB7
UDQS_cA7
NF_UDM_n_UDBI_nE2
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10_APM3
A11T2
A12_BC_nM7
A13T8
WE_n_A14L2
CAS_n_A15M8
RAS_n_A16L8
BG0M2
BA0N2
BA1N8
PART3
ODTK3
ACT_nL3
CKEK2
CS_nL7
RESET_nP1
ALERT_nP9
CK_tK7
CK_cK8
VDD0B3
VDD1B9
VDD2D1
VDD3G7
VDD4J1
VDD5J9
VDD6L1
VDD7L9
VDD8R1
VDD9T9
VDDQ0A1
VDDQ1A9
VDDQ2C1
VDDQ3D9
VDDQ4F2
VDDQ5F8
VDDQ6G1
VDDQ7G9
VDDQ8J2
VDDQ9J8
VPP_2V5_0B1VPP_2V5_1R9
VREFCAM1
ZQ0F9
VSS2T7
VSS0B2
VSS1E1
ZQ1E9
VSS3G8
VSS4K1
VSS5K9
BG1M9
VSS6N1
VSS7T1
VSSQ0A2
VSSQ1A8
VSSQ2C9
VSSQ3D2
VSSQ4D8
VSSQ5E3
VSSQ6E8
VSSQ7F1
VSSQ8H1
VSSQ9H9
TEN_VSSN9
C50
2.2nF
R20240
C64
22uF
C78
0.47uF
C77
0.47uF
C48
2.2nF
C44
0.47uF
C41
0.47uF
C57
3.3nF
C45
0.47uF
C66
1uF
C42
0.47uF
C68
0.01uF
R19240
C39
0.1uF
C70
0.01uF
C83
0.47uF
C75
0.47uF
C55
2.2nF
C82
0.47uF
C73
0.1uF
C40
0.1uF
C84
0.47uF
U3
MT40A1G16KNR-075:E
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
LDQS_tG3
LDQS_cF3
NF_LDM_n_LDBI_nE7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
UDQS_tB7
UDQS_cA7
NF_UDM_n_UDBI_nE2
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10_APM3
A11T2
A12_BC_nM7
A13T8
WE_n_A14L2
CAS_n_A15M8
RAS_n_A16L8
BG0M2
BA0N2
BA1N8
PART3
ODTK3
ACT_nL3
CKEK2
CS_nL7
RESET_nP1
ALERT_nP9
CK_tK7
CK_cK8
VDD0B3
VDD1B9
VDD2D1
VDD3G7
VDD4J1
VDD5J9
VDD6L1
VDD7L9
VDD8R1
VDD9T9
VDDQ0A1
VDDQ1A9
VDDQ2C1
VDDQ3D9
VDDQ4F2
VDDQ5F8
VDDQ6G1
VDDQ7G9
VDDQ8J2
VDDQ9J8
VPP_2V5_0B1VPP_2V5_1R9
VREFCAM1
ZQ0F9
VSS2T7
VSS0B2
VSS1E1
ZQ1E9
VSS3G8
VSS4K1
VSS5K9
BG1M9
VSS6N1
VSS7T1
VSSQ0A2
VSSQ1A8
VSSQ2C9
VSSQ3D2
VSSQ4D8
VSSQ5E3
VSSQ6E8
VSSQ7F1
VSSQ8H1
VSSQ9H9
TEN_VSSN9
C67
1uF
C65
22uF
C46
22uF
C60
4.7nF
C47
2.2nF
C59
4.7nF
C71
0.1uF
C69
0.01uF
R21240
C79
0.47uF
C51
2.2nF
R18240
C52
2.2nF
C80
0.47uF
C53
2.2nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 COMPONENT #3/#4
16Gb ,0.750ns@CL=19 (DDR4-2666)
DDR4_COMP_A15DDR4_COMP_A16
DDR4_COMP_BA0DDR4_COMP_BA1
DDR4_COMP_RESET_N
DDR4_COMP_DQ41DDR4_COMP_DQ42
DDR4_COMP_DQ40
DDR4_COMP_DQ43DDR4_COMP_DQ44DDR4_COMP_DQ45DDR4_COMP_DQ46DDR4_COMP_DQ47
DDR4_COMP_DQS_P5DDR4_COMP_DQS_N5
DDR4_COMP_DBI_N5
DDR4_COMP_TEN
DDR4_COMP_ALERT_N
DDR4_COMP_ODT
DDR4_COMP_CKEDDR4_COMP_PARDDR4_COMP_ACT_N
DDR4_COMP_CLK_PDDR4_COMP_CLK_N
DDR4_COMP_CS_N
DDR4_COMP_DBI_N4
DDR4_COMP_DQS_P4DDR4_COMP_DQS_N4
DDR4_COMP_DQ32DDR4_COMP_DQ33DDR4_COMP_DQ34DDR4_COMP_DQ35DDR4_COMP_DQ36DDR4_COMP_DQ37DDR4_COMP_DQ38DDR4_COMP_DQ39
DDR4_COMP_BG0DDR4_COMP_BG1
DDR4_COMP_A0DDR4_COMP_A1DDR4_COMP_A2DDR4_COMP_A3DDR4_COMP_A4DDR4_COMP_A5DDR4_COMP_A6DDR4_COMP_A7DDR4_COMP_A8DDR4_COMP_A9DDR4_COMP_A10DDR4_COMP_A11DDR4_COMP_A12DDR4_COMP_A13DDR4_COMP_A14
DDR4_COMP_A15DDR4_COMP_A16
DDR4_COMP_BA0DDR4_COMP_BA1
DDR4_COMP_RESET_N
DDR4_COMP_DQ57DDR4_COMP_DQ58
DDR4_COMP_DQ56
DDR4_COMP_DQ59DDR4_COMP_DQ60DDR4_COMP_DQ61DDR4_COMP_DQ62DDR4_COMP_DQ63
DDR4_COMP_DQS_P7DDR4_COMP_DQS_N7
DDR4_COMP_DBI_N7
DDR4_COMP_ODT
DDR4_COMP_TEN
DDR4_COMP_ALERT_NDDR4_COMP_CKEDDR4_COMP_PARDDR4_COMP_ACT_N
DDR4_COMP_CLK_PDDR4_COMP_CLK_N
DDR4_COMP_CS_N
DDR4_COMP_DBI_N6
DDR4_COMP_DQS_P6DDR4_COMP_DQS_N6
DDR4_COMP_DQ48DDR4_COMP_DQ49DDR4_COMP_DQ50DDR4_COMP_DQ51DDR4_COMP_DQ52DDR4_COMP_DQ53DDR4_COMP_DQ54DDR4_COMP_DQ55
DDR4_COMP_A0DDR4_COMP_A1DDR4_COMP_A2DDR4_COMP_A3DDR4_COMP_A4DDR4_COMP_A5DDR4_COMP_A6DDR4_COMP_A7DDR4_COMP_A8DDR4_COMP_A9DDR4_COMP_A10DDR4_COMP_A11DDR4_COMP_A12
DDR4_COMP_BG0DDR4_COMP_BG1
DDR4_COMP_A13DDR4_COMP_A14
2p5V
1p2V_DDR4
1p2V_DDR4
0p6V_DDR4_COMP_VREF
1p2V_DDR4
1p2V_DDR4
2p5V
2p5V
1p2V_DDR4
0p6V_DDR4_COMP_VREF
2p5V
DDR4_COMP_BG0 12,14,15
DDR4_COMP_CS_N 12,14,15DDR4_COMP_ODT 12,14,15
DDR4_COMP_PAR 12,14,15
DDR4_COMP_TEN 12,14
DDR4_COMP_BA[1:0] 12,14,15
DDR4_COMP_A[16:0] 12,14,15
DDR4_COMP_BG1 12,14,15
DDR4_COMP_DQS_P[8:0] 12,14,15,16
DDR4_COMP_DQS_N[8:0] 12,14,15,16
DDR4_COMP_DQ[71:0] 12,14,15,16
DDR4_COMP_DBI_N[8:0] 12,14,15,16
DDR4_COMP_ALERT_N 12,14,15
DDR4_COMP_CLK_P 12,14,15DDR4_COMP_CLK_N 12,14,15DDR4_COMP_CKE 12,14,15
DDR4_COMP_RESET_N 12,14,15DDR4_COMP_ACT_N 12,14,15
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
13 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
13 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
13 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.C127
0.47uF
C124
0.47uF
C101
2.2nF
C102
3.3nF
C107
0.47uF
U6
MT40A1G16KNR-075:E
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
LDQS_tG3
LDQS_cF3
NF_LDM_n_LDBI_nE7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
UDQS_tB7
UDQS_cA7
NF_UDM_n_UDBI_nE2
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10_APM3
A11T2
A12_BC_nM7
A13T8
WE_n_A14L2
CAS_n_A15M8
RAS_n_A16L8
BG0M2
BA0N2
BA1N8
PART3
ODTK3
ACT_nL3
CKEK2
CS_nL7
RESET_nP1
ALERT_nP9
CK_tK7
CK_cK8
VDD0B3
VDD1B9
VDD2D1
VDD3G7
VDD4J1
VDD5J9
VDD6L1
VDD7L9
VDD8R1
VDD9T9
VDDQ0A1
VDDQ1A9
VDDQ2C1
VDDQ3D9
VDDQ4F2
VDDQ5F8
VDDQ6G1
VDDQ7G9
VDDQ8J2
VDDQ9J8
VPP_2V5_0B1VPP_2V5_1R9
VREFCAM1
ZQ0F9
VSS2T7
VSS0B2
VSS1E1
ZQ1E9
VSS3G8
VSS4K1
VSS5K9
BG1M9
VSS6N1
VSS7T1
VSSQ0A2
VSSQ1A8
VSSQ2C9
VSSQ3D2
VSSQ4D8
VSSQ5E3
VSSQ6E8
VSSQ7F1
VSSQ8H1
VSSQ9H9
TEN_VSSN9
C114
0.01uF
C94
2.2nF
C108
0.47uFC111
22uF
C99
2.2nF
C115
0.01uF
U5
MT40A1G16KNR-075:E
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
LDQS_tG3
LDQS_cF3
NF_LDM_n_LDBI_nE7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
UDQS_tB7
UDQS_cA7
NF_UDM_n_UDBI_nE2
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10_APM3
A11T2
A12_BC_nM7
A13T8
WE_n_A14L2
CAS_n_A15M8
RAS_n_A16L8
BG0M2
BA0N2
BA1N8
PART3
ODTK3
ACT_nL3
CKEK2
CS_nL7
RESET_nP1
ALERT_nP9
CK_tK7
CK_cK8
VDD0B3
VDD1B9
VDD2D1
VDD3G7
VDD4J1
VDD5J9
VDD6L1
VDD7L9
VDD8R1
VDD9T9
VDDQ0A1
VDDQ1A9
VDDQ2C1
VDDQ3D9
VDDQ4F2
VDDQ5F8
VDDQ6G1
VDDQ7G9
VDDQ8J2
VDDQ9J8
VPP_2V5_0B1VPP_2V5_1R9
VREFCAM1
ZQ0F9
VSS2T7
VSS0B2
VSS1E1
ZQ1E9
VSS3G8
VSS4K1
VSS5K9
BG1M9
VSS6N1
VSS7T1
VSSQ0A2
VSSQ1A8
VSSQ2C9
VSSQ3D2
VSSQ4D8
VSSQ5E3
VSSQ6E8
VSSQ7F1
VSSQ8H1
VSSQ9H9
TEN_VSSN9
C109
0.47uF
C92
22uF
C129
0.47uF
C119
0.1uF
C112
1uF
C128
0.47uF
C123
0.47uF
C90
0.47uF
C85
0.1uF
R24240
C105
4.7nF
C130
0.47uF
C113
1uF
C116
0.01uF
C93
2.2nF
C91
0.47uF
C86
0.1uF
R23240
C106
4.7nF
C117
0.1uF
C98
2.2nF
C95
2.2nF
R22240
C120
0.1uF
C104
4.7nFC110
22uF
C121
0.47uF
C96
2.2nF
C89
22uF
C87
0.47uF
C97
2.2nF
C103
3.3nF
C88
0.47uF
C126
0.47uF
C100
2.2nF
C122
0.47uF
C118
0.1uF
C125
0.47uF
R25240
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 COMPONENT #5 & Termination
DDR4_COMP_ACT_NDDR4_COMP_A3DDR4_COMP_BA1DDR4_COMP_A12
DDR4_COMP_A2DDR4_COMP_A9DDR4_COMP_A11DDR4_COMP_A13
DDR4_COMP_BA0DDR4_COMP_A5DDR4_COMP_A4DDR4_COMP_A1
DDR4_COMP_A7DDR4_COMP_A8
DDR4_COMP_A6
DDR4_COMP_CKE
DDR4_COMP_RESET_N
DDR4_COMP_ALERT_N
DDR4_COMP_A16DDR4_COMP_A15DDR4_COMP_A14DDR4_COMP_ODT
DDR4_COMP_CLK_P
DDR4_COMP_CLK_N
DDR4_COMP_PAR
DDR4_COMP_A0DDR4_COMP_A10
DDR4_COMP_TEN
DDR4_COMP_BG0DDR4_COMP_CS_N
DDR4_COMP_BG1
DDR4_COMP_A16DDR4_COMP_A15
DDR4_COMP_RESET_N
DDR4_COMP_BA1DDR4_COMP_BA0
DDR4_COMP_ODT
DDR4_COMP_CKE DDR4_COMP_ALERT_N
DDR4_COMP_TEN
DDR4_COMP_ACT_NDDR4_COMP_PAR
DDR4_COMP_CS_N
DDR4_COMP_CLK_NDDR4_COMP_CLK_P
DDR4_COMP_DQS_P8
DDR4_COMP_DBI_N8
DDR4_COMP_DQ64
DDR4_COMP_DQS_N8
DDR4_COMP_DQ69DDR4_COMP_DQ68DDR4_COMP_DQ67DDR4_COMP_DQ66DDR4_COMP_DQ65
DDR4_COMP_A0
DDR4_COMP_DQ71DDR4_COMP_DQ70
DDR4_COMP_A4DDR4_COMP_A3DDR4_COMP_A2DDR4_COMP_A1
DDR4_COMP_A9DDR4_COMP_A8DDR4_COMP_A7DDR4_COMP_A6DDR4_COMP_A5
DDR4_COMP_BG1DDR4_COMP_BG0
DDR4_COMP_A12DDR4_COMP_A11DDR4_COMP_A10
DDR4_COMP_A14DDR4_COMP_A13
0p6V_DDR4_COMP_VTT
0p6V_DDR4_COMP_VTT 0p6V_DDR4_COMP_VTT 0p6V_DDR4_COMP_VTT
1p2V_DDR4
0p6V_DDR4_COMP_VTT
1p2V_DDR4
2p5V
1p2V_DDR4
0p6V_DDR4_COMP_VREF
2p5V
1p2V_DDR4
DDR4_COMP_BG0 12,13,15
DDR4_COMP_CS_N 12,13,15DDR4_COMP_ODT 12,13,15
DDR4_COMP_PAR 12,13,15
DDR4_COMP_BA[1:0] 12,13,15
DDR4_COMP_A[16:0] 12,13,15
DDR4_COMP_BG1 12,13,15
DDR4_COMP_CKE 12,13,15
DDR4_COMP_ACT_N 12,13,15
DDR4_COMP_DQS_P[8:0] 12,13,15,16
DDR4_COMP_DQS_N[8:0] 12,13,15,16
DDR4_COMP_DQ[71:0] 12,13,15,16
DDR4_COMP_DBI_N[8:0] 12,13,15,16
DDR4_COMP_ALERT_N 12,13,15
DDR4_COMP_CLK_P 12,13,15DDR4_COMP_CLK_N 12,13,15
DDR4_COMP_RESET_N 12,13,15
DDR4_COMP_TEN 12,13
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
14 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
14 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
14 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
V27
V4
V19
R43 DNI
R27 1K
C131
0.1uF
V18
R40 49.9
C134
0.47uF
RN3
43ohm
12345
678
V2
V17
R28 1K
C135
0.01uF
C133
0.47uF
R37240
V20
R45 0
C132
22uF
R41 DNI
U7
MT40A1G16KNR-075:E
DQ0G2
DQ1F7
DQ2H3
DQ3H7
DQ4H2
DQ5H8
DQ6J3
DQ7J7
LDQS_tG3
LDQS_cF3
NF_LDM_n_LDBI_nE7
DQ8A3
DQ9B8
DQ10C3
DQ11C7
DQ12C2
DQ13C8
DQ14D3
DQ15D7
UDQS_tB7
UDQS_cA7
NF_UDM_n_UDBI_nE2
A0P3
A1P7
A2R3
A3N7
A4N3
A5P8
A6P2
A7R8
A8R2
A9R7
A10_APM3
A11T2
A12_BC_nM7
A13T8
WE_n_A14L2
CAS_n_A15M8
RAS_n_A16L8
BG0M2
BA0N2
BA1N8
PART3
ODTK3
ACT_nL3
CKEK2
CS_nL7
RESET_nP1
ALERT_nP9
CK_tK7
CK_cK8
VDD0B3
VDD1B9
VDD2D1
VDD3G7
VDD4J1
VDD5J9
VDD6L1
VDD7L9
VDD8R1
VDD9T9
VDDQ0A1
VDDQ1A9
VDDQ2C1
VDDQ3D9
VDDQ4F2
VDDQ5F8
VDDQ6G1
VDDQ7G9
VDDQ8J2
VDDQ9J8
VPP_2V5_0B1VPP_2V5_1R9
VREFCAM1
ZQ0F9
VSS2T7
VSS0B2
VSS1E1
ZQ1E9
VSS3G8
VSS4K1
VSS5K9
BG1M9
VSS6N1
VSS7T1
VSSQ0A2
VSSQ1A8
VSSQ2C9
VSSQ3D2
VSSQ4D8
VSSQ5E3
VSSQ6E8
VSSQ7F1
VSSQ8H1
VSSQ9H9
TEN_VSSN9
V23
V26
R29 1K
CN4
0.1uF
1234 5
678
R44 1K
RN5
43ohm
12345
678
R35 1K
R47 49.9
RN4
43ohm
12345
678
R30 1K
CN3
0.1uF
1234 5
678
C136
100uF
R42 1K
R48 49.9
R36 1K
V7
R34 1K
V25
R31 1K
RN1
43ohm
12345
678
V28
CN5
0.1uF
1234 5
678
V8
RN6
43ohm
12345
678
R39 49.9
V11
R32 1K
V15
V10
RN2
43ohm
12345
678
V22
V14
V9
R46 DNI
V21
V6
V16
V12
R33 1K
V24
V13R38240
R26 1K
V5
V3V1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 COMP Interface - FPGA Side 2L/2M
CLK_DDR4_COMP_P CLK_DDR4_COMP_N
DDR4_COMP_DBI_N8DDR4_COMP_DQ66
DDR4_COMP_DQ69DDR4_COMP_DQ68DDR4_COMP_DQS_N8DDR4_COMP_DQS_P8DDR4_COMP_DQ67DDR4_COMP_DQ71
DDR4_COMP_DQ70
DDR4_COMP_DQ64DDR4_COMP_DQ65
DDR4_COMP_RESET_NDDR4_COMP_CS_NDDR4_COMP_ACT_NDDR4_COMP_ODT
DDR4_COMP_CKE
DDR4_COMP_CLK_PDDR4_COMP_CLK_N
DDR4_COMP_PARDDR4_COMP_A0DDR4_COMP_A1DDR4_COMP_A2DDR4_COMP_A3DDR4_COMP_A4DDR4_COMP_A5DDR4_COMP_A6DDR4_COMP_A7DDR4_COMP_A8DDR4_COMP_A9DDR4_COMP_A10DDR4_COMP_A11
DDR4_COMP_A12DDR4_COMP_A13DDR4_COMP_A14DDR4_COMP_A15DDR4_COMP_A16
DDR4_COMP_BA0DDR4_COMP_BA1DDR4_COMP_BG0
DDR4_COMP_RZQ
DDR4_COMP_BG1
DDR4_COMP_ALERT_N
DDR4_COMP_DBI_N3DDR4_COMP_DQ25
DDR4_COMP_DQ26DDR4_COMP_DQ30DDR4_COMP_DQS_N3DDR4_COMP_DQS_P3DDR4_COMP_DQ31DDR4_COMP_DQ27
DDR4_COMP_DQ29
DDR4_COMP_DQ24DDR4_COMP_DQ28
DDR4_COMP_DBI_N7DDR4_COMP_DQ63
DDR4_COMP_DQ61DDR4_COMP_DQ57DDR4_COMP_DQS_N7DDR4_COMP_DQS_P7DDR4_COMP_DQ60DDR4_COMP_DQ56
DDR4_COMP_DQ59
DDR4_COMP_DQ62DDR4_COMP_DQ58
DDR4_COMP_DBI_N4DDR4_COMP_DQ33
DDR4_COMP_DQ37DDR4_COMP_DQ39DDR4_COMP_DQS_N4DDR4_COMP_DQS_P4DDR4_COMP_DQ38DDR4_COMP_DQ34
DDR4_COMP_DQ35
DDR4_COMP_DQ32DDR4_COMP_DQ36
DDR4_COMP_DBI_N0DDR4_COMP_DQ7
DDR4_COMP_DQ2DDR4_COMP_DQ6DDR4_COMP_DQS_N0DDR4_COMP_DQS_P0DDR4_COMP_DQ4DDR4_COMP_DQ0
DDR4_COMP_DQ3
DDR4_COMP_DQ1DDR4_COMP_DQ5
DDR4_COMP_DQS_P[8:0] 12,13,14,16
DDR4_COMP_DQS_N[8:0] 12,13,14,16
DDR4_COMP_DQ[71:0] 12,13,14,16
CLK_DDR4_COMP_P 41CLK_DDR4_COMP_N 41
DDR4_COMP_DBI_N[8:0] 12,13,14,16
DDR4_COMP_BG012,13,14
DDR4_COMP_BA[1:0]12,13,14
DDR4_COMP_A[16:0]12,13,14
DDR4_COMP_ODT12,13,14
DDR4_COMP_ACT_N12,13,14DDR4_COMP_PAR12,13,14DDR4_COMP_CKE12,13,14
DDR4_COMP_RESET_N12,13,14
DDR4_COMP_CLK_P12,13,14DDR4_COMP_CLK_N12,13,14
DDR4_COMP_ALERT_N 12,13,14
DDR4_COMP_CS_N12,13,14
DDR4_COMP_BG112,13,14
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
15 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
15 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
15 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
IO BANK 2L
1SM210H_UF53
U2G
IO, LVDS2L_1N, DQ8R31
IO, LVDS2L_1P, DQ8P31
IO, LVDS2L_2N, DQ8R32
IO, LVDS2L_2P, DQ8P32
IO, LVDS2L_3N, DQ8T32
IO, LVDS2L_3P, DQ8T33
IO, LVDS2L_4N, DQSN8N31
IO, LVDS2L_4P, DQS8M31
IO, LVDS2L_5N, DQ8P33
IO, LVDS2L_5P, DQ8N33
IO, LVDS2L_6N, DQ8M33
IO, LVDS2L_6P, DQ8L33
IO, LVDS2L_7N, DQ9L32
IO, LVDS2L_7P, DQ9M32
IO, LVDS2L_8N, DQ9J32
IO, LVDS2L_8P, DQ9K32
IO, LVDS2L_9N, DQ9J33
IO, LVDS2L_9P, DQ9H33
IO, PLL_2L_CLKOUT1N, LVDS2L_10N, DQSN9F33
IO, PLL_2L_CLKOUT1P, PLL_2L_CLKOUT1, PLL_2L_FBN, LVDS2L_10P, DQS9G33
IO, LVDS2L_11N, DQ9C35
IO, RZQ_2L, LVDS2L_11P, DQ9C34
IO, CLK_2L_1N, LVDS2L_12N, DQ9E34
IO, CLK_2L_1P, LVDS2L_12P, DQ9D34
IO, CLK_2L_0N, LVDS2L_13N, DQ10G32
IO, CLK_2L_0P, LVDS2L_13P, DQ10F32
IO, LVDS2L_14N, DQ10H31
IO, LVDS2L_14P, DQ10G31
IO, PLL_2L_CLKOUT0N, LVDS2L_15N, DQ10C33
IO, PLL_2L_CLKOUT0P, PLL_2L_CLKOUT0, PLL_2L_FBP, PLL_2L_FB0, LVDS2L_15P, DQ10D33
IO, LVDS2L_16N, DQSN10E32
IO, LVDS2L_16P, DQS10D32
IO, LVDS2L_17N, DQ10K31
IO, LVDS2L_17P, DQ10J31
IO, LVDS2L_18N, DQ10B32
IO, LVDS2L_18P, DQ10B33
IO, LVDS2L_19N, DQ11A34
IO, LVDS2L_19P, DQ11A33
IO, LVDS2L_20N, DQ11B35
IO, LVDS2L_20P, DQ11A35
IO, LVDS2L_21N, DQ11E31
IO, LVDS2L_21P, DQ11D31
IO, LVDS2L_22N, DQSN11A32
IO, LVDS2L_22P, DQS11B31
IO, LVDS2L_23N, DQ11A30
IO, LVDS2L_23P, DQ11B30
IO, LVDS2L_24N, DQ11C31
IO, LVDS2L_24P, DQ11C30
R49240
IO BANK 2M
1SM210H_UF53
U2F
IO, LVDS2M_1N, DQ4T34
IO, LVDS2M_1P, DQ4R34
IO, LVDS2M_2N, DQ4T35
IO, LVDS2M_2P, DQ4R35
IO, LVDS2M_3N, DQ4P36
IO, LVDS2M_3P, DQ4R36
IO, LVDS2M_4N, DQSN4N36
IO, LVDS2M_4P, DQS4M36
IO, LVDS2M_5N, DQ4J36
IO, LVDS2M_5P, DQ4K36
IO, LVDS2M_6N, DQ4H36
IO, LVDS2M_6P, DQ4G36
IO, LVDS2M_7N, DQ5G37
IO, LVDS2M_7P, DQ5F37
IO, LVDS2M_8N, DQ5D37
IO, LVDS2M_8P, DQ5E37
IO, LVDS2M_9N, DQ5C38
IO, LVDS2M_9P, DQ5D38
IO, PLL_2M_CLKOUT1N, LVDS2M_10N, DQSN5D39
IO, PLL_2M_CLKOUT1P, PLL_2M_CLKOUT1, PLL_2M_FBN, LVDS2M_10P, DQS5C39
IO, LVDS2M_11N, DQ5B40
IO, RZQ_2M, LVDS2M_11P, DQ5A40
IO, CLK_2M_1N, LVDS2M_12N, DQ5B41
IO, CLK_2M_1P, LVDS2M_12P, DQ5A42
IO, CLK_2M_0N, LVDS2M_13N, DQ6N35
IO, CLK_2M_0P, LVDS2M_13P, DQ6M35
IO, LVDS2M_14N, DQ6P34
IO, LVDS2M_14P, DQ6N34
IO, PLL_2M_CLKOUT0N, LVDS2M_15N, DQ6K34
IO, PLL_2M_CLKOUT0P, PLL_2M_CLKOUT0, PLL_2M_FBP, PLL_2M_FB0, LVDS2M_15P, DQ6L34
IO, LVDS2M_16N, DQSN6K35
IO, LVDS2M_16P, DQS6L35
IO, LVDS2M_17N, DQ6H35
IO, LVDS2M_17P, DQ6G35
IO, LVDS2M_18N, DQ6J34
IO, LVDS2M_18P, DQ6H34
IO, LVDS2M_19N, DQ7A39
IO, LVDS2M_19P, DQ7A38
IO, LVDS2M_20N, DQ7B38
IO, LVDS2M_20P, DQ7B37
IO, LVDS2M_21N, DQ7A37
IO, LVDS2M_21P, DQ7B36
IO, LVDS2M_22N, DQSN7D36
IO, LVDS2M_22P, DQS7C36
IO, LVDS2M_23N, DQ7E35
IO, LVDS2M_23P, DQ7E36
IO, LVDS2M_24N, DQ7F35
IO, LVDS2M_24P, DQ7F34
R50 100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR4 COMP Interface - FPGA Side 2N/2K/2F
DDR4_COMP_DBI_N5DDR4_COMP_DQ44
DDR4_COMP_DQ42DDR4_COMP_DQ41DDR4_COMP_DQS_N5DDR4_COMP_DQS_P5DDR4_COMP_DQ47DDR4_COMP_DQ43
DDR4_COMP_DQ40
DDR4_COMP_DQ46DDR4_COMP_DQ45
DDR4_COMP_DBI_N2DDR4_COMP_DQ17
DDR4_COMP_DQ19DDR4_COMP_DQ22DDR4_COMP_DQS_N2DDR4_COMP_DQS_P2DDR4_COMP_DQ23DDR4_COMP_DQ20
DDR4_COMP_DQ21
DDR4_COMP_DQ18DDR4_COMP_DQ16
DDR4_COMP_DBI_N1DDR4_COMP_DQ8
DDR4_COMP_DQ10DDR4_COMP_DQ12DDR4_COMP_DQS_N1DDR4_COMP_DQS_P1DDR4_COMP_DQ13DDR4_COMP_DQ15
DDR4_COMP_DQ9
DDR4_COMP_DQ14DDR4_COMP_DQ11
DDR4_COMP_DBI_N6DDR4_COMP_DQ48
DDR4_COMP_DQ52DDR4_COMP_DQ54DDR4_COMP_DQS_N6DDR4_COMP_DQS_P6DDR4_COMP_DQ55DDR4_COMP_DQ49
DDR4_COMP_DQ50
DDR4_COMP_DQ51DDR4_COMP_DQ53
DDR4_DIMM_EVENT_NDDR4_DIMM_SAVE_NDDR4_DIMM_SCLDDR4_DIMM_SDA
1p8V
DDR4_COMP_DQS_P[8:0] 12,13,14,15
DDR4_COMP_DQS_N[8:0] 12,13,14,15
DDR4_COMP_DQ[71:0] 12,13,14,15
DDR4_COMP_DBI_N[8:0] 12,13,14,15
DDR4_DIMM_SAVE_N9DDR4_DIMM_EVENT_N9
DDR4_DIMM_SCL9
DDR4_DIMM_SDA9
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
16 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
16 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
16 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R53 10.0KR54 10.0K
R51 10.0K
IO BANK 2K,2F
1SM210H_UF53
U2H
IO, LVDS2K_1N, DQ12P29
IO, LVDS2K_1P, DQ12N29
IO, LVDS2K_2N, DQ12R29
IO, LVDS2K_2P, DQ12R30
IO, LVDS2K_3N, DQ12L30
IO, LVDS2K_3P, DQ12K30
IO, LVDS2K_4N, DQSN12L29
IO, LVDS2K_4P, DQS12K29
IO, LVDS2K_5N, DQ12J29
IO, LVDS2K_5P, DQ12H29
IO, LVDS2K_6N, DQ12N30
IO, LVDS2K_6P, DQ12M30
IO, LVDS2K_7N, DQ13F30
IO, LVDS2K_7P, DQ13E30
IO, LVDS2K_8N, DQ13H30
IO, LVDS2K_8P, DQ13G30
IO, LVDS2K_9N, DQ13D29
IO, LVDS2K_9P, DQ13C29
IO, PLL_2K_CLKOUT1N, LVDS2K_10N, DQSN13F29
IO, PLL_2K_CLKOUT1P, PLL_2K_CLKOUT1, PLL_2K_FBN, LVDS2K_10P, DQS13E29
IO, LVDS2K_11N, DQ13A29
IO, RZQ_2K, LVDS2K_11P, DQ13A28
IO, CLK_2K_1N, LVDS2K_12N, DQ13B28
IO, CLK_2K_1P, LVDS2K_12P, DQ13C28
IO, CLK_2F_0N, LVDS2F_13N, DQ18BL22
IO, CLK_2F_0P, LVDS2F_13P, DQ18BL23
IO, LVDS2F_14N, DQ18BK22
IO, LVDS2F_14P, DQ18BJ22
IO, PLL_2F_CLKOUT0N, LVDS2F_15N, DQ18BH23
IO, PLL_2F_CLKOUT0P, PLL_2F_CLKOUT0, PLL_2F_FBP, PLL_2F_FB0, LVDS2F_15P, DQ18BJ23
IO, LVDS2F_16N, DQSN18BG23
IO, LVDS2F_16P, DQS18BF23
IO, LVDS2F_17N, DQ18BF24
IO, LVDS2F_17P, DQ18BE24
IO, LVDS2F_18N, DQ18BH25
IO, LVDS2F_18P, DQ18BH24
IO, LVDS2F_19N, DQ19BE25
IO, LVDS2F_19P, DQ19BE26
IO, LVDS2F_20N, DQ19BF25
IO, LVDS2F_20P, DQ19BG25
IO, LVDS2F_21N, DQ19BB27
IO, LVDS2F_21P, DQ19BB26
IO, LVDS2F_22N, DQSN19BD26
IO, LVDS2F_22P, DQS19BC26
IO, LVDS2F_23N, DQ19AW27
IO, LVDS2F_23P, DQ19AW28
IO, LVDS2F_24N, DQ19BA27
IO, LVDS2F_24P, DQ19AY27
R52 10.0K
IO BANK 2N
1SM210H_UF53
U2E
IO, LVDS2N_1N, DQ0C40
IO, LVDS2N_1P, DQ0C41
IO, LVDS2N_2N, DQ0B42
IO, LVDS2N_2P, DQ0C42
IO, LVDS2N_3N, DQ0D41
IO, LVDS2N_3P, DQ0D42
IO, LVDS2N_4N, DQSN0E40
IO, LVDS2N_4P, DQS0E41
IO, LVDS2N_5N, DQ0F40
IO, LVDS2N_5P, DQ0E39
IO, LVDS2N_6N, DQ0F39
IO, LVDS2N_6P, DQ0F38
IO, LVDS2N_7N, DQ1K37
IO, LVDS2N_7P, DQ1J37
IO, LVDS2N_8N, DQ1G38
IO, LVDS2N_8P, DQ1H39
IO, LVDS2N_9N, DQ1M37
IO, LVDS2N_9P, DQ1L37
IO, PLL_2N_CLKOUT1N, LVDS2N_10N, DQSN1J38
IO, PLL_2N_CLKOUT1P, PLL_2N_CLKOUT1, PLL_2N_FBN, LVDS2N_10P, DQS1H38
IO, LVDS2N_11N, DQ1P37
IO, RZQ_2N, LVDS2N_11P, DQ1R37
IO, CLK_2N_1N, LVDS2N_12N, DQ1N38
IO, CLK_2N_1P, LVDS2N_12P, DQ1P38
IO, CLK_2N_0N, LVDS2N_13N, DQ2J39
IO, CLK_2N_0P, LVDS2N_13P, DQ2K39
IO, LVDS2N_14N, DQ2L39
IO, LVDS2N_14P, DQ2L38
IO, PLL_2N_CLKOUT0N, LVDS2N_15N, DQ2G40
IO, PLL_2N_CLKOUT0P, PLL_2N_CLKOUT0, PLL_2N_FBP, PLL_2N_FB0, LVDS2N_15P, DQ2H40
IO, LVDS2N_16N, DQSN2F42
IO, LVDS2N_16P, DQS2E42
IO, LVDS2N_17N, DQ2G41
IO, LVDS2N_17P, DQ2H41
IO, LVDS2N_18N, DQ2H42
IO, LVDS2N_18P, DQ2G42
IO, LVDS2N_19N, DQ3M38
IO, LVDS2N_19P, DQ3N39
IO, LVDS2N_20N, DQ3P39
IO, LVDS2N_20P, DQ3R39
IO, LVDS2N_21N, DQ3T38
IO, LVDS2N_21P, DQ3T39
IO, LVDS2N_22N, DQSN3T37
IO, LVDS2N_22P, DQS3U37
IO, LVDS2N_23N, DQ3W39
IO, LVDS2N_23P, DQ3V39
IO, LVDS2N_24N, DQ3U38
IO, LVDS2N_24P, DQ3V38
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HILO Memory Interface Connector Map
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
17 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
17 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
17 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MEMORY INTERFACE
POWER CONTROL
HiLo Connector
Place near HILOconnector VDD pins
Place near HILOconnector VDDQ pins
MEM_DQA15 MEM_DQB15MEM_DQA16 MEM_DQB16MEM_DQA17 MEM_DQB17MEM_DQA18 MEM_DQB18MEM_DQA19 MEM_DQB19MEM_DQA20 MEM_DQB20MEM_DQA21 MEM_DQB21MEM_DQA22 MEM_DQB22MEM_DQA23 MEM_DQB23MEM_DQA24 MEM_DQB24MEM_DQA25 MEM_DQB25MEM_DQA26 MEM_DQB26
MEM_ADDR_CMD0
MEM_DQA27
HILO_VDD_1p35V_SET
MEM_DQB27
HILO_VDD_1p5V_SET
HILO_VDDQ_1p35V_SETHILO_VDDQ_1p5V_SET
MEM_DQA28 MEM_DQB28MEM_DQA29 MEM_DQB29MEM_DQA30 MEM_DQB30MEM_DQA31 MEM_DQB31MEM_DQA32 MEM_DQB32MEM_DQA33 MEM_DQB33
MEM_DQSA_P0 MEM_DQSB_P0MEM_DQSA_N0 MEM_DQSB_N0MEM_DQSA_P1MEM_DQSA_N1 MEM_DQSB_N1
MEM_DQSB_P1
MEM_DQSB_N2MEM_DQSA_P2MEM_DQSA_N2
MEM_DQSB_P2
MEM_DQSB_N3MEM_DQSA_P3MEM_DQSA_N3
MEM_DQSB_P3
MEM_QKA_P0MEM_QKA_P1
MEM_QKB_P0MEM_QKB_P1
MEM_DQ_ADDR_CMD0MEM_ADDR_CMD1 MEM_DQ_ADDR_CMD1MEM_ADDR_CMD2 MEM_DQ_ADDR_CMD2MEM_ADDR_CMD3 MEM_DQ_ADDR_CMD3MEM_ADDR_CMD4 MEM_DQ_ADDR_CMD4MEM_ADDR_CMD5 MEM_DQ_ADDR_CMD5MEM_ADDR_CMD6 MEM_DQ_ADDR_CMD6MEM_ADDR_CMD7 MEM_DQ_ADDR_CMD7MEM_ADDR_CMD8 MEM_DQ_ADDR_CMD8MEM_ADDR_CMD9MEM_ADDR_CMD10MEM_ADDR_CMD11MEM_ADDR_CMD12MEM_ADDR_CMD13MEM_ADDR_CMD14MEM_ADDR_CMD15MEM_ADDR_CMD16MEM_ADDR_CMD17MEM_ADDR_CMD18MEM_ADDR_CMD19MEM_ADDR_CMD20MEM_ADDR_CMD21MEM_ADDR_CMD22MEM_ADDR_CMD23MEM_ADDR_CMD24MEM_ADDR_CMD25MEM_ADDR_CMD26MEM_ADDR_CMD27MEM_ADDR_CMD28MEM_ADDR_CMD29MEM_ADDR_CMD30MEM_ADDR_CMD31
MEM_DQS_ADDR_CMD_PMEM_DQS_ADDR_CMD_N
MEM_CLK_PMEM_CLK_N
MEM_DMA0 MEM_DMB0MEM_DMA1 MEM_DMB1MEM_DMA2 MEM_DMB2MEM_DMA3 MEM_DMB3
HILO_VDD_1p25V_SET
HILO_VDD_1p8V_SET
MEM_DQA0
HILO_VDDQ_1p25V_SET
HILO_VDDQ_1p8V_SET
MEM_DQB0MEM_DQA1 MEM_DQB1MEM_DQA2 MEM_DQB2MEM_DQA3 MEM_DQB3MEM_DQA4 MEM_DQB4MEM_DQA5 MEM_DQB5MEM_DQA6 MEM_DQB6MEM_DQA7 MEM_DQB7MEM_DQA8 MEM_DQB8MEM_DQA9 MEM_DQB9MEM_DQA10 MEM_DQB10MEM_DQA11 MEM_DQB11MEM_DQA12 MEM_DQB12MEM_DQA13 MEM_DQB13MEM_DQA14 MEM_DQB14
HILO_VDD_1p3V_SET
HILO_VDDQ_1p3V_SET
HILO_VDDQ
HILO_VDD 2p5V
3p3V
MEM_VREF
HILO_VDD
HILO_VDDQ
MEM_VREF
2p5V3p3V
MEM_DQA[33:0]20
MEM_DMA[3:0]20
MEM_DQSA_P[3:0]20
MEM_DQSA_N[3:0]20
MEM_DQ_ADDR_CMD[8:0]19
MEM_DQS_ADDR_CMD_P19MEM_DQS_ADDR_CMD_N19
MEM_QKA_P[1:0]20
MEM_DMB[3:0]19
MEM_DQB[33:0]19
MEM_DQSB_N[3:0]19
MEM_DQSB_P[3:0]19
MEM_QKB_P[1:0]19
MEM_ADDR_CMD[31:0]19
MEM_CLK_P19MEM_CLK_N19
HILO_VDD_1p25V_SET65
HILO_VDDQ_1p35V_SET64
HILO_VDDQ_1p8V_SET64HILO_VDDQ_1p5V_SET64
HILO_VDD_1p35V_SET65HILO_VDD_1p5V_SET65HILO_VDD_1p8V_SET65
HILO_VDDQ_1p25V_SET64
HILO_VDD_1p3V_SET65
HILO_VDDQ_1p3V_SET64
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
18 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
18 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
18 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C149
0.1uF
C142
0.1uF
C138
10uF
C140
1uF
C143
0.1uF
C152
0.1uF
C146
1uF
C144
10uFC155
0.1uF
C145
1uF C151
1uFC154
1uF
C150
10uF
C156 0.1uF
C141
0.1uF
HiLo EMI - GND
J2C
HLS-180324-B-12
GNDA1
GNDA5
GNDA9
GNDA13
GNDA17
GNDB3
GNDB7
GNDB11
GNDB15
GNDC1
GNDC5
GNDC6
GNDC8
GNDC10
GNDC12
GNDC14
GNDC17
GNDD3
GNDD7
GNDD9
GNDD11
GNDD13
GNDD15
GNDE1
GNDE5
GNDE6
GNDE8
GNDE10
GNDE12
GNDE14
GNDE17
GNDF3
GNDF7
GNDF9
GNDF11
GNDF13
GNDF15
GNDG1
GNDG5
GNDG6
GNDG8
GNDG10
GNDG12
GNDG14
GNDG17
GNDH3
GNDH7
GNDH9
GNDH11
GNDH13
GNDH15
GNDJ1
GNDJ5
GNDJ6
GNDJ8
GNDJ10
GNDJ12
GNDJ14
GNDJ17
GNDK3
GNDK7
GNDK9
GNDK11
GNDK13
GNDK15
GNDL1
GNDL5
GNDL8
GNDL10
GNDL12
GNDL14
GNDL17
GNDM3
GNDM7
GNDM9
GNDM11
GNDM13
GNDM15
GNDN1
GNDN5
GNDN8
GNDN10
GNDN12
GNDN14
GNDN17
GNDP3
GNDP6
GNDP7
GNDP9
GNDP11
GNDP13
GNDP15
GNDR1
GNDR5
GNDR9
GNDR10
GNDR13
GNDR17
GNDT3
GNDT7
GNDT11
GNDT15
GNDU1
GNDU5
GNDU9
GNDU13
GNDU17
GNDV3
GNDV7
GNDV11
GNDV15
C158 0.1uF
C153
10uF
C148
0.1uF
C160 0.1uF
C137
10uF
HiLo EMI - EMI SIGNALSJ2A
HLS-180324-B-12
MEM_CLK_PV1
MEM_CLK_NV2
MEM_ADDR_CMD0F1
MEM_ADDR_CMD1H1
MEM_ADDR_CMD2F2
MEM_ADDR_CMD3G2
MEM_ADDR_CMD4H2
MEM_ADDR_CMD5J2
MEM_ADDR_CMD6K2
MEM_ADDR_CMD7G3
MEM_ADDR_CMD8J3
MEM_ADDR_CMD9L3
MEM_ADDR_CMD10E4
MEM_ADDR_CMD11F4
MEM_ADDR_CMD12G4
MEM_ADDR_CMD13H4
MEM_ADDR_CMD14J4
MEM_ADDR_CMD15K4
MEM_ADDR_CMD16M1
MEM_ADDR_CMD17M2
MEM_ADDR_CMD18N2
MEM_ADDR_CMD19L4
MEM_ADDR_CMD20P5
MEM_ADDR_CMD21M5
MEM_ADDR_CMD22P1
MEM_ADDR_CMD23R4
MEM_ADDR_CMD24M4
MEM_ADDR_CMD25R3
MEM_ADDR_CMD26L2
MEM_ADDR_CMD27K1
MEM_ADDR_CMD28P2
MEM_ADDR_CMD29N4
MEM_ADDR_CMD30P4
MEM_DQS_ADDR_CMD_PV4
MEM_DQS_ADDR_CMD_NV5
MEM_DQ_ADDR_CMD0R6
MEM_DQ_ADDR_CMD1T1
MEM_DQ_ADDR_CMD2R2
MEM_DQ_ADDR_CMD3T2
MEM_DQ_ADDR_CMD4U2
MEM_DQ_ADDR_CMD5U3
MEM_DQ_ADDR_CMD6T4
MEM_DQ_ADDR_CMD7U4
MEM_DQ_ADDR_CMD8T5
MEM_DMA0B10
MEM_DMA1C4
MEM_DMA2B17
MEM_DMA3F17
MEM_DQA0A4
MEM_DQA1B4
MEM_DQA2B5
MEM_DQA3B6
MEM_DQA4A8
MEM_DQA5B8
MEM_DQA6B9
MEM_DQA7A10
MEM_DQA8B1
MEM_DQA9B2
MEM_DQA10C2
MEM_DQA11C3
MEM_DQA12E3
MEM_DQA13D4
MEM_DQA14D1
MEM_DQA15D2
MEM_DQA16A12
MEM_DQA17B12
MEM_DQA18B13
MEM_DQA19B14
MEM_DQA20C15
MEM_DQA21A16
MEM_DQA22B16
MEM_DQA23A18
MEM_DQA24C16
MEM_DQA25D16
MEM_DQA26E16
MEM_DQA27F16
MEM_DQA28D17
MEM_DQA29C18
MEM_DQA30D18
MEM_DQA31E18
MEM_DQA32E2
MEM_DQA33G16
MEM_DQSA_P0A6
MEM_DQSA_P1A2
MEM_DQSA_P2A14
MEM_DQSA_P3F18
MEM_DQSA_N0A7
MEM_DQSA_N1A3
MEM_DQSA_N2A15
MEM_DQSA_N3G18
MEM_QKA_N0A11
MEM_DQSB_N0J18
MEM_DQSB_N1V18
MEM_DQSB_N2V17
MEM_DQSB_N3V9
MEM_DQSB_P0H18
MEM_DQSB_P1U18
MEM_DQSB_P2V16
MEM_DQSB_P3V8
MEM_QKB_N0M18
MEM_DMB0M16
MEM_DMB1U16
MEM_DMB2U11
MEM_DMB3U6
MEM_DQB0H16
MEM_DQB1J16
MEM_DQB2K16
MEM_DQB3L16
MEM_DQB4H17
MEM_DQB5K17
MEM_DQB6K18
MEM_DQB7L18
MEM_DQB8M17
MEM_DQB9N18
MEM_DQB10P17
MEM_DQB11P18
MEM_DQB12R18
MEM_DQB13T16
MEM_DQB14T17
MEM_DQB15T18
MEM_DQB16U15
MEM_DQB17T14
MEM_DQB18U14
MEM_DQB19V14
MEM_DQB20T13
MEM_DQB21T12
MEM_DQB22U12
MEM_DQB23V12
MEM_DQB24T10
MEM_DQB25U10
MEM_DQB26V10
MEM_DQB27T9
MEM_DQB28T8
MEM_DQB29U8
MEM_DQB30U7
MEM_DQB31V6
MEM_DQB32R16
MEM_DQB33T6
CONFIG0L6
CONFIG1M6
VDD_1.25V_SETD5
VDDQ_1.25V_SETF5
RFU2H5
RFU3K5
RFU4N6
RFU5R7
MEM_ADDR_CMD31N3
MEM_QKA_N1B18
MEM_QKB_N1V13
RFU6R8
HiLo EMI - POWER
VDD = 1.2(DEFAULT)(1.2V, 1.25V, 1.35V, 1.8V)
VDDQ = 1.2(DEFAULT)(1.1V,1.2V, 1.25V,1.35V, 1.8V)
VEXT = 2.5V
J2B
HLS-180324-B-12
VDDC7
VDDC9
VDDC11
VDDC13
VDDD6
VDDD8
VDDD10
VDDD12
VDDD14
VDDE7
VDDE9
VDDE11
VDDE13
VDDF6
VDDF8
VDDF10
VDDQF12
VDDQF14
VDDQG7
VDDQG9
VDDQG11
VDDQG13
VDDQH6
VDDQH8
VDDQH10
VDDQH12
VEXTL11
VEXTL13
VEXTM8
VEXTM10
VEXTM12
VEXTM14
VEXTN7
VEXTN9
VEXTN11
VEXTN13
VEXTP8
VEXTP10
VEXTP12
VEXTP14
2.5V/3.3V (VTT)J7
2.5V/3.3V (VTT)J9
2.5V/3.3V (VTT)K6
2.5V/3.3V (VTT)K8
2.5V/3.3V (VTT)L7
2.5V/3.3V (VTT)L9
VREFH14
2.5V/3.3V (VTT)J11
VREFJ13
2.5V/3.3V (VTT)K10
2.5V/3.3V (VTT)K12
VREFK14
VDD_1.2V_SETG15
VDD_1.30V_SETE15
VDD_1.35V_SETJ15
VDD_1.5V_SETL15
VDD_1.8V_SETN16
VDDQ_1.8V_SETR11
VDDQ_1.35V_SETR14 VDDQ_1.30V_SETR15 VDDQ_1.2V_SETP16
VDDQ_1.5V_SETR12
VDDQ_1.1V_SETN15
C139
1uF
C147
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HiLo Interface - FPGA Side 2B/2C
MEMORY INTERFACE
LB_REF_N0 -->LB_REF_P0 -->
LB_REF_N1 -->LB_REF_P1 -->
QDRII K_N/QDR4 QKB_N -->
LB_BN1_x36N -->LB_BN1_x36P -->
QDR4 QKB_N (NEW) -->QDR4 QKB_P (NEW) -->
QDRII K_P/QDR4 QKB_P -->
MEM_DQS_ADDR_CMD_PMEM_DQS_ADDR_CMD_N
MEM_DQ_ADDR_CMD4MEM_DQ_ADDR_CMD3MEM_DQ_ADDR_CMD0MEM_DQ_ADDR_CMD2MEM_DQ_ADDR_CMD1MEM_DQ_ADDR_CMD5
CLK_HILO_MEM_P CLK_HILO_MEM_N
MEM_DQB24
MEM_DQB29
MEM_DQB28MEM_DQSB_P3MEM_DQSB_N3
MEM_DQB26
MEM_DMB3MEM_DQB33
MEM_DQB0MEM_DQB7
MEM_DQB1
MEM_QKB_P0
MEM_DQB3MEM_DQSB_P0MEM_DQSB_N0
MEM_DQB4
MEM_DQB6MEM_DQB2
MEM_DMB0MEM_DQB5
MEM_DQB12MEM_DQB15
MEM_DQB9
MEM_DQB14MEM_DQSB_P1MEM_DQSB_N1
MEM_DQB8
MEM_DQB11MEM_DQB10
MEM_DQB32
MEM_DQB23
MEM_DQB19
MEM_QKB_P1
MEM_DQSB_P2MEM_DQSB_N2
MEM_DQB16
MEM_DQB17MEM_DQB18
MEM_ADDR_CMD28MEM_ADDR_CMD27MEM_ADDR_CMD22MEM_ADDR_CMD23MEM_ADDR_CMD24
MEM_ADDR_CMD20
MEM_CLK_PMEM_CLK_N
MEM_ADDR_CMD0MEM_ADDR_CMD1MEM_ADDR_CMD2MEM_ADDR_CMD3MEM_ADDR_CMD4MEM_ADDR_CMD5MEM_ADDR_CMD6MEM_ADDR_CMD7MEM_ADDR_CMD8MEM_ADDR_CMD9MEM_ADDR_CMD10MEM_ADDR_CMD11
MEM_ADDR_CMD12MEM_ADDR_CMD13MEM_ADDR_CMD14
MEM_ADDR_CMD26MEM_ADDR_CMD19MEM_ADDR_CMD16MEM_ADDR_CMD17MEM_ADDR_CMD18
MEM_ADDR_CMD25
MEM_ADDR_CMD21
MEM_ADDR_CMD15
MEM_ADDR_CMD30MEM_ADDR_CMD31
MEM_ADDR_CMD29MEM_DQ_ADDR_CMD8MEM_DQ_ADDR_CMD7MEM_DQ_ADDR_CMD6
HiLo_MEM_RZQ
MEM_DMB1
MEM_DQB13
MEM_DMB2MEM_DQB20
MEM_DQB22MEM_DQB21
MEM_DQB27MEM_DQB25
MEM_DQB31MEM_DQB30
CLK_HILO_MEM_P 41CLK_HILO_MEM_N 41
MEM_DQA[33:0]18,20
MEM_DMA[3:0]18,20
MEM_DQSA_P[3:0]18,20
MEM_DQSA_N[3:0]18,20
MEM_DQ_ADDR_CMD[8:0]18
MEM_DQS_ADDR_CMD_P18MEM_DQS_ADDR_CMD_N18
MEM_QKA_P[1:0]18,20
MEM_DMB[3:0]18
MEM_DQB[33:0]18
MEM_DQSB_N[3:0]18
MEM_DQSB_P[3:0]18
MEM_QKB_P[1:0]18
MEM_ADDR_CMD[31:0]18
MEM_CLK_P18MEM_CLK_N18
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
19 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
19 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
19 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
IO BANK 2C
1SM210H_UF53
U2I
IO, LVDS2C_1N, DQ20BL24
IO, LVDS2C_1P, DQ20BL25
IO, LVDS2C_2N, DQ20BJ24
IO, LVDS2C_2P, DQ20BK24
IO, LVDS2C_3N, DQ20BH26
IO, LVDS2C_3P, DQ20BJ26
IO, LVDS2C_4N, DQSN20BK25
IO, LVDS2C_4P, DQS20BK26
IO, LVDS2C_5N, DQ20BF27
IO, LVDS2C_5P, DQ20BE27
IO, LVDS2C_6N, DQ20BG27
IO, LVDS2C_6P, DQ20BG26
IO, LVDS2C_7N, DQ21BL27
IO, LVDS2C_7P, DQ21BL28
IO, LVDS2C_8N, DQ21BJ27
IO, LVDS2C_8P, DQ21BK27
IO, LVDS2C_9N, DQ21BF28
IO, LVDS2C_9P, DQ21BG28
IO, PLL_2C_CLKOUT1N, LVDS2C_10N, DQSN21BH28
IO, PLL_2C_CLKOUT1P, PLL_2C_CLKOUT1, PLL_2C_FBN, LVDS2C_10P, DQS21BJ28
IO, LVDS2C_11N, DQ21BB28
IO, RZQ_2C, LVDS2C_11P, DQ21BC28
IO, CLK_2C_1N, LVDS2C_12N, DQ21BD27
IO, CLK_2C_1P, LVDS2C_12P, DQ21BD28
IO, CLK_2C_0N, LVDS2C_13N, DQ22BC29
IO, CLK_2C_0P, LVDS2C_13P, DQ22BD29
IO, LVDS2C_14N, DQ22BA29
IO, LVDS2C_14P, DQ22BA28
IO, PLL_2C_CLKOUT0N, LVDS2C_15N, DQ22BH29
IO, PLL_2C_CLKOUT0P, PLL_2C_CLKOUT0, PLL_2C_FBP, PLL_2C_FB0, LVDS2C_15P, DQ22BJ29
IO, LVDS2C_16N, DQSN22BE29
IO, LVDS2C_16P, DQS22BF29
IO, LVDS2C_17N, DQ22BL30
IO, LVDS2C_17P, DQ22BK30
IO, LVDS2C_18N, DQ22BL29
IO, LVDS2C_18P, DQ22BK29
IO, LVDS2C_19N, DQ23BE30
IO, LVDS2C_19P, DQ23BF30
IO, LVDS2C_20N, DQ23BG30
IO, LVDS2C_20P, DQ23BH30
IO, LVDS2C_21N, DQ23BA30
IO, LVDS2C_21P, DQ23AY30
IO, LVDS2C_22N, DQSN23BC30
IO, LVDS2C_22P, DQS23BB30
IO, LVDS2C_23N, DQ23AV29
IO, LVDS2C_23P, DQ23AV30
IO, LVDS2C_24N, DQ23AY29
IO, LVDS2C_24P, DQ23AW29
IO BANK 2B
1SM210H_UF53
U2J
IO, LVDS2B_1N, DQ24BC31
IO, LVDS2B_1P, DQ24BB31
IO, LVDS2B_2N, DQ24BE31
IO, LVDS2B_2P, DQ24BD31
IO, LVDS2B_3N, DQ24BG31
IO, LVDS2B_3P, DQ24BH31
IO, LVDS2B_4N, DQSN24BJ31
IO, LVDS2B_4P, DQS24BK31
IO, LVDS2B_5N, DQ24BK32
IO, LVDS2B_5P, DQ24BJ32
IO, LVDS2B_6N, DQ24BL33
IO, LVDS2B_6P, DQ24BL32
IO, LVDS2B_7N, DQ25BD32
IO, LVDS2B_7P, DQ25BE32
IO, LVDS2B_8N, DQ25BF32
IO, LVDS2B_8P, DQ25BG32
IO, LVDS2B_9N, DQ25AY32
IO, LVDS2B_9P, DQ25AW32
IO, PLL_2B_CLKOUT1N, LVDS2B_10N, DQSN25BA32
IO, PLL_2B_CLKOUT1P, PLL_2B_CLKOUT1, PLL_2B_FBN, LVDS2B_10P, DQS25BB32
IO, LVDS2B_11N, DQ25BB33
IO, RZQ_2B, LVDS2B_11P, DQ25BA33
IO, CLK_2B_1N, LVDS2B_12N, DQ25AY31
IO, CLK_2B_1P, LVDS2B_12P, DQ25AW31
IO, CLK_2B_0N, LVDS2B_13N, DQ26BF33
IO, CLK_2B_0P, LVDS2B_13P, DQ26BG33
IO, LVDS2B_14N, DQ26BC33
IO, LVDS2B_14P, DQ26BD33
IO, PLL_2B_CLKOUT0N, LVDS2B_15N, DQ26BL35
IO, PLL_2B_CLKOUT0P, PLL_2B_CLKOUT0, PLL_2B_FBP, PLL_2B_FB0, LVDS2B_15P, DQ26BK35
IO, LVDS2B_16N, DQSN26BJ33
IO, LVDS2B_16P, DQS26BH33
IO, LVDS2B_17N, DQ26BH34
IO, LVDS2B_17P, DQ26BJ34
IO, LVDS2B_18N, DQ26BK34
IO, LVDS2B_18P, DQ26BL34
IO, LVDS2B_19N, DQ27BH35
IO, LVDS2B_19P, DQ27BG35
IO, LVDS2B_20N, DQ27BE34
IO, LVDS2B_20P, DQ27BF34
IO, LVDS2B_21N, DQ27BC34
IO, LVDS2B_21P, DQ27BD34
IO, LVDS2B_22N, DQSN27AY34
IO, LVDS2B_22P, DQS27BA34
IO, LVDS2B_23N, DQ27AV34
IO, LVDS2B_23P, DQ27AW34
IO, LVDS2B_24N, DQ27AW33
IO, LVDS2B_24P, DQ27AV33
R55169 (1%)
R56240
J3
CON2
12
XJ1
881545-2
R57 100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HiLo Interface - FPGA Side 2A
MEMORY INTERFACE
QDRII CQn -->QDRII CQp -->
QDR4 QKA_N (NEW) -->QDR4 QKA_P (NEW) -->
QDR4 QKA_N (NEW) -->QDR4 QKA_P (NEW) -->
MEM_DQA24MEM_DQA25
MEM_DQA31
MEM_DQA26
MEM_DQA28MEM_DQSA_P3MEM_DQSA_N3
MEM_DQA27
MEM_DMA3MEM_DQA33
MEM_DQA0MEM_DQA7
MEM_DQA4
MEM_QKA_P0
MEM_DQA2MEM_DQSA_P0MEM_DQSA_N0
MEM_DQA5
MEM_DQA1MEM_DQA3
MEM_DMA0MEM_DQA6
MEM_DQA15MEM_DQA32
MEM_DQA10
MEM_DQA14
MEM_DQA8MEM_DQSA_P1MEM_DQSA_N1
MEM_DQA9
MEM_DQA11MEM_DQA13
MEM_DQA20MEM_DQA23
MEM_DQA21
MEM_QKA_P1
MEM_DQA19MEM_DQSA_P2MEM_DQSA_N2
MEM_DQA22
MEM_DQA17MEM_DQA18
MEM_DMA2MEM_DQA16
MEM_DQA12MEM_DMA1
MEM_DQA29MEM_DQA30
MEM_DQA[33:0]18
MEM_DMA[3:0]18
MEM_DQSA_P[3:0]18
MEM_DQSA_N[3:0]18
MEM_QKA_P[1:0]18
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
20 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
20 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
20 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
IO BANK 2A
1SM210H_UF53
U2K
IO, LVDS2A_1N, DQ28BF40
IO, LVDS2A_1P, DQ28BE40
IO, LVDS2A_2N, DQ28BH40
IO, LVDS2A_2P, DQ28BG40
IO, LVDS2A_3N, DQ28BL40
IO, LVDS2A_3P, DQ28BK40
IO, LVDS2A_4N, DQSN28BL39
IO, LVDS2A_4P, DQS28BK39
IO, LVDS2A_5N, DQ28BH39
IO, LVDS2A_5P, DQ28BJ39
IO, LVDS2A_6N, DQ28BE39
IO, LVDS2A_6P, DQ28BF39
IO, LVDS2A_7N, DQ29BD39
IO, LVDS2A_7P, DQ29BC39
IO, LVDS2A_8N, DQ29BD38
IO, LVDS2A_8P, DQ29BC38
IO, LVDS2A_9N, DQ29BG38
IO, LVDS2A_9P, DQ29BF38
IO, PLL_2A_CLKOUT1N, LVDS2A_10N, DQSN29BJ38
IO, PLL_2A_CLKOUT1P, PLL_2A_CLKOUT1, PLL_2A_FBN, LVDS2A_10P, DQS29BH38
IO, LVDS2A_11N, DQ29BL38
IO, RZQ_2A, LVDS2A_11P, DQ29BL37
IO, CLK_2A_1N, LVDS2A_12N, DQ29BK37
IO, CLK_2A_1P, LVDS2A_12P, DQ29BJ37
IO, CLK_2A_0N, LVDS2A_13N, DQ30BE37
IO, CLK_2A_0P, LVDS2A_13P, DQ30BD37
IO, LVDS2A_14N, DQ30BF37
IO, LVDS2A_14P, DQ30BG37
IO, PLL_2A_CLKOUT0N, LVDS2A_15N, DQ30AY37
IO, PLL_2A_CLKOUT0P, PLL_2A_CLKOUT0, PLL_2A_FBP, PLL_2A_FB0, LVDS2A_15P, DQ30AW37
IO, LVDS2A_16N, DQSN30BB37
IO, LVDS2A_16P, DQS30BA37
IO, LVDS2A_17N, DQ30BB36
IO, LVDS2A_17P, DQ30BC36
IO, LVDS2A_18N, DQ30AW36
IO, LVDS2A_18P, DQ30AY36
IO, LVDS2A_19N, DQ31BH36
IO, LVDS2A_19P, DQ31BG36
IO, LVDS2A_20N, DQ31BE36
IO, LVDS2A_20P, DQ31BD36
IO, LVDS2A_21N, DQ31BF35
IO, LVDS2A_21P, DQ31BE35
IO, LVDS2A_22N, DQSN31BK36
IO, LVDS2A_22P, DQS31BJ36
IO, LVDS2A_23N, DQ31AY35
IO, LVDS2A_23P, DQ31BA35
IO, LVDS2A_24N, DQ31BB35
IO, LVDS2A_24P, DQ31BC35
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XCVR BANK 1K 1L 1M 1N
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
21 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
21 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
21 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
XCVR BANK 1M
XCVR BANK 1L
XCVR BANK 1K
XCVR BANK 1N
1SM210H_UF53
U2A
REFCLK_GXBL1N_CHTPL43
REFCLK_GXBL1N_CHTNL42
GXBL1N_TX_CH5ND49
GXBL1N_TX_CH5PD48
GXBL1N_RX_CH5N, GXBL1N_REFCLK5NA46
GXBL1N_RX_CH5P, GXBL1N_REFCLK5PA47
GXBL1N_TX_CH4NB50
GXBL1N_TX_CH4PC50
GXBL1N_RX_CH4N, GXBL1N_REFCLK4NA44
GXBL1N_RX_CH4P, GXBL1N_REFCLK4PB44
GXBL1N_TX_CH3ND51
GXBL1N_TX_CH3PE51
GXBL1N_RX_CH3N, GXBL1N_REFCLK3ND44
GXBL1N_RX_CH3P, GXBL1N_REFCLK3PD45
GXBL1N_TX_CH2NB48
GXBL1N_TX_CH2PA48
GXBL1N_RX_CH2N, GXBL1N_REFCLK2NC46
GXBL1N_RX_CH2P, GXBL1N_REFCLK2PC47
GXBL1N_TX_CH1NG50
GXBL1N_TX_CH1PG51
GXBL1N_RX_CH1N, GXBL1N_REFCLK1NF44
GXBL1N_RX_CH1P, GXBL1N_REFCLK1PF45
GXBL1N_TX_CH0NJ50
GXBL1N_TX_CH0PJ51
GXBL1N_RX_CH0N, GXBL1N_REFCLK0NH44
GXBL1N_RX_CH0P, GXBL1N_REFCLK0PH45
REFCLK_GXBL1N_CHBPN43
REFCLK_GXBL1N_CHBNN42
REFCLK_GXBL1M_CHTPR43
REFCLK_GXBL1M_CHTNR42
GXBL1M_TX_CH5NF48
GXBL1M_TX_CH5PF49
GXBL1M_RX_CH5N, GXBL1M_REFCLK5NE46
GXBL1M_RX_CH5P, GXBL1M_REFCLK5PE47
GXBL1M_TX_CH4NH48
GXBL1M_TX_CH4PH49
GXBL1M_RX_CH4N, GXBL1M_REFCLK4NG46
GXBL1M_RX_CH4P, GXBL1M_REFCLK4PG47
GXBL1M_TX_CH3NK48
GXBL1M_TX_CH3PK49
GXBL1M_RX_CH3N, GXBL1M_REFCLK3NK44
GXBL1M_RX_CH3P, GXBL1M_REFCLK3PK45
GXBL1M_TX_CH2NL50
GXBL1M_TX_CH2PL51
GXBL1M_RX_CH2N, GXBL1M_REFCLK2NJ46
GXBL1M_RX_CH2P, GXBL1M_REFCLK2PJ47
GXBL1M_TX_CH1NM48
GXBL1M_TX_CH1PM49
GXBL1M_RX_CH1N, GXBL1M_REFCLK1NM44
GXBL1M_RX_CH1P, GXBL1M_REFCLK1PM45
GXBL1M_TX_CH0NN50
GXBL1M_TX_CH0PN51
GXBL1M_RX_CH0N, GXBL1M_REFCLK0NL46
GXBL1M_RX_CH0P, GXBL1M_REFCLK0PL47
REFCLK_GXBL1M_CHBPU43
REFCLK_GXBL1M_CHBNU42
REFCLK_GXBL1L_CHTPW43
REFCLK_GXBL1L_CHTNW42
GXBL1L_TX_CH5NP48
GXBL1L_TX_CH5PP49
GXBL1L_RX_CH5N, GXBL1L_REFCLK5NP44
GXBL1L_RX_CH5P, GXBL1L_REFCLK5PP45
GXBL1L_TX_CH4NR50
GXBL1L_TX_CH4PR51
GXBL1L_RX_CH4N, GXBL1L_REFCLK4NN46
GXBL1L_RX_CH4P, GXBL1L_REFCLK4PN47
GXBL1L_TX_CH3NT48
GXBL1L_TX_CH3PT49
GXBL1L_RX_CH3N, GXBL1L_REFCLK3NT44
GXBL1L_RX_CH3P, GXBL1L_REFCLK3PT45
GXBL1L_TX_CH2NU50
GXBL1L_TX_CH2PU51
GXBL1L_RX_CH2N, GXBL1L_REFCLK2NR46
GXBL1L_RX_CH2P, GXBL1L_REFCLK2PR47
GXBL1L_TX_CH1NV48
GXBL1L_TX_CH1PV49
GXBL1L_RX_CH1N, GXBL1L_REFCLK1NV44
GXBL1L_RX_CH1P, GXBL1L_REFCLK1PV45
GXBL1L_TX_CH0NW50
GXBL1L_TX_CH0PW51
GXBL1L_RX_CH0N, GXBL1L_REFCLK0NU46
GXBL1L_RX_CH0P, GXBL1L_REFCLK0PU47
REFCLK_GXBL1L_CHBPAA43
REFCLK_GXBL1L_CHBNAA42
REFCLK_GXBL1K_CHTPAC43
REFCLK_GXBL1K_CHTNAC42
GXBL1K_TX_CH5NY48
GXBL1K_TX_CH5PY49
GXBL1K_RX_CH5N, GXBL1K_REFCLK5NY44
GXBL1K_RX_CH5P, GXBL1K_REFCLK5PY45
GXBL1K_TX_CH4NAA50
GXBL1K_TX_CH4PAA51
GXBL1K_RX_CH4N, GXBL1K_REFCLK4NW46
GXBL1K_RX_CH4P, GXBL1K_REFCLK4PW47
GXBL1K_TX_CH3NAB48
GXBL1K_TX_CH3PAB49
GXBL1K_RX_CH3N, GXBL1K_REFCLK3NAB44
GXBL1K_RX_CH3P, GXBL1K_REFCLK3PAB45
GXBL1K_TX_CH2NAC50
GXBL1K_TX_CH2PAC51
GXBL1K_RX_CH2N, GXBL1K_REFCLK2NAA46
GXBL1K_RX_CH2P, GXBL1K_REFCLK2PAA47
GXBL1K_TX_CH1NAD48
GXBL1K_TX_CH1PAD49
GXBL1K_RX_CH1N, GXBL1K_REFCLK1NAD44
GXBL1K_RX_CH1P, GXBL1K_REFCLK1PAD45
GXBL1K_TX_CH0NAE50
GXBL1K_TX_CH0PAE51
GXBL1K_RX_CH0N, GXBL1K_REFCLK0NAC46
GXBL1K_RX_CH0P, GXBL1K_REFCLK0PAC47
REFCLK_GXBL1K_CHBPAE43
REFCLK_GXBL1K_CHBNAE42
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XCVR BANK 1C 1D 1E 1FPCIe Endpoint / zQSFP0
PCIE_EP_TX_P0PCIE_EP_TX_N0PCIE_EP_TX_P1PCIE_EP_TX_N1PCIE_EP_TX_P2PCIE_EP_TX_N2PCIE_EP_TX_P3PCIE_EP_TX_N3PCIE_EP_TX_P4PCIE_EP_TX_N4PCIE_EP_TX_P5PCIE_EP_TX_N5
PCIE_EP_RX_P0PCIE_EP_RX_N0PCIE_EP_RX_P1PCIE_EP_RX_N1PCIE_EP_RX_P2PCIE_EP_RX_N2PCIE_EP_RX_P3PCIE_EP_RX_N3PCIE_EP_RX_P4PCIE_EP_RX_N4PCIE_EP_RX_P5PCIE_EP_RX_N5
PCIE_EP_TX_P6PCIE_EP_TX_N6PCIE_EP_TX_P7PCIE_EP_TX_N7PCIE_EP_TX_P8PCIE_EP_TX_N8PCIE_EP_TX_P9PCIE_EP_TX_N9PCIE_EP_TX_P10PCIE_EP_TX_N10PCIE_EP_TX_P11PCIE_EP_TX_N11
PCIE_EP_RX_P6PCIE_EP_RX_N6PCIE_EP_RX_P7PCIE_EP_RX_N7PCIE_EP_RX_P8PCIE_EP_RX_N8PCIE_EP_RX_P9PCIE_EP_RX_N9PCIE_EP_RX_P10PCIE_EP_RX_N10PCIE_EP_RX_P11PCIE_EP_RX_N11
PCIE_EP_TX_P12PCIE_EP_TX_N12PCIE_EP_TX_P13PCIE_EP_TX_N13PCIE_EP_TX_P14PCIE_EP_TX_N14PCIE_EP_TX_P15PCIE_EP_TX_N15
PCIE_EP_RX_P12PCIE_EP_RX_N12PCIE_EP_RX_P13PCIE_EP_RX_N13PCIE_EP_RX_P14PCIE_EP_RX_N14PCIE_EP_RX_P15PCIE_EP_RX_N15
ZQSFP0_RX0_PZQSFP0_RX0_NZQSFP0_RX1_PZQSFP0_RX1_N
ZQSFP0_TX0_PZQSFP0_TX0_NZQSFP0_TX1_PZQSFP0_TX1_N
REFCLK_PCIE_EP_PREFCLK_PCIE_EP_N
REFCLK_PCIE_EP_EDGE_PREFCLK_PCIE_EP_EDGE_N
REFCLK_ZQSFP0_PREFCLK_ZQSFP0_N
REFCLK_PCIE_EP1_PREFCLK_PCIE_EP1_N
ZQSFP0_TX2_NZQSFP0_TX2_PZQSFP0_TX3_NZQSFP0_TX3_P
ZQSFP0_RX2_NZQSFP0_RX2_PZQSFP0_RX3_NZQSFP0_RX3_P
PCIE_EP_TX_N0 27PCIE_EP_TX_P0 27
PCIE_EP_TX_N1 27PCIE_EP_TX_P1 27
PCIE_EP_TX_N2 27PCIE_EP_TX_P2 27
PCIE_EP_TX_N3 27PCIE_EP_TX_P3 27
PCIE_EP_TX_N4 27PCIE_EP_TX_P4 27
PCIE_EP_TX_N5 27PCIE_EP_TX_P5 27
PCIE_EP_RX_P0 27PCIE_EP_RX_N0 27PCIE_EP_RX_P1 27PCIE_EP_RX_N1 27PCIE_EP_RX_P2 27PCIE_EP_RX_N2 27PCIE_EP_RX_P3 27PCIE_EP_RX_N3 27PCIE_EP_RX_P4 27PCIE_EP_RX_N4 27PCIE_EP_RX_P5 27PCIE_EP_RX_N5 27
PCIE_EP_TX_N6 27PCIE_EP_TX_P6 27
PCIE_EP_TX_N7 27PCIE_EP_TX_P7 27
PCIE_EP_TX_N8 27PCIE_EP_TX_P8 27
PCIE_EP_TX_N9 27PCIE_EP_TX_P9 27
PCIE_EP_TX_N10 27PCIE_EP_TX_P10 27
PCIE_EP_TX_N11 27PCIE_EP_TX_P11 27
PCIE_EP_RX_P6 27PCIE_EP_RX_N6 27PCIE_EP_RX_P7 27PCIE_EP_RX_N7 27PCIE_EP_RX_P8 27PCIE_EP_RX_N8 27PCIE_EP_RX_P9 27PCIE_EP_RX_N9 27PCIE_EP_RX_P10 27PCIE_EP_RX_N10 27PCIE_EP_RX_P11 27PCIE_EP_RX_N11 27
PCIE_EP_TX_P1227PCIE_EP_TX_N1227PCIE_EP_TX_P1327PCIE_EP_TX_N1327PCIE_EP_TX_P1427PCIE_EP_TX_N1427PCIE_EP_TX_P1527PCIE_EP_TX_N1527
PCIE_EP_RX_P1227PCIE_EP_RX_N1227PCIE_EP_RX_P1327PCIE_EP_RX_N1327PCIE_EP_RX_P1427PCIE_EP_RX_N1427PCIE_EP_RX_P1527PCIE_EP_RX_N1527
ZQSFP0_RX0_P25ZQSFP0_RX0_N25ZQSFP0_RX1_P25ZQSFP0_RX1_N25
ZQSFP0_TX0_P25ZQSFP0_TX0_N25ZQSFP0_TX1_P25ZQSFP0_TX1_N25
REFCLK_PCIE_EP_P 40REFCLK_PCIE_EP_N 40
REFCLK_PCIE_EP_EDGE_P 27REFCLK_PCIE_EP_EDGE_N 27
REFCLK_ZQSFP0_N40REFCLK_ZQSFP0_P40
REFCLK_PCIE_EP1_P 41REFCLK_PCIE_EP1_N 41
ZQSFP0_TX2_N25ZQSFP0_TX2_P25ZQSFP0_TX3_N25ZQSFP0_TX3_P25
ZQSFP0_RX2_N25ZQSFP0_RX2_P25ZQSFP0_RX3_N25ZQSFP0_RX3_P25
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
22 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
22 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
22 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R60 DNI
R58 DNI
R59 DNI
XCVR BANK 1C
XCVR BANK 1D
XCVR BANK 1F
XCVR BANK 1E
1SM210H_UF53
U2B
REFCLK_GXBL1F_CHTPAG43
REFCLK_GXBL1F_CHTNAG42
GXBL1F_TX_CH5NAF48
GXBL1F_TX_CH5PAF49
GXBL1F_RX_CH5N, GXBL1F_REFCLK5NAE46
GXBL1F_RX_CH5P, GXBL1F_REFCLK5PAE47
GXBL1F_TX_CH4NAG50
GXBL1F_TX_CH4PAG51
GXBL1F_RX_CH4N, GXBL1F_REFCLK4NAF44
GXBL1F_RX_CH4P, GXBL1F_REFCLK4PAF45
GXBL1F_TX_CH3NAJ50
GXBL1F_TX_CH3PAJ51
GXBL1F_RX_CH3N, GXBL1F_REFCLK3NAH44
GXBL1F_RX_CH3P, GXBL1F_REFCLK3PAH45
GXBL1F_TX_CH2NAH48
GXBL1F_TX_CH2PAH49
GXBL1F_RX_CH2N, GXBL1F_REFCLK2NAG46
GXBL1F_RX_CH2P, GXBL1F_REFCLK2PAG47
GXBL1F_TX_CH1NAL50
GXBL1F_TX_CH1PAL51
GXBL1F_RX_CH1N, GXBL1F_REFCLK1NAK44
GXBL1F_RX_CH1P, GXBL1F_REFCLK1PAK45
GXBL1F_TX_CH0NAN50
GXBL1F_TX_CH0PAN51
GXBL1F_RX_CH0N, GXBL1F_REFCLK0NAM44
GXBL1F_RX_CH0P, GXBL1F_REFCLK0PAM45
REFCLK_GXBL1F_CHBPAJ43
REFCLK_GXBL1F_CHBNAJ42
REFCLK_GXBL1E_CHTPAL43
REFCLK_GXBL1E_CHTNAL42
GXBL1E_TX_CH5NAK48
GXBL1E_TX_CH5PAK49
GXBL1E_RX_CH5N, GXBL1E_REFCLK5NAJ46
GXBL1E_RX_CH5P, GXBL1E_REFCLK5PAJ47
GXBL1E_TX_CH4NAM48
GXBL1E_TX_CH4PAM49
GXBL1E_RX_CH4N, GXBL1E_REFCLK4NAL46
GXBL1E_RX_CH4P, GXBL1E_REFCLK4PAL47
GXBL1E_TX_CH3NAR50
GXBL1E_TX_CH3PAR51
GXBL1E_RX_CH3N, GXBL1E_REFCLK3NAP44
GXBL1E_RX_CH3P, GXBL1E_REFCLK3PAP45
GXBL1E_TX_CH2NAT48
GXBL1E_TX_CH2PAT49
GXBL1E_RX_CH2N, GXBL1E_REFCLK2NAR46
GXBL1E_RX_CH2P, GXBL1E_REFCLK2PAR47
GXBL1E_TX_CH1NAU50
GXBL1E_TX_CH1PAU51
GXBL1E_RX_CH1N, GXBL1E_REFCLK1NAT44
GXBL1E_RX_CH1P, GXBL1E_REFCLK1PAT45
GXBL1E_TX_CH0NAV48
GXBL1E_TX_CH0PAV49
GXBL1E_RX_CH0N, GXBL1E_REFCLK0NAU46
GXBL1E_RX_CH0P, GXBL1E_REFCLK0PAU47
REFCLK_GXBL1E_CHBPAN43
REFCLK_GXBL1E_CHBNAN42
REFCLK_GXBL1D_CHTPAR43
REFCLK_GXBL1D_CHTNAR42
GXBL1D_TX_CH5NAW50
GXBL1D_TX_CH5PAW51
GXBL1D_RX_CH5N, GXBL1D_REFCLK5NAV44
GXBL1D_RX_CH5P, GXBL1D_REFCLK5PAV45
GXBL1D_TX_CH4NAY48
GXBL1D_TX_CH4PAY49
GXBL1D_RX_CH4N, GXBL1D_REFCLK4NAW46
GXBL1D_RX_CH4P, GXBL1D_REFCLK4PAW47
GXBL1D_TX_CH3NBA50
GXBL1D_TX_CH3PBA51
GXBL1D_RX_CH3N, GXBL1D_REFCLK3NAY44
GXBL1D_RX_CH3P, GXBL1D_REFCLK3PAY45
GXBL1D_TX_CH2NBB48
GXBL1D_TX_CH2PBB49
GXBL1D_RX_CH2N, GXBL1D_REFCLK2NBA46
GXBL1D_RX_CH2P, GXBL1D_REFCLK2PBA47
GXBL1D_TX_CH1NBC50
GXBL1D_TX_CH1PBC51
GXBL1D_RX_CH1N, GXBL1D_REFCLK1NBC46
GXBL1D_RX_CH1P, GXBL1D_REFCLK1PBC47
GXBL1D_TX_CH0NBD48
GXBL1D_TX_CH0PBD49
GXBL1D_RX_CH0N, GXBL1D_REFCLK0NBB44
GXBL1D_RX_CH0P, GXBL1D_REFCLK0PBB45
REFCLK_GXBL1D_CHBPAU43
REFCLK_GXBL1D_CHBNAU42
REFCLK_GXBL1C_CHTPAW43
REFCLK_GXBL1C_CHTNAW42
GXBL1C_TX_CH5NBE50
GXBL1C_TX_CH5PBE51
GXBL1C_RX_CH5N, GXBL1C_REFCLK5NBD44
GXBL1C_RX_CH5P, GXBL1C_REFCLK5PBD45
GXBL1C_TX_CH4NBF48
GXBL1C_TX_CH4PBF49
GXBL1C_RX_CH4N, GXBL1C_REFCLK4NBE46
GXBL1C_RX_CH4P, GXBL1C_REFCLK4PBE47
GXBL1C_TX_CH3NBG50
GXBL1C_TX_CH3PBG51
GXBL1C_RX_CH3N, GXBL1C_REFCLK3NBF44
GXBL1C_RX_CH3P, GXBL1C_REFCLK3PBF45
GXBL1C_TX_CH2NBH48
GXBL1C_TX_CH2PBH49
GXBL1C_RX_CH2N, GXBL1C_REFCLK2NBG46
GXBL1C_RX_CH2P, GXBL1C_REFCLK2PBG47
GXBL1C_TX_CH1NBK48
GXBL1C_TX_CH1PBK49
GXBL1C_RX_CH1N, GXBL1C_REFCLK1NBJ46
GXBL1C_RX_CH1P, GXBL1C_REFCLK1PBJ47
GXBL1C_TX_CH0NBL46
GXBL1C_TX_CH0PBL47
GXBL1C_RX_CH0N, GXBL1C_REFCLK0NBH44
GXBL1C_RX_CH0P, GXBL1C_REFCLK0PBH45
REFCLK_GXBL1C_CHBPBA43
REFCLK_GXBL1C_CHBNBA42
R61 DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XCVR 4K 4L 4M 4N
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
23 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
23 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
23 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
XCVR BANK 4N
XCVR BANK 4K
XCVR BANK 4M
XCVR BANK 4L
1SM210H_UF53
U2C
REFCLK_GXBR4N_CHTPL9
REFCLK_GXBR4N_CHTNL10
GXBR4N_TX_CH5NB3
GXBR4N_TX_CH5PB2
GXBR4N_RX_CH5N, GXBR4N_REFCLK5NA6
GXBR4N_RX_CH5P, GXBR4N_REFCLK5PA5
GXBR4N_TX_CH4ND4
GXBR4N_TX_CH4PD3
GXBR4N_RX_CH4N, GXBR4N_REFCLK4NC6
GXBR4N_RX_CH4P, GXBR4N_REFCLK4PC5
GXBR4N_TX_CH3NE2
GXBR4N_TX_CH3PE1
GXBR4N_RX_CH3N, GXBR4N_REFCLK3ND8
GXBR4N_RX_CH3P, GXBR4N_REFCLK3PD7
GXBR4N_TX_CH2NF4
GXBR4N_TX_CH2PF3
GXBR4N_RX_CH2N, GXBR4N_REFCLK2NE6
GXBR4N_RX_CH2P, GXBR4N_REFCLK2PE5
GXBR4N_TX_CH1NG2
GXBR4N_TX_CH1PG1
GXBR4N_RX_CH1N, GXBR4N_REFCLK1NF8
GXBR4N_RX_CH1P, GXBR4N_REFCLK1PF7
GXBR4N_TX_CH0NH4
GXBR4N_TX_CH0PH3
GXBR4N_RX_CH0N, GXBR4N_REFCLK0NG6
GXBR4N_RX_CH0P, GXBR4N_REFCLK0PG5
REFCLK_GXBR4N_CHBPN9
REFCLK_GXBR4N_CHBNN10
REFCLK_GXBR4M_CHTPR9
REFCLK_GXBR4M_CHTNR10
GXBR4M_TX_CH5NJ2
GXBR4M_TX_CH5PJ1
GXBR4M_RX_CH5N, GXBR4M_REFCLK5NH8
GXBR4M_RX_CH5P, GXBR4M_REFCLK5PH7
GXBR4M_TX_CH4NK4
GXBR4M_TX_CH4PK3
GXBR4M_RX_CH4N, GXBR4M_REFCLK4NJ6
GXBR4M_RX_CH4P, GXBR4M_REFCLK4PJ5
GXBR4M_TX_CH3NL2
GXBR4M_TX_CH3PL1
GXBR4M_RX_CH3N, GXBR4M_REFCLK3NK8
GXBR4M_RX_CH3P, GXBR4M_REFCLK3PK7
GXBR4M_TX_CH2NM4
GXBR4M_TX_CH2PM3
GXBR4M_RX_CH2N, GXBR4M_REFCLK2NL6
GXBR4M_RX_CH2P, GXBR4M_REFCLK2PL5
GXBR4M_TX_CH1NN2
GXBR4M_TX_CH1PN1
GXBR4M_RX_CH1N, GXBR4M_REFCLK1NM8
GXBR4M_RX_CH1P, GXBR4M_REFCLK1PM7
GXBR4M_TX_CH0NP4
GXBR4M_TX_CH0PP3
GXBR4M_RX_CH0N, GXBR4M_REFCLK0NN6
GXBR4M_RX_CH0P, GXBR4M_REFCLK0PN5
REFCLK_GXBR4M_CHBPU9
REFCLK_GXBR4M_CHBNU10
REFCLK_GXBR4L_CHTPW9
REFCLK_GXBR4L_CHTNW10
GXBR4L_TX_CH5NR2
GXBR4L_TX_CH5PR1
GXBR4L_RX_CH5N, GXBR4L_REFCLK5NP8
GXBR4L_RX_CH5P, GXBR4L_REFCLK5PP7
GXBR4L_TX_CH4NT4
GXBR4L_TX_CH4PT3
GXBR4L_RX_CH4N, GXBR4L_REFCLK4NR6
GXBR4L_RX_CH4P, GXBR4L_REFCLK4PR5
GXBR4L_TX_CH3NU2
GXBR4L_TX_CH3PU1
GXBR4L_RX_CH3N, GXBR4L_REFCLK3NT8
GXBR4L_RX_CH3P, GXBR4L_REFCLK3PT7
GXBR4L_TX_CH2NV4
GXBR4L_TX_CH2PV3
GXBR4L_RX_CH2N, GXBR4L_REFCLK2NU6
GXBR4L_RX_CH2P, GXBR4L_REFCLK2PU5
GXBR4L_TX_CH1NW2
GXBR4L_TX_CH1PW1
GXBR4L_RX_CH1N, GXBR4L_REFCLK1NV8
GXBR4L_RX_CH1P, GXBR4L_REFCLK1PV7
GXBR4L_TX_CH0NY4
GXBR4L_TX_CH0PY3
GXBR4L_RX_CH0N, GXBR4L_REFCLK0NW6
GXBR4L_RX_CH0P, GXBR4L_REFCLK0PW5
REFCLK_GXBR4L_CHBPAA9
REFCLK_GXBR4L_CHBNAA10
REFCLK_GXBR4K_CHTPAC9
REFCLK_GXBR4K_CHTNAC10
GXBR4K_TX_CH5NAA2
GXBR4K_TX_CH5PAA1
GXBR4K_RX_CH5N, GXBR4K_REFCLK5NY8
GXBR4K_RX_CH5P, GXBR4K_REFCLK5PY7
GXBR4K_TX_CH4NAB4
GXBR4K_TX_CH4PAB3
GXBR4K_RX_CH4N, GXBR4K_REFCLK4NAA6
GXBR4K_RX_CH4P, GXBR4K_REFCLK4PAA5
GXBR4K_TX_CH3NAC2
GXBR4K_TX_CH3PAC1
GXBR4K_RX_CH3N, GXBR4K_REFCLK3NAB8
GXBR4K_RX_CH3P, GXBR4K_REFCLK3PAB7
GXBR4K_TX_CH2NAD4
GXBR4K_TX_CH2PAD3
GXBR4K_RX_CH2N, GXBR4K_REFCLK2NAC6
GXBR4K_RX_CH2P, GXBR4K_REFCLK2PAC5
GXBR4K_TX_CH1NAE2
GXBR4K_TX_CH1PAE1
GXBR4K_RX_CH1N, GXBR4K_REFCLK1NAD8
GXBR4K_RX_CH1P, GXBR4K_REFCLK1PAD7
GXBR4K_TX_CH0NAF4
GXBR4K_TX_CH0PAF3
GXBR4K_RX_CH0N, GXBR4K_REFCLK0NAE6
GXBR4K_RX_CH0P, GXBR4K_REFCLK0PAE5
REFCLK_GXBR4K_CHBPAE9
REFCLK_GXBR4K_CHBNAE10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XCVR BANK 4C 4D 4E 4FPCIe Root / zQSFP1
Swaped for routing
Swaped for routing
Swaped for routing
Swaped for routing
Swaped for routing
Swaped for routing
PCIE_RT_TX_P0PCIE_RT_TX_N0PCIE_RT_TX_P1PCIE_RT_TX_N1PCIE_RT_TX_P2PCIE_RT_TX_N2PCIE_RT_TX_P3PCIE_RT_TX_N3PCIE_RT_TX_P4PCIE_RT_TX_N4PCIE_RT_TX_P5PCIE_RT_TX_N5
PCIE_RT_RX_N1PCIE_RT_RX_P1
PCIE_RT_RX_N7PCIE_RT_RX_P7
PCIE_RT_RX_N8PCIE_RT_RX_P8
PCIE_RT_RX_N9PCIE_RT_RX_P9
PCIE_RT_RX_N10PCIE_RT_RX_P10
PCIE_RT_RX_N11PCIE_RT_RX_P11
PCIE_RT_TX_P6PCIE_RT_TX_N6PCIE_RT_TX_P7PCIE_RT_TX_N7PCIE_RT_TX_P8PCIE_RT_TX_N8PCIE_RT_TX_P9PCIE_RT_TX_N9PCIE_RT_TX_P10PCIE_RT_TX_N10PCIE_RT_TX_P11PCIE_RT_TX_N11
PCIE_RT_RX_P12PCIE_RT_RX_N12PCIE_RT_RX_P13PCIE_RT_RX_N13PCIE_RT_RX_P14PCIE_RT_RX_N14PCIE_RT_RX_P15PCIE_RT_RX_N15
PCIE_RT_TX_P12PCIE_RT_TX_N12PCIE_RT_TX_P13PCIE_RT_TX_N13PCIE_RT_TX_P14PCIE_RT_TX_N14PCIE_RT_TX_P15PCIE_RT_TX_N15
ZQSFP1_RX0_PZQSFP1_RX0_NZQSFP1_RX1_PZQSFP1_RX1_N
ZQSFP1_RX2_PZQSFP1_RX2_NZQSFP1_RX3_PZQSFP1_RX3_N
ZQSFP1_TX0_PZQSFP1_TX0_NZQSFP1_TX1_PZQSFP1_TX1_N
ZQSFP1_TX2_PZQSFP1_TX2_NZQSFP1_TX3_PZQSFP1_TX3_N
REFCLK_PCIE_RT_PREFCLK_PCIE_RT_N
REFCLK_ZQSFP1_PREFCLK_ZQSFP1_N
PCIE_RT_RX_N0PCIE_RT_RX_P0
PCIE_RT_RX_P2PCIE_RT_RX_N2
PCIE_RT_RX_P3PCIE_RT_RX_N3
PCIE_RT_RX_P4PCIE_RT_RX_N4
PCIE_RT_RX_P5PCIE_RT_RX_N5
PCIE_RT_RX_N6PCIE_RT_RX_P6
PCIE_RT_TX_P0 28PCIE_RT_TX_N0 28PCIE_RT_TX_P1 28PCIE_RT_TX_N1 28PCIE_RT_TX_P2 28PCIE_RT_TX_N2 28PCIE_RT_TX_P3 28PCIE_RT_TX_N3 28PCIE_RT_TX_P4 28PCIE_RT_TX_N4 28PCIE_RT_TX_P5 28PCIE_RT_TX_N5 28
PCIE_RT_RX_N1 28PCIE_RT_RX_P1 28
PCIE_RT_RX_N7 28PCIE_RT_RX_P7 28
PCIE_RT_RX_N8 28PCIE_RT_RX_P8 28
PCIE_RT_RX_N9 28PCIE_RT_RX_P9 28
PCIE_RT_RX_N10 28PCIE_RT_RX_P10 28
PCIE_RT_RX_N11 28PCIE_RT_RX_P11 28
PCIE_RT_TX_P6 28PCIE_RT_TX_N6 28PCIE_RT_TX_P7 28PCIE_RT_TX_N7 28PCIE_RT_TX_P8 28PCIE_RT_TX_N8 28PCIE_RT_TX_P9 28PCIE_RT_TX_N9 28PCIE_RT_TX_P10 28PCIE_RT_TX_N10 28PCIE_RT_TX_P11 28PCIE_RT_TX_N11 28
PCIE_RT_RX_P1228PCIE_RT_RX_N1228PCIE_RT_RX_P1328PCIE_RT_RX_N1328PCIE_RT_RX_P1428PCIE_RT_RX_N1428PCIE_RT_RX_P1528PCIE_RT_RX_N1528
PCIE_RT_TX_P1228PCIE_RT_TX_N1228PCIE_RT_TX_P1328PCIE_RT_TX_N1328PCIE_RT_TX_P1428PCIE_RT_TX_N1428PCIE_RT_TX_P1528PCIE_RT_TX_N1528
ZQSFP1_RX0_P26ZQSFP1_RX0_N26ZQSFP1_RX1_P26ZQSFP1_RX1_N26
ZQSFP1_RX2_P26ZQSFP1_RX2_N26ZQSFP1_RX3_P26ZQSFP1_RX3_N26
ZQSFP1_TX0_P26ZQSFP1_TX0_N26ZQSFP1_TX1_P26ZQSFP1_TX1_N26
ZQSFP1_TX2_P26ZQSFP1_TX2_N26ZQSFP1_TX3_P26ZQSFP1_TX3_N26
REFCLK_PCIE_RT_P 40REFCLK_PCIE_RT_N 40
REFCLK_ZQSFP1_N40REFCLK_ZQSFP1_P40
PCIE_RT_RX_N0 28PCIE_RT_RX_P0 28
PCIE_RT_RX_P2 28PCIE_RT_RX_N2 28
PCIE_RT_RX_P3 28PCIE_RT_RX_N3 28
PCIE_RT_RX_P4 28PCIE_RT_RX_N4 28
PCIE_RT_RX_P5 28PCIE_RT_RX_N5 28
PCIE_RT_RX_N6 28PCIE_RT_RX_P6 28
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
24 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
24 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
24 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R62 DNI
XCVR BANK 4E
XCVR BANK 4F
XCVR BANK 4C
XCVR BANK 4D
1SM210H_UF53
U2D
REFCLK_GXBR4F_CHTPAG9
REFCLK_GXBR4F_CHTNAG10
GXBR4F_TX_CH5NAG2
GXBR4F_TX_CH5PAG1
GXBR4F_RX_CH5N, GXBR4F_REFCLK5NAF8
GXBR4F_RX_CH5P, GXBR4F_REFCLK5PAF7
GXBR4F_TX_CH4NAH4
GXBR4F_TX_CH4PAH3
GXBR4F_RX_CH4N, GXBR4F_REFCLK4NAG6
GXBR4F_RX_CH4P, GXBR4F_REFCLK4PAG5
GXBR4F_TX_CH3NAJ2
GXBR4F_TX_CH3PAJ1
GXBR4F_RX_CH3N, GXBR4F_REFCLK3NAH8
GXBR4F_RX_CH3P, GXBR4F_REFCLK3PAH7
GXBR4F_TX_CH2NAK4
GXBR4F_TX_CH2PAK3
GXBR4F_RX_CH2N, GXBR4F_REFCLK2NAJ6
GXBR4F_RX_CH2P, GXBR4F_REFCLK2PAJ5
GXBR4F_TX_CH1NAL2
GXBR4F_TX_CH1PAL1
GXBR4F_RX_CH1N, GXBR4F_REFCLK1NAK8
GXBR4F_RX_CH1P, GXBR4F_REFCLK1PAK7
GXBR4F_TX_CH0NAM4
GXBR4F_TX_CH0PAM3
GXBR4F_RX_CH0N, GXBR4F_REFCLK0NAL6
GXBR4F_RX_CH0P, GXBR4F_REFCLK0PAL5
REFCLK_GXBR4F_CHBPAJ9
REFCLK_GXBR4F_CHBNAJ10
REFCLK_GXBR4E_CHTPAL9
REFCLK_GXBR4E_CHTNAL10
GXBR4E_TX_CH5NAN2
GXBR4E_TX_CH5PAN1
GXBR4E_RX_CH5N, GXBR4E_REFCLK5NAM8
GXBR4E_RX_CH5P, GXBR4E_REFCLK5PAM7
GXBR4E_TX_CH4NAP4
GXBR4E_TX_CH4PAP3
GXBR4E_RX_CH4N, GXBR4E_REFCLK4NAN6
GXBR4E_RX_CH4P, GXBR4E_REFCLK4PAN5
GXBR4E_TX_CH3NAR2
GXBR4E_TX_CH3PAR1
GXBR4E_RX_CH3N, GXBR4E_REFCLK3NAP8
GXBR4E_RX_CH3P, GXBR4E_REFCLK3PAP7
GXBR4E_TX_CH2NAT4
GXBR4E_TX_CH2PAT3
GXBR4E_RX_CH2N, GXBR4E_REFCLK2NAR6
GXBR4E_RX_CH2P, GXBR4E_REFCLK2PAR5
GXBR4E_TX_CH1NAU2
GXBR4E_TX_CH1PAU1
GXBR4E_RX_CH1N, GXBR4E_REFCLK1NAT8
GXBR4E_RX_CH1P, GXBR4E_REFCLK1PAT7
GXBR4E_TX_CH0NAV4
GXBR4E_TX_CH0PAV3
GXBR4E_RX_CH0N, GXBR4E_REFCLK0NAU6
GXBR4E_RX_CH0P, GXBR4E_REFCLK0PAU5
REFCLK_GXBR4E_CHBPAN9
REFCLK_GXBR4E_CHBNAN10
REFCLK_GXBR4D_CHTPAR9
REFCLK_GXBR4D_CHTNAR10
GXBR4D_TX_CH5NAW2
GXBR4D_TX_CH5PAW1
GXBR4D_RX_CH5N, GXBR4D_REFCLK5NAV8
GXBR4D_RX_CH5P, GXBR4D_REFCLK5PAV7
GXBR4D_TX_CH4NAY4
GXBR4D_TX_CH4PAY3
GXBR4D_RX_CH4N, GXBR4D_REFCLK4NAW6
GXBR4D_RX_CH4P, GXBR4D_REFCLK4PAW5
GXBR4D_TX_CH3NBA2
GXBR4D_TX_CH3PBA1
GXBR4D_RX_CH3N, GXBR4D_REFCLK3NAY8
GXBR4D_RX_CH3P, GXBR4D_REFCLK3PAY7
GXBR4D_TX_CH2NBB4
GXBR4D_TX_CH2PBB3
GXBR4D_RX_CH2N, GXBR4D_REFCLK2NBA6
GXBR4D_RX_CH2P, GXBR4D_REFCLK2PBA5
GXBR4D_TX_CH1NBC2
GXBR4D_TX_CH1PBC1
GXBR4D_RX_CH1N, GXBR4D_REFCLK1NBC6
GXBR4D_RX_CH1P, GXBR4D_REFCLK1PBC5
GXBR4D_TX_CH0NBD4
GXBR4D_TX_CH0PBD3
GXBR4D_RX_CH0N, GXBR4D_REFCLK0NBB8
GXBR4D_RX_CH0P, GXBR4D_REFCLK0PBB7
REFCLK_GXBR4D_CHBPAU9
REFCLK_GXBR4D_CHBNAU10
REFCLK_GXBR4C_CHTPAW9
REFCLK_GXBR4C_CHTNAW10
GXBR4C_TX_CH5NBE2
GXBR4C_TX_CH5PBE1
GXBR4C_RX_CH5N, GXBR4C_REFCLK5NBD8
GXBR4C_RX_CH5P, GXBR4C_REFCLK5PBD7
GXBR4C_TX_CH4NBF4
GXBR4C_TX_CH4PBF3
GXBR4C_RX_CH4N, GXBR4C_REFCLK4NBE6
GXBR4C_RX_CH4P, GXBR4C_REFCLK4PBE5
GXBR4C_TX_CH3NBG2
GXBR4C_TX_CH3PBG1
GXBR4C_RX_CH3N, GXBR4C_REFCLK3NBF8
GXBR4C_RX_CH3P, GXBR4C_REFCLK3PBF7
GXBR4C_TX_CH2NBH4
GXBR4C_TX_CH2PBH3
GXBR4C_RX_CH2N, GXBR4C_REFCLK2NBG6
GXBR4C_RX_CH2P, GXBR4C_REFCLK2PBG5
GXBR4C_TX_CH1NBK4
GXBR4C_TX_CH1PBK3
GXBR4C_RX_CH1N, GXBR4C_REFCLK1NBJ6
GXBR4C_RX_CH1P, GXBR4C_REFCLK1PBJ5
GXBR4C_TX_CH0NBL6
GXBR4C_TX_CH0PBL5
GXBR4C_RX_CH0N, GXBR4C_REFCLK0NBH8
GXBR4C_RX_CH0P, GXBR4C_REFCLK0PBH7
REFCLK_GXBR4C_CHBPBA9
REFCLK_GXBR4C_CHBNBA10
R63 DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Route traceshort aspossible
Ios Limit = 1.489A / 1.742A / 1.965A
ZQSFP: Molex MPN 170432-0002
Guide PinsGuide Pins
NOTE 2: zQSFP 100-ohm termination is implemented via the FPGA on-chip termination.
NOTE 3: DC blocking capacitors are in the module for RX and TX.
NOTE 4: 1uH inductors should have a DC Resistance of less than 0.1-ohm.
NOTE 1: Bypass Capacitors should be placed as close to the associated 20-pinconnector as possible.
Place close to zQSFP Connector
MOLEX MPN 1000141901
60uA
Vil=0.66VVih=1.1V
Rds(on) max = 35mOhmdropout max = 1.965A x .035 = .069V
ABSMAX = 7V
ABSMAX = 7V
zQSFP0
3p3V3p3V_ZQSFP0
ZQSFP0_VCC ZQSFP0_VCCT ZQSFP0_VCCR
3p3V
GND_QSFP0_CAGE
GND_QSFP0_CAGE GND_QSFP0_CAGE
3p3V
3p3V_ZQSFP0 ZQSFP0_VCCT
ZQSFP0_VCCR
ZQSFP0_VCC
ZQSFP0_FAULT_N48
ZQSFP0_TX0_P 22ZQSFP0_TX0_N 22
ZQSFP0_TX1_P 22ZQSFP0_TX1_N 22
ZQSFP0_TX2_P 22ZQSFP0_TX2_N 22
ZQSFP0_TX3_P 22ZQSFP0_TX3_N 22
ZQSFP0_RX0_P22ZQSFP0_RX0_N22
ZQSFP0_RX1_P22ZQSFP0_RX1_N22
ZQSFP0_RX2_P22ZQSFP0_RX2_N22
ZQSFP0_RX3_P22ZQSFP0_RX3_N22
ZQSFP_I2C_SCL26,32ZQSFP_I2C_SDA26,32
ZQSFP0_3V3_MODPRS_L45
ZQSFP0_PWR_EN48
ZQSFP0_3V3_INT_L45
ZQSFP0_3V3_RESET_L45
ZQSFP0_3V3_LPMODE45
ZQSFP0_3V3_MODSEL_L45
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
25 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
25 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
25 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R68 10.0K
U8
TPS2557DRBR
IN23 IN12
EN4
FAULT8
GND1
MPAD9
ILIM5
OUT16
OUT27
C170
22uF
R671M
C166
22uF
R69 10.0K
C176
10uF
C177
22uF
C165
0.1uF
B1
Molex_zQSFP_Cage
1000141901
Pin11
Pin22
Pin33
Pin44
Pin55
Pin66
Pin77
Pin88
Pin99
Pin1010
Pin1111
C175
0.1uF
C162
22uF
C178
22uF
FB2
80ohm @ 100Mhz5A, 10mOhm
C1791000pF
R65
4.7K
C174
22uF
FB3
80ohm @ 100Mhz5A, 10mOhm
C167
0.1uF
C168
10uF
J4
Molex_zQSFP_Connector
GND121
TX2n2TX2p3
GND114
TX4n5TX4p6
GND107
ModselL8
ResetL9
VCCRX10
SCL11
SDA12
GND913
RX3p14
RX3n15
GND816
RX1p17
RX1n18
GND719GND620
RX2n21 RX2p22
GND523
RX4n24 RX4p25
GND426
ModPrsL27
Intl28
VCCTX29VCC130
LPMode31
GND332
TX3p33
TX3n34
GND235
TX1p36
TX1n37
GND138
MTH139
MTH240
C172
10uF
FB1
80ohm @ 100Mhz5A, 10mOhm
C173
22uF
C163
1uF
R6663.4K04021%
R6454.9K04021%
C164
0.1uF
C171
0.1uF
C169
22uF
R842
4.7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ZQSFP: Molex MPN 170432-0002
Place close to zQSFP Connector
Guide PinsGuide Pins
NOTE 1: Bypass Capacitors should be placed as close to the associated 20-pinconnector as possible.
NOTE 2: zQSFP 100-ohm termination is implemented via the FPGA on-chip termination.
NOTE 3: DC blocking capacitors are in the module for RX and TX.
NOTE 4: 1uH inductors should have a DC Resistance of less than 0.1-ohm.
MOLEX MPN 1000141901
zQSFP1
Vil=0.66VVih=1.1V
Rds(on) max = 35mOhmdropout max = 1.965A x .035 = .069V
Route traceshort aspossible
Ios Limit = 1.489A / 1.742A / 1.965A
60uA
ABSMAX = 7V
ABSMAX = 7V
3p3V_ZQSFP1 ZQSFP1_VCCT
ZQSFP1_VCCR
ZQSFP1_VCC
ZQSFP1_VCC ZQSFP1_VCCT ZQSFP1_VCCR
3p3V
GND_QSFP1_CAGE
GND_QSFP1_CAGE GND_QSFP1_CAGE
3p3V3p3V_ZQSFP1
3p3V
ZQSFP1_RX0_P24 ZQSFP1_TX0_P 24ZQSFP1_RX0_N24 ZQSFP1_TX0_N 24
ZQSFP1_RX1_P24 ZQSFP1_TX1_P 24ZQSFP1_RX1_N24 ZQSFP1_TX1_N 24
ZQSFP1_RX2_P24 ZQSFP1_TX2_P 24ZQSFP1_RX2_N24 ZQSFP1_TX2_N 24
ZQSFP1_RX3_P24 ZQSFP1_TX3_P 24ZQSFP1_RX3_N24 ZQSFP1_TX3_N 24
ZQSFP1_3V3_RESET_L45ZQSFP1_3V3_MODPRS_L45ZQSFP1_3V3_LPMODE45ZQSFP1_3V3_INT_L45
ZQSFP_I2C_SCL25,32ZQSFP_I2C_SDA25,32
ZQSFP1_3V3_MODSEL_L45
ZQSFP1_FAULT_N48
ZQSFP1_PWR_EN48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
26 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
26 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
26 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
R7054.9K04021%
C189
0.1uF
C187
22uF
FB6
80ohm @ 100Mhz5A, 10mOhm
R731M
FB4
80ohm @ 100Mhz5A, 10mOhm
C195
22uF
R75 10.0K
C194
10uF
C1971000pF
C184
22uF
R74 10.0K
C192
22uF
R71
4.7K
C193
0.1uF
J5
Molex_zQSFP_Connector
GND121
TX2n2TX2p3
GND114
TX4n5TX4p6
GND107
ModselL8
ResetL9
VCCRX10
SCL11
SDA12
GND913
RX3p14
RX3n15
GND816
RX1p17
RX1n18
GND719GND620
RX2n21 RX2p22
GND523
RX4n24 RX4p25
GND426
ModPrsL27
Intl28
VCCTX29VCC130
LPMode31
GND332
TX3p33
TX3n34
GND235
TX1p36
TX1n37
GND138
MTH139
MTH240
FB5
80ohm @ 100Mhz5A, 10mOhm
C185
0.1uF
C182
0.1uF
C180
1uF
C183
0.1uF
R843
4.7K
C191
22uF
C181
22uF
C190
10uF
U9
TPS2557DRBR
IN23 IN12
EN4
FAULT8
GND1
MPAD9
ILIM5
OUT16
OUT27
R7263.4K04021%
C188
22uF
B2
Molex_zQSFP_Cage
1000141901
Pin11
Pin22
Pin33
Pin44
Pin55
Pin66
Pin77
Pin88
Pin99
Pin1010
Pin1111
C196
22uF
C186
10uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE TX to FPGA RXP/N Lane Reversal during layout is allowed
PCIE RX from FPGA TXP/N Lane Reversal during layout is allowed
PCIe TX/RX signal naming conventionwith respect to CPU
PCIe Endpoint Edge ConnectorPCIE_EP_PRSNT_N
PCIE_EP_3V3_I2C_SCLPCIE_EP_3V3_I2C_SDA
PCIE_EP_PERSTN
PCIE_EP_RX_CP0PCIE_EP_RX_CN0
PCIE_EP_PRSNT_N
PCIE_EP_RX_CP1PCIE_EP_RX_CN1
PCIE_EP_RX_CP2PCIE_EP_RX_CN2
PCIE_EP_RX_CP3PCIE_EP_RX_CN3
PCIE_EP_RX_CP4PCIE_EP_RX_CN4
PCIE_EP_RX_CP5PCIE_EP_RX_CN5
PCIE_EP_RX_CP6PCIE_EP_RX_CN6
PCIE_EP_RX_CP7PCIE_EP_RX_CN7
PCIE_EP_RX_CP8PCIE_EP_RX_CN8
PCIE_EP_RX_CP9PCIE_EP_RX_CN9
PCIE_EP_RX_CP10PCIE_EP_RX_CN10
PCIE_EP_RX_CP11PCIE_EP_RX_CN11
PCIE_EP_RX_CP12PCIE_EP_RX_CN12
PCIE_EP_RX_CP13PCIE_EP_RX_CN13
PCIE_EP_RX_CP14PCIE_EP_RX_CN14
PCIE_EP_RX_CP15PCIE_EP_RX_CN15
PCIE_EP_3V3_I2C_SCLPCIE_EP_3V3_I2C_SDA
PCIE_EP_3V3_WAKEN
PCIE_EP_3V3_WAKENPCIE_EP_PERSTN PCIE_EP_RSTN
PCIE_EP_RSTN
PCIE_EP_3p3V
3p3V
3p3V
1p8V
1p8V
3p3V
3p3V
1p8V
1p8V
1p8V
PCIE_EP_3p3V PCIE_EP_12V PCIE_EP_12V
REFCLK_PCIE_EP_EDGE_P 22REFCLK_PCIE_EP_EDGE_N 22PCIE_EP_TX_P022
PCIE_EP_TX_N022
PCIE_EP_TX_P122PCIE_EP_TX_N122
PCIE_EP_TX_P222PCIE_EP_TX_N222
PCIE_EP_TX_P322PCIE_EP_TX_N322
PCIE_EP_TX_P422PCIE_EP_TX_N422
PCIE_EP_TX_P522PCIE_EP_TX_N522
PCIE_EP_TX_P622PCIE_EP_TX_N622
PCIE_EP_TX_P722PCIE_EP_TX_N722
PCIE_EP_TX_P822PCIE_EP_TX_N822
PCIE_EP_TX_P922PCIE_EP_TX_N922
PCIE_EP_TX_P1022PCIE_EP_TX_N1022
PCIE_EP_TX_P1122PCIE_EP_TX_N1122
PCIE_EP_TX_P1222PCIE_EP_TX_N1222
PCIE_EP_TX_P1322PCIE_EP_TX_N1322
PCIE_EP_TX_P1422PCIE_EP_TX_N1422
PCIE_EP_TX_P1522PCIE_EP_TX_N1522
PCIE_EP_JTAG_TCK 45PCIE_EP_JTAG_TDI 45
PCIE_EP_JTAG_TMS 45PCIE_EP_JTAG_TDO 45
PCIE_EP_RX_P0 22PCIE_EP_RX_N0 22
PCIE_EP_RX_P1 22PCIE_EP_RX_N1 22
PCIE_EP_RX_P2 22PCIE_EP_RX_N2 22
PCIE_EP_RX_P3 22PCIE_EP_RX_N3 22
PCIE_EP_RX_P4 22PCIE_EP_RX_N4 22
PCIE_EP_RX_P5 22PCIE_EP_RX_N5 22
PCIE_EP_RX_P6 22PCIE_EP_RX_N6 22
PCIE_EP_RX_P7 22PCIE_EP_RX_N7 22
PCIE_EP_RX_P8 22PCIE_EP_RX_N8 22
PCIE_EP_RX_P9 22PCIE_EP_RX_N9 22
PCIE_EP_RX_P10 22PCIE_EP_RX_N10 22
PCIE_EP_RX_P11 22PCIE_EP_RX_N11 22
PCIE_EP_RX_P12 22PCIE_EP_RX_N12 22
PCIE_EP_RX_P13 22PCIE_EP_RX_N13 22
PCIE_EP_RX_P14 22PCIE_EP_RX_N14 22
PCIE_EP_RX_P15 22PCIE_EP_RX_N15 22
PCIE_EP_I2C_SCL 32PCIE_EP_I2C_SDA 32PCIE_EP_WAKEN 32
S10_PCIE_PERSTn0 33
PCIE_EP_3V3_I2C_SCL45PCIE_EP_3V3_I2C_SDA45
PCIE_EP_PERSTN 49
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
27 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
27 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
27 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2016, Intel Corporation. All Rights Reserved.
C220 0.22uF 040225V X6S
R76 10.0K
R84
10.0K
C208 0.22uF 040225V X6S
C224 0.22uF 040225V X6S
KEY
X4
X8
X1
X16
J6
PCIE_Slot
+12V_B1B1
+12V_B2B2
+12V_B3B3
GNDB4
SMCLKB5
SMDATB6
GNDB7
+3_3VB8
JTAG_TRSTNB9
+3_3VAUXB10
WAKE_NB11
RSVD1B12
GNDB13
PET0PB14
PET0NB15
GNDB16
PRSNT2n_X1B17
GNDB18
PET1PB19
PET1NB20
GNDB21
GNDB22
PET2PB23
PET2NB24
GNDB25
GNDB26
PET3PB27
PET3NB28
GNDB29
RSVD3B30
PRSNT2n_X4B31
GNDB32
PET4PB33
PET4NB34
GNDB35
GNDB36
PET5PB37
PET5NB38
GNDB39
GNDB40
PET6PB41
PET6NB42
GNDB43
GNDB44
PET7PB45
PET7NB46
GNDB47
PRSNT2n_X8B48
GNDB49
PRSNT1_NA1
+12V_A2A2
+12V_A3A3
GNDA4
JTAG_TCKA5
JTAG_TDIA6
JTAG_TDOA7
JTAG_TMSA8
+3_3VA9
+3_3VA10
PERST_NA11
GNDA12
REFCLK+A13
REFCLK-A14
GNDA15
PER0PA16
PER0NA17
GNDA18
RSVD2A19
GNDA20
PER1PA21
PER1NA22
GNDA23
GNDA24
PER2PA25
PER2NA26
GNDA27
GNDA28
PER3PA29
PER3NA30
GNDA31
RSVD4A32
RSVD5A33
GNDA34
PER4PA35
PER4NA36
GNDA37
GNDA38
PER5PA39
PER5NA40
GNDA41
GNDA42
PER6PA43
PER6NA44
GNDA45
GNDA46
PER7PA47
PER7NA48
GNDA49
PET8PB50
PET8NB51
GNDB52
GNDB53
PET9PB54
PET9NB55
GNDB56
GNDB57
PET10PB58
PET10NB59
GNDB60
GNDB61
PET11PB62
PET11NB63
GNDB64
GNDB65
PET12PB66
PET12NB67
GNDB68
GNDB69
PET13PB70
PET13NB71
GNDB72
GNDB73
PET14PB74
PET14NB75
GNDB76
GNDB77
PET15PB78
PET15NB79
GNDB80
PRSNT2n_X16B81
RSVD6B82
RSVD7A50
GNDA51
PER8PA52
PER8NA53
GNDA54
GNDA55
PER9PA56
PER9NA57
GNDA58
GNDA59
PER10PA60
PER10NA61
GNDA62
GNDA63
PER11PA64
PER11NA65
GNDA66
GNDA67
PER12PA68
PER12NA69
GNDA70
GNDA71
PER13PA72
PER13NA73
GNDA74
GNDA75
PER14PA76
PER14NA77
GNDA78
GNDA79
PER15PA80
PER15NA81
GNDA82
C198 0.22uF 040225V X6S
C212 0.22uF 040225V X6S
R85 0
R78
4.7K
C228 0.22uF 040225V X6S
U10
MAX3378E
VL1
IOVL12
IOVL23
IOVL34
IOVL45
NC06
GND7
TSn8 NC19 IOVCC4
10 IOVCC311 IOVCC212 IOVCC113 VCC14
C217 0.22uF 040225V X6S
C232 0.22uF 040225V X6S
R86 0
C1553 1000pF
C205 0.22uF 040225V X6S
C221 0.22uF 040225V X6S
R829 1K
C209 0.22uF 040225V X6S
C225 0.22uF 040225V X6S
C201 0.22uF 040225V X6S
S1
PB Switch1 2
R82 10.0K
C213 0.22uF 040225V X6S
R79 10.0K
C229 0.22uF 040225V X6S
R83
10.0K
C218 0.22uF 040225V X6S
C233 0.22uF 040225V X6S
C206 0.22uF 040225V X6S
C222 0.22uF 040225V X6S
C210 0.22uF 040225V X6S
C226 0.22uF 040225V X6S
R81 DNI
C214 0.22uF 040225V X6S
C230 0.22uF 040225V X6S
U11
SN74LVC1G08
A1
B2
GND3
VCC5
Y4
C203 0.22uF 040225V X6S
C219 0.22uF 040225V X6S
C207 0.22uF 040225V X6S
C223 0.22uF 040225V X6S
C215
0.1uF
C199
1uF
R77
4.7K
C211 0.22uF 040225V X6S
C227 0.22uF 040225V X6S
R87 10.0K
C202
0.1uF
R80 DNI
C216 0.22uF 040225V X6S
C231 0.22uF 040225V X6S
C200
0.1uF
C204 0.22uF 040225V X6S
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To PWR MAX10, UBII MAX10, S10
PCIe Root ConnectorThis is a 25W slot+12V : 2.1A +/-8%
+3.3V : 3.0A +/-9%
Place caps near connector
PCIE_RT_TX_CP6PCIE_RT_TX_CN6
PCIE_RT_TX_CP7PCIE_RT_TX_CN7
PCIE_RT_TX_CN5PCIE_RT_TX_CP5
PCIE_RT_TX_CN4PCIE_RT_TX_CP4
PCIE_RT_TX_CP2PCIE_RT_TX_CN2
PCIE_RT_TX_CP3PCIE_RT_TX_CN3
PCIE_RT_TX_CN1PCIE_RT_TX_CP1
PCIE_RT_TX_CP0PCIE_RT_TX_CN0
PCIE_RT_TX_CP8PCIE_RT_TX_CN8
PCIE_RT_TX_CP9PCIE_RT_TX_CN9
PCIE_RT_TX_CP10PCIE_RT_TX_CN10
PCIE_RT_TX_CP11PCIE_RT_TX_CN11
PCIE_RT_TX_CP12PCIE_RT_TX_CN12
PCIE_RT_TX_CP13PCIE_RT_TX_CN13
PCIE_RT_TX_CP14PCIE_RT_TX_CN14
PCIE_RT_TX_CP15PCIE_RT_TX_CN15
3p3V12V_G13p3V 12V_G1
3p3V
3p3V
12V_G1
3p3V
3p3V
PCIE_RT_TX_P024PCIE_RT_TX_N024
PCIE_RT_TX_P124PCIE_RT_TX_N124
PCIE_RT_TX_P224PCIE_RT_TX_N224
PCIE_RT_TX_P324PCIE_RT_TX_N324
PCIE_RT_TX_P424PCIE_RT_TX_N424
PCIE_RT_TX_P524PCIE_RT_TX_N524
PCIE_RT_TX_P624PCIE_RT_TX_N624
PCIE_RT_TX_P724PCIE_RT_TX_N724
PCIE_RT_TX_P824PCIE_RT_TX_N824
PCIE_RT_TX_P924PCIE_RT_TX_N924
PCIE_RT_TX_P1024PCIE_RT_TX_N1024
PCIE_RT_TX_P1124PCIE_RT_TX_N1124
PCIE_RT_TX_P1224PCIE_RT_TX_N1224
PCIE_RT_TX_P1324PCIE_RT_TX_N1324
PCIE_RT_TX_P1424PCIE_RT_TX_N1424
PCIE_RT_TX_P1524PCIE_RT_TX_N1524
PCIE_RT_RX_P0 24PCIE_RT_RX_N0 24
PCIE_RT_RX_P1 24PCIE_RT_RX_N1 24
PCIE_RT_RX_P2 24PCIE_RT_RX_N2 24
PCIE_RT_RX_P3 24PCIE_RT_RX_N3 24
PCIE_RT_RX_P4 24PCIE_RT_RX_N4 24
PCIE_RT_RX_P5 24PCIE_RT_RX_N5 24
PCIE_RT_RX_P6 24PCIE_RT_RX_N6 24
PCIE_RT_RX_P7 24PCIE_RT_RX_N7 24
PCIE_RT_RX_P8 24PCIE_RT_RX_N8 24
PCIE_RT_RX_P9 24
PCIE_RT_JTAG_TCK 45
PCIE_RT_RX_N9 24
PCIE_RT_JTAG_TDI 45PCIE_RT_JTAG_TDO 45
PCIE_RT_RX_P10 24PCIE_RT_RX_N10 24
PCIE_RT_JTAG_TMS 45
PCIE_RT_RX_P11 24PCIE_RT_RX_N11 24
PCIE_RT_RX_P12 24PCIE_RT_RX_N12 24
PCIE_RT_RX_P13 24PCIE_RT_RX_N13 24
PCIE_RT_RX_P14 24PCIE_RT_RX_N14 24
PCIE_RT_RX_P15 24PCIE_RT_RX_N15 24
REFCLK_PCIE_RT_SYS_P 40REFCLK_PCIE_RT_SYS_N 40
PCIE_RT_WAKEN45
PCIE_RT_JTAG_TRSTn45
PCIE_RT_PERSTn 45
PCIE_RT_PRSNT2n45,48
I2C_3V3_SCL42,48,49,52I2C_3V3_SDA42,48,49,52
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
28 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
28 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
28 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C252 0.22uF
C2340.1uF
C274 0.22uF
C260 0.22uF
R93 10.0K
C249 0.22uF
C240 0.22uF
R94 DNI
C276 0.22uF
C2360.1uF
C245 0.22uF
R92 10.0K
C272 0.22uF
C2390.1uF
C242 0.22uF
C251 0.22uF
R88 10.0K
C2370.1uF
C257 0.22uF
C248 0.22uF
C2630.1uF
C250 0.22uF
C241 0.22uF
C2640.1uF
C269 0.22uF
C255 0.22uF
C2670.1uF
C247 0.22uF
C259 0.22uF
KEY
X4
X8
X1
X16
J7
PCIE-164-02-F-D-EMS2
+12VB1
+12VB2
+12VB3
GNDB4
SMCLKB5
SMDATB6
GNDB7
+3_3VB8
JTAG_TRSTNB9
+3_3VAUXB10
WAKE_NB11
RSVD1B12
GNDB13
PET0PB14
PET0NB15
GNDB16
PRSNT2n_X1B17
GNDB18
PET1PB19
PET1NB20
GNDB21
GNDB22
PET2PB23
PET2NB24
GNDB25
GNDB26
PET3PB27
PET3NB28
GNDB29
RSVD3B30
PRSNT2n_X4B31
GNDB32
PET4PB33
PET4NB34
GNDB35
GNDB36
PET5PB37
PET5NB38
GNDB39
GNDB40
PET6PB41
PET6NB42
GNDB43
GNDB44
PET7PB45
PET7NB46
GNDB47
PRSNT2n_X8B48
GNDB49
PRSNT1_NA1
+12VA2
+12VA3
GNDA4
JTAG_TCKA5
JTAG_TDIA6
JTAG_TDOA7
JTAG_TMSA8
+3_3VA9
+3_3VA10
PERST_NA11
GNDA12
REFCLK+A13
REFCLK-A14
GNDA15
PER0PA16
PER0NA17
GNDA18
RSVD2A19
GNDA20
PER1PA21
PER1NA22
GNDA23
GNDA24
PER2PA25
PER2NA26
GNDA27
GNDA28
PER3PA29
PER3NA30
GNDA31
RSVD4A32
RSVD5A33
GNDA34
PER4PA35
PER4NA36
GNDA37
GNDA38
PER5PA39
PER5NA40
GNDA41
GNDA42
PER6PA43
PER6NA44
GNDA45
GNDA46
PER7PA47
PER7NA48
GNDA49
PET8PB50
PET8NB51
GNDB52
GNDB53
PET9PB54
PET9NB55
GNDB56
GNDB57
PET10PB58
PET10NB59
GNDB60
GNDB61
PET11PB62
PET11NB63
GNDB64
GNDB65
PET12PB66
PET12NB67
GNDB68
GNDB69
PET13PB70
PET13NB71
GNDB72
GNDB73
PET14PB74
PET14NB75
GNDB76
GNDB77
PET15PB78
PET15NB79
GNDB80
PRSNT2n_X16B81
RSVD6B82
RSVD7A50
GNDA51
PER8PA52
PER8NA53
GNDA54
GNDA55
PER9PA56
PER9NA57
GNDA58
GNDA59
PER10PA60
PER10NA61
GNDA62
GNDA63
PER11PA64
PER11NA65
GNDA66
GNDA67
PER12PA68
PER12NA69
GNDA70
GNDA71
PER13PA72
PER13NA73
GNDA74
GNDA75
PER14PA76
PER14NA77
GNDA78
GNDA79
PER15PA80
PER15NA81
GNDA82
R90 10.0K
C261 0.22uF C2660.1uF
C275 0.22uF
C271 0.22uF
C273 0.22uF
C2650.1uF
C244 0.22uF
C254 0.22uFC253 0.22uF
C26222uF
C258 0.22uF
R911K
C243 0.22uF
C256 0.22uF
R95 4.7K C238
100uF
C270 0.22uF
C235 0.22uF
R96 10.0K
C268 0.22uF
R89 DNI
C246 0.22uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
This page is left blank
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
29 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
29 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
29 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SDM & Configuration
Config Mode MSEL2 MSEL1 MSEL0
AS_FAST 0 0 1 AS_NORMAL 0 1 1
MSEL0MSEL1MSEL2
VFEF_ADC R valuebased on 20ma for1.25V zener
S10_NCONFIG
S10_NSTATUS
S10_INIT_DONE
S10_CVP_CONFDONE
S10_JTAG_TDO
S10_JTAG_TDIS10_JTAG_TCKS10_JTAG_TMS
S10_OSC_CLK_1
S10_NCONFIGS10_NSTATUS
S10_JTAG_TMSS10_JTAG_TDIS10_JTAG_TCK
AS_CLK AS_CLK_R
AS_DATA0AS_DATA1AS_DATA2AS_DATA3
AS_CS0_MSEL0
AS_DATA2AS_DATA0AS_CS0_MSEL0AS_DATA3
AS_DATA1
MSEL1
MSEL2
MSEL2 MSEL1 AS_CS0_MSEL0
AS_CLK
S10_SDM_SCL
S10_SDM_SDA
S10_CONF_DONES10_CVP_CONFDONE
S10_INIT_DONE
S10_CONF_DONE
S10_TEMP0nS10_TEMP0p
1p8V
1p8V
1p8V 1p8V1p8V
1p8V
S10_JTAG_TCK45S10_JTAG_TMS45
S10_OSC_CLK_141
S10_NCONFIG45S10_JTAG_TDI45
S10_JTAG_TDO45
S10_SDM_SCL42
S10_SDM_SDA42
S10_CONF_DONE43,45S10_CVP_CONFDONE43,45
S10_INIT_DONE45
S10_TEMP0p49S10_TEMP0n49
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
30 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
30 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
30 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R129 2K
R140 10.0K
R132 2K
FB7
DNI
12
R128 2K
R126
DNI
D6
LT1389
Gnd4
Vout6
Gnd5
nc11
nc22
nc33
nc47
nc58
R137 1K
R134 499
R136 10.0K
C298
0.1uF
R133
1K
R142 10.0K
R135 10.0K
R121
DNI
C299
0.1uF
R123
4.7K
V30
R124
4.7K
R141 10.0K
V29
R127 33
R139 10.0K
R122
DNI
R131 2K
C300
0.1uF
R138 10.0K
R125
4.7K
SDM BANK
1SM210H_UF53
U2S
RREF_TLAF39
RREF_BLAT39
RREF_TRAD13
RREF_BRBL8
TDOAR36
TMSBJ41
TCKBE42
TDIAU37
OSC_CLK_1AR35
SDM_IO0, INIT_DONE, PWRMGT_PWM0, PWRMGT_SCLBK41
SDM_IO1, AVSTX8_DATA2, AS_DATA1, SDMMC_CFG_DATA1, NAND_RE_NBG42
SDM_IO5, AS_NCSO0, SDMMC_CFG_CCLK, NAND_WE_N, MSEL0, CONF_DONEAR37
SDM_IO3, AVSTX8_DATA3, AS_DATA2, SDMMC_CFG_DATA2, NAND_ADQ2BF42
NCONFIGBG41
SDM_IO4, AVSTX8_DATA1, AS_DATA0, SDMMC_CFG_CMD, NAND_ADQ1BH41
SDM_IO2, AVSTX8_DATA0, AS_CLK, SDMMC_CFG_DATA0, NAND_ADQ0AT37
SDM_IO7, AS_NCSO2, NAND_ALE, MSEL1AV38
SDM_IO11, AVSTX8_VALID, PWRMGT_SDA, NAND_ADQ6AW38
NSTATUSAV39
SDM_IO16, CONF_DONE, PWRMGT_SDAAY39
SDM_IO13, AVSTX8_DATA5, SDMMC_CFG_DATA5, NAND_CE_NAW39
SDM_IO9, AS_NCSO1, NAND_CLE, MSEL2BA39
SDM_IO6, AVSTX8_DATA4, AS_DATA3, SDMMC_CFG_DATA3, NAND_ADQ3BC40
SDM_IO10, AVSTX8_DATA7, SDMMC_CFG_DATA7, NAND_ADQ5BB40
SDM_IO8, AVST_READY, AS_NCSO3, SDMMC_CFG_DATA4, NAND_RBBE41
SDM_IO12, PWRMGT_PWM0, PWRMGT_SDA, NAND_WP_NBD42
SDM_IO15, AVSTX8_DATA6, SDMMC_CFG_DATA6, NAND_ADQ4BC42 SDM_IO14, AVSTX8_CLK, PWRMGT_SCL, NAND_ADQ7BA38
DNU,ATB0_SDMAR34
DNU,ATB1_SDMAT35
RREF_SDMAR32
DNU,TBGREFAP33
VREFP_ADCBL43
VREFN_ADCBL42
VSIGP_0BL44
VSIGN_0BK44
VSIGP_1BJ42
VSIGN_1BK42
DNU,TPWELL0AT32
TEMPDIODE0nBC41
TEMPDIODE0pBD41
R130 2K
U14
MT25QU02GCBB3E12-1SIT
S#C2
CB2
RESET#/DNUA4
W#/DQ2C4
DQ0D3
DQ1D2
DQ3D4
VCCB4
VSSB3
DNU1A2
DNU2A3
DNU3A5
DNU4B1
DNU5B5
DNU6C1
DNU7C3
DNU8C5
DNU9D1
DNU10D5
DNU11E1
DNU12E2
DNU13E3
DNU14E4
DNU15E5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Bank 3A/DNU_UIB
DA28 = 0, Normal Operation;DA28 = 1, Vendor Test
U50_DA28
U50_DA28
U51_DA28
U51_DA28
CLK_SYS_50M_NCLK_SYS_50M_P
1p2V_VCCIO_UIB 1p2V_VCCIO_UIB
CLK_SYS_50M_N41CLK_SYS_50M_P41
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
31 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
31 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
31 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R144
DNI
R146
49.9
R145
DNI
R147
49.9
R818 100
1SM210H_UF53
U2T
DNU1BB25
DNU2BA25
DNU3AU25
DNU4AT25
DNU5BL20
DNU6BL19
DNU7BK21
DNU8BK20
DNU9AT24
DNU10BJ21
DNU11BG22
DNU12BH21
DNU13BG21
DNU14BD24
DNU15AR24
DNU16BF22
DNU17BC24
DNU18BD23
DNU19BE22
DNU20BD22
DNU21BC23
DNU22AU27
DNU23BB23
DNU24AT23
DNU25BE21
DNU26BB22
DNU27BD21
DNU28AT22
DNU29AU28
DNU30AU21
DNU31BC21
DNU32BB21
DNU33AK16
DNU34AN16
DNU35AM16
DNU36AP17
DNU37AP16
DNU38AU26
DNU39BC25
DNU40U17
DNU41T18
DNU42U18
DNU43U20
DNU44T20
DNU45T19
DNU46R20
DNU47R21
DNU48R22
DNU49T22
DNU50U23
DNU51T23
DNU52K24
DNU53K25
DNU54T24
DNU55L25
DNU56T25
DNU57K26
DNU58R26
DNU59U26
DNU60A27
DNU61U16
DNU62K27
DNU63D27
DNU64M27
DNU65D28
DNU66F28 DNU67L27 DNU68
W16 DNU69G28 DNU70N28 DNU71H28 DNU72J28 DNU73L28 DNU74J27 DNU75
M28 DNU76P28 DNU77V16 DNU78Y16
IO BANK 3A
1SM210H_UF53
U2Q
IO, LVDS3A_1N, DQ60AU20
IO, LVDS3A_1P, DQ60AV20
IO, LVDS3A_2N, DQ60AT20
IO, LVDS3A_2P, DQ60AR20
IO, LVDS3A_3N, DQ60AR19
IO, LVDS3A_3P, DQ60AT19
IO, LVDS3A_4N, DQSN60AW19
IO, LVDS3A_4P, DQS60AV19
IO, LVDS3A_5N, DQ60AV18
IO, LVDS3A_5P, DQ60AW18
IO, LVDS3A_6N, DQ60AU18
IO, LVDS3A_6P, DQ60AT18
IO, LVDS3A_7N, DQ61BA20
IO, LVDS3A_7P, DQ61AY20
IO, LVDS3A_8N, DQ61AY19
IO, LVDS3A_8P, DQ61BA19
IO, LVDS3A_9N, DQ61BB18
IO, LVDS3A_9P, DQ61BA18
IO, PLL_3A_CLKOUT1N, LVDS3A_10N, DQSN61BC18
IO, PLL_3A_CLKOUT1P, PLL_3A_CLKOUT1, PLL_3A_FBN, LVDS3A_10P, DQS61BD18
IO, LVDS3A_11N, DQ61BC19
IO, RZQ_3A, LVDS3A_11P, DQ61BD19
IO, CLK_3A_1N, LVDS3A_12N, DQ61BC20
IO, CLK_3A_1P, LVDS3A_12P, DQ61BB20
IO, CLK_3A_0N, LVDS3A_13N, DQ62BD17
IO, CLK_3A_0P, LVDS3A_13P, DQ62BE17
IO, LVDS3A_14N, DQ62BG17
IO, LVDS3A_14P, DQ62BF17
IO, PLL_3A_CLKOUT0N, LVDS3A_15N, DQ62BH18
IO, PLL_3A_CLKOUT0P, PLL_3A_CLKOUT0, PLL_3A_FBP, PLL_3A_FB0, LVDS3A_15P, DQ62BG18
IO, LVDS3A_16N, DQSN62BJ18
IO, LVDS3A_16P, DQS62BJ17
IO, LVDS3A_17N, DQ62BK16
IO, LVDS3A_17P, DQ62BK17
IO, LVDS3A_18N, DQ62BL15
IO, LVDS3A_18P, DQ62BK15
IO, LVDS3A_19N, DQ63BF18
IO, LVDS3A_19P, DQ63BF19
IO, LVDS3A_20N, DQ63BE19
IO, LVDS3A_20P, DQ63BE20
IO, LVDS3A_21N, DQ63BH19
IO, LVDS3A_21P, DQ63BH20
IO, LVDS3A_22N, DQSN63BF20
IO, LVDS3A_22P, DQS63BG20
IO, LVDS3A_23N, DQ63BL17
IO, LVDS3A_23P, DQ63BL18
IO, LVDS3A_24N, DQ63BJ19
IO, LVDS3A_24P, DQ63BK19
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Bank 3BGPIO
Place these resesitors near to MAX10
CLK_SYS_100M_NCLK_SYS_100M_P
ZQSFP0_1V8_MODSEL_LZQSFP1_1V8_MODSEL_LZQSFP0_1V8_RESET_LZQSFP1_1V8_RESET_LZQSFP0_1V8_LPMODEZQSFP1_1V8_LPMODE
PCIE_EP_I2C_SCLPCIE_EP_I2C_SDAPCIE_EP_WAKEN
1p8V 3p3V
1p8V 3p3V
1p8V
CPU_RESETn43,45CLK_SYS_100M_N40CLK_SYS_100M_P40
ZQSFP0_1V8_MODPRS_L45ZQSFP0_1V8_RESET_L45
ZQSFP0_1V8_LPMODE45ZQSFP0_1V8_INT_L45
ZQSFP1_1V8_MODPRS_L45ZQSFP1_1V8_RESET_L45
ZQSFP1_1V8_LPMODE45ZQSFP1_1V8_INT_L45
ZQSFP_S10_I2C_SCL32ZQSFP_S10_I2C_SDA32
ZQSFP_I2C_SCL 25,26ZQSFP_I2C_SDA 25,26
ZQSFP0_1V8_MODSEL_L45
ZQSFP1_1V8_MODSEL_L45
PCIE_EP_I2C_SCL27PCIE_EP_I2C_SDA27PCIE_EP_WAKEN27
PCIE_RT_S10_WAKEN45PCIE_RT_S10_PERSTn45
PCIE_RT_S10_PRSNT2n45
ZQSFP_S10_I2C_SCL32
ZQSFP_S10_I2C_SDA32
MAIN_I2C_SCL40,41,42,45MAIN_I2C_SDA40,41,42,45
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
32 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
32 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
32 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C302
0.1uF
R151 10.0K
R148 10.0K
R153 10.0K
R166 10.0K
R156 10.0K
R159 DNI
R161 100
R155 10.0K
R157 DNIR160 DNI
R162 10.0K
R158 DNI
IO BANK 3B
1SM210H_UF53
U2P
IO, LVDS3B_1N, DQ56AR15
IO, LVDS3B_1P, DQ56AT15
IO, LVDS3B_2N, DQ56AU15
IO, LVDS3B_2P, DQ56AV15
IO, LVDS3B_3N, DQ56AV14
IO, LVDS3B_3P, DQ56AW14
IO, LVDS3B_4N, DQSN56BA14
IO, LVDS3B_4P, DQS56AY14
IO, LVDS3B_5N, DQ56BA15
IO, LVDS3B_5P, DQ56BB15
IO, LVDS3B_6N, DQ56BC15
IO, LVDS3B_6P, DQ56BC14
IO, LVDS3B_7N, DQ57BD14
IO, LVDS3B_7P, DQ57BE14
IO, LVDS3B_8N, DQ57BF13
IO, LVDS3B_8P, DQ57BF14
IO, LVDS3B_9N, DQ57BG13
IO, LVDS3B_9P, DQ57BH13
IO, PLL_3B_CLKOUT1N, LVDS3B_10N, DQSN57BJ12
IO, PLL_3B_CLKOUT1P, PLL_3B_CLKOUT1, PLL_3B_FBN, LVDS3B_10P, DQS57BJ13
IO, LVDS3B_11N, DQ57BK14
IO, RZQ_3B, LVDS3B_11P, DQ57BJ14
IO, CLK_3B_1N, LVDS3B_12N, DQ57BL13
IO, CLK_3B_1P, LVDS3B_12P, DQ57BL14
IO, CLK_3B_0N, LVDS3B_13N, DQ58AU16
IO, CLK_3B_0P, LVDS3B_13P, DQ58AU17
IO, LVDS3B_14N, DQ58AR17
IO, LVDS3B_14P, DQ58AT17
IO, PLL_3B_CLKOUT0N, LVDS3B_15N, DQ58AY17
IO, PLL_3B_CLKOUT0P, PLL_3B_CLKOUT0, PLL_3B_FBP, PLL_3B_FB0, LVDS3B_15P, DQ58AW17
IO, LVDS3B_16N, DQSN58AV16
IO, LVDS3B_16P, DQS58AW16
IO, LVDS3B_17N, DQ58BC16
IO, LVDS3B_17P, DQ58BB16
IO, LVDS3B_18N, DQ58AY16
IO, LVDS3B_18P, DQ58AY15
IO, LVDS3B_19N, DQ59BE15
IO, LVDS3B_19P, DQ59BF15
IO, LVDS3B_20N, DQ59BA17
IO, LVDS3B_20P, DQ59BB17
IO, LVDS3B_21N, DQ59BG15
IO, LVDS3B_21P, DQ59BG16
IO, LVDS3B_22N, DQSN59BD16
IO, LVDS3B_22P, DQS59BE16
IO, LVDS3B_23N, DQ59BJ16
IO, LVDS3B_23P, DQ59BH16
IO, LVDS3B_24N, DQ59BH14
IO, LVDS3B_24P, DQ59BH15
R164 10.0KR163 10.0K
U15
FXMA2102UMX
A02
A13B0
7
B16
VCCA1
GND4
OE5
VCCB8
R149 10.0K
R165 10.0K
R150 10.0K
R152 DNIR154 DNI
C301
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UIB eSRAM
ATB0_LATB0_RATB1_LATB1_R
CLK_UIB0_NCLK_UIB0_PCLK_UIB1_NCLK_UIB1_P
CLK_ESRAM0_NCLK_ESRAM0_PCLK_ESRAM1_NCLK_ESRAM1_P
CLK_ESRAM0_PCLK_ESRAM0_N
CLK_ESRAM1_PCLK_ESRAM1_N
CLK_UIB0_PCLK_UIB0_N
CLK_UIB1_PCLK_UIB1_N
S10_PCIE_PERSTn0 27CLK_ESRAM0_P40CLK_ESRAM0_N40
CLK_ESRAM1_P40CLK_ESRAM1_N40
CLK_UIB0_P40CLK_UIB0_N40
CLK_UIB1_P40CLK_UIB1_N40
S10_PCIE_PERSTn1 43
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
33 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
33 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
33 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R169 2K
V45
V38
BANK 6A/6C/7A/7C, UIB, ESRAM
1SM210H_UF53
U2R
CLK_ESRAM_0NAU32
CLK_ESRAM_0PAU31
RREF_ESRAM_0AU35
ESRAM0_TEST_DEBUG0_ESRAMAU33
ESRAM0_TEST_DEBUG1_ESRAMAT30
ESRAM0_TEST_DEBUG2_ESRAMAU36
ESRAM0_TEST_DEBUG3_ESRAMAU30
CLK_ESRAM_1NU31
CLK_ESRAM_1PV31
RREF_ESRAM_1V34
DNU,ATB0_ESRAM1T28
DNU,ATB1_ESRAM1V35
ESRAM1_TEST_DEBUG0_ESRAMU35
ESRAM1_TEST_DEBUG1_ESRAMT29
ESRAM1_TEST_DEBUG2_ESRAMV36
ESRAM1_TEST_DEBUG3_ESRAMU30
UIB_PLL_REF_CLK_00_NAP26
UIB_PLL_REF_CLK_00_PAR26
UIB00_TEST_DEBUG0_UIBAT27
UIB00_TEST_DEBUG1_UIBAT28
UIB00_TEST_DEBUG2_UIBAR27
UIB00_TEST_DEBUG3_UIBAT29
UIB_RREF_00AW23
UIB_PLL_REF_CLK_01_NR27
UIB_PLL_REF_CLK_01_PP27
UIB01_TEST_DEBUG0_UIBT27
UIB01_TEST_DEBUG1_UIBU27
UIB01_TEST_DEBUG2_UIBU28
UIB01_TEST_DEBUG3_UIBV28
UIB_RREF_01N24
DNU,EDM_INAN38
DNU,EDM_OUTAP38
DIODEHB8
DIODELA8
TEMPDIODE1nAT38
TEMPDIODE1pAR39
IO3V0_10, NPERSTL0AH39
IO3V1_10AK39
IO3V2_10AJ39
IO3V3_10AM38
IO3V4_10AL38
IO3V5_10AL39
IO3V6_10AN39
IO3V7_10AP39
DNU79AU38
TEMPDIODE3nAC40
TEMPDIODE3pAA40
IO3V0_12, NPERSTL2Y39
IO3V1_12AC38
IO3V2_12AC39
IO3V3_12AD38
IO3V4_12AA39
IO3V5_12AA38
IO3V6_12AB38
IO3V7_12AD39
DNU80AG38
TEMPDIODE4nBA12
TEMPDIODE4pBB11
IO3V0_20, NPERSTR0BL10
IO3V1_20BK10
IO3V2_20BH10
IO3V3_20BG10
IO3V4_20BF10
IO3V5_20BE10
IO3V6_20BD10
IO3V7_20BC10
DNU81BK9
TEMPDIODE6nAJ12
TEMPDIODE6pAG12
IO3V0_22, NPERSTR2AG13
IO3V1_22AH13
IO3V2_22AJ13
IO3V3_22AL13
IO3V4_22AM13
IO3V5_22AN13
IO3V6_22AP13
IO3V7_22AF13
DNU82AE14
DNU,ATB0_LAE39
DNU,ATB0_RAC14
DNU,ATB1_LAF38
DNU,ATB1_RAD14
R173 DNI
R171 DNI
V46
V35V36
R170 2K
V49
V39
V37
V50
V40
V51
V41
V52
V42
R172 DNI
R167 240 (1%)
V31
V47
R174 DNI
V32
V48
V33
R168 240 (1%)
V34
V43V44
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA Power 1
VCCLSENSEGNDSENSE
S10MX_VCC
S10MX_VCC
VCC_SENSE53VSS_SENSE53
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
34 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
34 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
34 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
1SM210H_UF53
U2U
VCCY35
VCCY34
VCCY31
VCCY30
VCCY29
VCCY27
VCCY26
VCCY25
VCCY24
VCCY22
VCCY21
VCCY20
VCCY19
VCCY17
VCCW34
VCCW33
VCCW31
VCCW29
VCCW28
VCCW27
VCCW26
VCCW24
VCCW22
VCCW21
VCCW19
VCCW18
VCCW17
VCCV25
VCCV24
VCCV23
VCCV21
VCCV20
VCCV19
VCCAP24
VCCAP23
VCCAP22
VCCAP21
VCCAN35
VCCAN34
VCCAN33
VCCAB16
VCCAA35
VCCAA34
VCCAA33
VCCAA30
VCCAA29
VCCAA28
VCCAA27
VCCAA25
VCCAA24
VCCAA22
VCCAA20
VCCAA19
VCCAA18
VCCAA17
VCCLSENSEAF27
GNDSENSEAF28
VCCPY32
VCCPW32
VCCPW23
VCCPAN23
VCCPAM32
VCCPAM23
VCCPAL32
VCCPAL23
VCCPAK32
VCCPAJ32
VCCPAC23
VCCPAB32
VCCPAB23
VCCPAA32
VCCPAA23
VCCAJ36
VCCAJ34
VCCAJ33
VCCAJ31
VCCAJ29
VCCAJ28
VCCAJ27
VCCAJ26
VCCAJ24
VCCAJ23
VCCAJ22
VCCAJ21
VCCAJ19
VCCAJ18
VCCAJ17
VCCAJ16
VCCAH36
VCCAH35
VCCAH34
VCCAH33
VCCAH31
VCCAH30
VCCAH29
VCCAH28
VCCAH26
VCCAH25
VCCAH24
VCCAH23
VCCAH21
VCCAH20
VCCAH19
VCCAH18
VCCAH16
VCCAG36
VCCAG35
VCCAG33
VCCAG20
VCCAG18
VCCAG17
VCCAG16
VCCAF35
VCCAF34
VCCAF33
VCCAF20
VC
CA
F1
9V
CC
AF
18
VC
CA
F1
7V
CC
AE
36
VC
CA
E3
5
VC
CA
E3
4
VC
CA
E2
0
VC
CA
E1
9
VC
CA
E1
7
VC
CA
E1
6
VC
CA
D3
6
VC
CA
D3
4
VC
CA
D3
3
VC
CA
D3
2
VC
CA
D3
1
VC
CA
D2
9
VC
CA
D2
8
VC
CA
D2
7
VC
CA
D2
6
VC
CA
D2
4
VC
CA
D2
3
VC
CA
D2
2
VC
CA
D2
1
VC
CA
D1
9
VC
CA
D1
8
VC
CA
D1
7
VC
CA
D1
6
VC
CA
C3
6
VC
CA
C3
5
VC
CA
C3
4
VC
CA
C3
3
VC
CA
C3
1
VC
CA
C3
0
VC
CA
C2
9
VC
CA
C2
8
VC
CA
C2
6
VC
CA
C2
5
VC
CA
C2
4
VC
CA
C2
1
VC
CA
C2
0
VC
CA
C1
9
VC
CA
C1
8
VC
CA
C1
6
VC
CA
B3
6
VC
CA
B3
5
VC
CA
B3
3
VC
CA
B3
1
VC
CA
B3
0
VC
CA
B2
8
VC
CA
B2
7
VC
CA
B2
6
VC
CA
B2
5
VC
CA
B2
2
VC
CA
B2
1
VC
CA
B2
0
VC
CA
B1
8
VC
CA
B1
7
VC
CA
N3
1
VC
CA
N3
0
VC
CA
N2
9
VC
CA
N2
8
VC
CA
N2
6
VC
CA
N2
5
VC
CA
N2
4
VC
CA
N2
1
VC
CA
N2
0
VC
CA
N1
9
VC
CA
N1
8
VC
CA
M3
5
VC
CA
M3
3
VC
CA
M3
1
VC
CA
M3
0
VC
CA
M2
8
VC
CA
M2
7
VC
CA
M2
6
VC
CA
M2
5
VC
CA
M2
2
VC
CA
M2
1
VC
CA
M2
0
VC
CA
M1
8
VC
CA
M1
7
VC
CA
L3
5
VC
CA
L3
4
VC
CA
L3
3
VC
CA
L3
0
VC
CA
L2
9
VC
CA
L2
8
VC
CA
L2
7
VC
CA
L2
5
VC
CA
L2
4
VC
CA
L2
2
VC
CA
L2
0
VC
CA
L1
9
VC
CA
L1
8
VC
CA
L1
7
VC
CA
K3
6
VC
CA
K3
5
VC
CA
K3
4
VC
CA
K3
1
VC
CA
K3
0
VC
CA
K2
9
VC
CA
K2
7
VC
CA
K2
6
VC
CA
K2
5
VC
CA
K2
4
VC
CA
K2
2
VC
CA
K2
1
VC
CA
K2
0
VC
CA
K1
9
VC
CA
K1
7
C303 0.1uF
R175 0R176 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA Power 2
S10_VCCT_GXB
1p8V_FLTR
1p8V_FLTR
S10_VCCERAMS10_VCCRR_GXB
S10_VCCRL_GXB
1p8V_FLTR
1p8V
1p8V_FLTR1p8V
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
35 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
35 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
35 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
FB10
80ohm @ 100Mhz5A, 10mOhm
C305
0.1uF
FB8
80ohm @ 100Mhz5A, 10mOhm
C304
0.1uF
C306
0.1uF
FB9
80ohm @ 100Mhz5A, 10mOhm
1SM210H_UF53
U2V
VCCA_PLLAF30
VCCA_PLLAF29
VCCA_PLLAF24
VCCA_PLLAF23
VCCADCAR29
VCCBATAP31
VCCH_GXBLAV41
VCCH_GXBLAP41
VCCH_GXBLAK41
VCCH_GXBLAF41
VCCH_GXBLV41
VCCH_GXBLP41
VCCH_GXBLK41
VCCH_GXBLAB41
VCCH_GXBRAV11
VCCH_GXBRAP11
VCCH_GXBRAK11
VCCH_GXBRAF11
VCCH_GXBRV11
VCCH_GXBRP11
VCCH_GXBRK11
VCCH_GXBRAB11
VCCERAMY37
VCCERAMY36
VCCERAMY15
VCCERAMY14
VCCERAMW37
VCCERAMW36
VCCERAMV33
VCCERAMV30
VCCERAMV29
VCCERAMV26
VCCERAMV18
VCCERAMV15
VCCERAMU25
VCCERAMU22
VCCERAMU21
VCCERAMAR25
VCCERAMAR22
VCCERAMAR21
VCCERAMAP37
VCCERAMAP36
VCCERAMAP34
VCCERAMAP29
VCCERAMAP28
VCCERAMAP27
VCCERAMAP18
VCCERAMAN36
VCCERAMAN15
VCCERAMAM37
VCCERAMAM36
VCCERAMAM15
VCCERAMAL37
VCCERAMAL15
VCCERAMAK37
VCCERAMAK15
VCCERAMAJ37
VCCERAMAJ14
VCCERAMAH15
VCCERAMAH14
VCCERAMAG37
VCCERAMAG15
VCCERAMAF37
VCCERAMAF15
VCCERAMAF14
VCCERAMAE37
VCCERAMAE15
VCCERAMAD37
VCCERAMAC15
VCCERAMAB37
VCCERAMAB15
VCCERAMAA37
VCCERAMAA15
VCCERAMAA14
VCCR_GXBL1CAY43
VCCR_GXBL1CAY42
VCCR_GXBL1CAY41
VCCR_GXBL1DAT43
VCCR_GXBL1DAT42
VCCR_GXBL1DAT41
VCCR_GXBL1EAM43
VCCR_GXBL1EAM42
VCCR_GXBL1EAM41
VCCR_GXBL1FAH43
VCCR_GXBL1FAH42
VCCR_GXBL1FAH41
VCCR_GXBL1KAD43
VCCR_GXBL1KAD42
VCCR_GXBL1KAD41
VCCR_GXBL1LY43
VCCR_GXBL1LY42
VCCR_GXBL1LY41
VCCR_GXBL1MT43
VCCR_GXBL1MT42
VCCR_GXBL1MT41
VCCR_GXBL1NM43
VCCR_GXBL1NM42
VCCR_GXBL1NM41
VCCR_GXBR4CAY9
VCCR_GXBR4CAY11
VCCR_GXBR4CAY10
VCCR_GXBR4DAT9
VCCR_GXBR4DAT11
VCCR_GXBR4DAT10
VCCR_GXBR4EAM9
VCCR_GXBR4EAM11
VCCR_GXBR4EAM10
VCCR_GXBR4FAH9
VCCR_GXBR4FAH11
VCCR_GXBR4FAH10
VCCR_GXBR4KAD9
VCCR_GXBR4KAD11
VCCR_GXBR4KAD10
VCCR_GXBR4LY9
VCCR_GXBR4LY11
VCCR_GXBR4LY10
VCCR_GXBR4MT9
VCCR_GXBR4MT11
VCCR_GXBR4MT10
VCCR_GXBR4NM9
VCCR_GXBR4NM11
VCCR_GXBR4NM10
VCCT_GXBL1CAV43
VCCT_GXBL1CAV42
VCCT_GXBL1DAP43
VCCT_GXBL1DAP42
VCCT_GXBL1EAK43
VCCT_GXBL1EAK42
VCCT_GXBL1FAF43
VCCT_GXBL1FAF42
VCCT_GXBL1KAB43
VCCT_GXBL1KAB42
VCCT_GXBL1LV43
VCCT_GXBL1LV42
VCCT_GXBL1MP43
VCCT_GXBL1MP42
VCCT_GXBL1NK43
VCCT_GXBL1NK42
VCCT_GXBR4CAV9
VCCT_GXBR4CAV10
VCCT_GXBR4DAP9
VCCT_GXBR4DAP10
VCCT_GXBR4EAK9
VCCT_GXBR4EAK10
VCCT_GXBR4FAF9
VCCT_GXBR4FAF10
VCCT_GXBR4KAB9
VCCT_GXBR4KAB10
VCCT_GXBR4LV9
VCCT_GXBR4LV10
VCCT_GXBR4MP9
VCCT_GXBR4MP10
VCCT_GXBR4NK9
VCCT_GXBR4NK10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA Power 3
VCCFUSEWR_SDM is floating, Fuse can't be written
0p6V_DDR4_COMP_VREF
0p6V_DDR4_DIMM_VREF
MEM_VREF
1p8V
1p8V
1p8V
1p8V
1p8V
1p2V_VCCIO_UIB
VCCPLLDIG_SDM
VCCM
1p8V
HILO_VDDQ
1p8V
1p2V_DDR4
VCCFUSEWR_SDM
1p8V
1p2V_DDR4
1p8V
VCCPLL_SDM
S10_VCCERAM
MEM_VREF
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
36 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
36 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
36 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
1SM210H_UF53
U2W
VCCFUSEWR_SDMAR31
VCCIO_UIB_BLAY26
VCCIO_UIB_BLAY25
VCCIO_UIB_BLAY24
VCCIO_UIB_BLAY22
VCCIO_UIB_BLAY21
VCCIO_UIB_BLAW26
VCCIO_UIB_BLAW24
VCCIO_UIB_BLAW22
VCCIO_UIB_BLAW21
VCCIO_UIB_BLAV26
VCCIO_UIB_BLAV25
VCCIO_UIB_BLAV24
VCCIO_UIB_BLAV23
VCCIO_UIB_BLAV21
VCCIO_UIB_BLAU23
VCCIO_UIB_BLAU22
VCCIO_UIB_TLR25
VCCIO_UIB_TLR24
VCCIO_UIB_TLP26
VCCIO_UIB_TLP24
VCCIO_UIB_TLP23
VCCIO_UIB_TLP22
VCCIO_UIB_TLP21
VCCIO_UIB_TLN26
VCCIO_UIB_TLN25
VCCIO_UIB_TLN23
VCCIO_UIB_TLN21
VCCIO_UIB_TLM26
VCCIO_UIB_TLM25
VCCIO_UIB_TLM23
VCCIO_UIB_TLM22
VCCIO_UIB_TLM21
VCCM_WORD_BLBA24
VCCM_WORD_BLBA23
VCCM_WORD_BLBA22
VCCM_WORD_TLL24
VCCM_WORD_TLL23
VCCM_WORD_TLL22
VCCPTAG32
VCCPTAG31
VCCPTAG30
VCCPTAG28
VCCPTAG27
VCCPTAG26
VCCPTAG25
VCCPTAG23
VCCPTAG22
VCCPTAG21
VCCPTAF32
VCCPTAF22
VCCPTAE32
VCCPTAE31
VCCPTAE30
VCCPTAE29
VCCPTAE27
VCCPTAE26
VCCPTAE25
VCCPTAE24
VCCPTAE22
VCCPTAE21
VREFB2AN0AV36
VREFB2BN0AV35
VREFB2CN0AV31
VREFB2FN0AV28
VREFB2KN0T30
VREFB2LN0U32
VREFB2MN0U36
VREFB2NN0W38
VREFB3AN0AP19
VREFB3BN0AR16
VREFB3CN0AP14
VREFB3IN0W14
VREFB3JN0U15
VREFB3KN0T17
VREFB3LN0R19
VCCIO3VAJ38
VCCIO3VAH38
VCCIO3VAL14
VCCIO3VAK14
VCCIO2ABA36
VCCIO2AAY38
VCCIO2AAV37
VCCIO2BBC32
VCCIO2BAY33
VCCIO2BAV32
VCCIO2CBD30
VCCIO2CBB29
VCCIO2CAY28
VCCIO2FBC27
VCCIO2FBA26
VCCIO2FAV27
VCCIO2KP30
VCCIO2KM29
VCCIO2KJ30
VCCIO2LR33
VCCIO2LN32
VCCIO2LK33
VCCIO2ML36
VCCIO2MJ35
VCCIO2MH37
VCCIO2NU39
VCCIO2NR38
VCCIO2NM39
VCCIO3ABB19
VCCIO3AAW20
VCCIO3AAU19
VCCIO3BBA16
VCCIO3BAW15
VCCIO3BAT16
VCCIO3CAU14
VCCIO3CAR13
VCCIO3CAN14
VCCIO3IY13
VCCIO3IW13
VCCIO3IAA13
VCCIO3JT16
VCCIO3JP15
VCCIO3JL16
VCCIO3KN17
VCCIO3KM19
VCCIO3KK18
VCCIO3LK23
VCCIO3LJ25
VCCIO3LG24
VCCIO_SDMAR30
VCCPLLDIG_SDMAT33
VCCPLL_SDMAP32
C307
0.1uF
C157 0.1uF FB1780ohm @ 100Mhz 5A, 10mOhm
C1528
1uF, DNI
C159 0.1uFFB11
80ohm @ 100Mhz5A, 10mOhm
C161 0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
37 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
37 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
37 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
1SM210H_UF53
U2X
GNDY6
GNDY51
GNDY50
GNDY5
GNDY47
GNDY46
GNDY40
GNDY38
GNDY33
GNDY28
GNDY23
GNDY2
GNDY18
GNDY12
GNDY1
GNDW8
GNDW7
GNDW49
GNDW48
GNDW45
GNDW44
GNDW41
GNDW40
GNDW4
GNDW35
GNDW30
GNDW3
GNDW25
GNDW20
GNDW15
GNDW12
GNDW11
GNDV6
GNDV51
GNDV50
GNDV5
GNDV47
GNDV46
GNDV40
GNDV37
GNDV32
GNDV27
GNDV22
GNDV2
GNDV17
GNDV12
GNDAA16
GNDAA12
GNDAA11
GNDA7
GNDA50
GNDA49
GNDA45
GNDA43
GNDA41
GNDA4
GNDA36
GNDA31
GNDA3
GNDA26
GNDA21
GNDA2
GNDA16
GNDA11
GNDAT34
GNDU33
GNDN48
GNDN45
GNDN44
GNDN41
GNDN40
GNDN4
GNDN37
GNDN3
GNDN27
GNDN22
GNDN12
GNDN11
GNDM6
GNDM51
GNDM50
GNDM5
GNDM47
GNDM46
GNDM40
GNDM34
GNDM24
GNDM2
GNDM14
GNDM12
GNDM1
GNDL8
GNDL7
GNDL49
GNDL48
GNDL45
GNDL44
GNDL41
GNDL40
GNDL4
GNDL31
GNDL3
GNDL26
GNDL21
GNDL12
GNDL11
GNDK6
GNDK51
GNDK50
GNDK5
GNDK47
GNDK46
GNDK40
GNDK38
GNDK28
GNDK2
GNDK13
GNDK12
GNDK1
GNDJ9
GNDJ8
GNDJ7
GNDJ49
GNDJ48
GNDJ45
GNDJ44
GNDJ43
GNDJ42
GNDJ41
GNDJ40
GNDJ4
GN
DJ3
GN
DJ2
0
GN
DJ1
5
GN
DJ1
2
GN
DJ1
1
GN
DJ1
0
GN
DH
9
GN
DH
6
GN
DH
51
GN
DH
50
GN
DH
5
GN
DH
47
GN
DH
46
GN
DH
43
GN
DH
32
GN
DH
27
GN
DH
22
GN
DH
2
GN
DH
17
GN
DH
12
GN
DH
1
GN
DG
9
GN
DG
8
GN
DG
7
GN
DG
49
GN
DG
48
GN
DG
45
GN
DG
44
GN
DG
43
GN
DG
4
GN
DG
39
GN
DG
34
GN
DG
3
GN
DG
29
GN
DG
19
GN
DG
14
GN
DG
13
GN
DF
9
GN
DF
6
GN
DF
51
GN
DF
50
GN
DF
5
GN
DF
47
GN
DF
46
GN
DF
43
GN
DF
41
GN
DF
36
GN
DF
31
GN
DF
26
GN
DF
21
GN
DF
2
GN
DF
16
GN
DF
11
GN
DF
1
GN
DE
9
GN
DE
8
GN
DE
7
GN
DE
50
GN
DE
49
GN
DE
48
GN
DE
45
GN
DE
44
GN
DE
43
GN
DV
1
GN
DU
8
GN
DU
7
GN
DU
49
GN
DU
48
GN
DU
45
GN
DU
44
GN
DU
41
GN
DU
40
GN
DU
4
GN
DU
34
GN
DU
3
GN
DU
29
GN
DU
24
GN
DU
19
GN
DU
14
GN
DU
12
GN
DU
11
GN
DT
6
GN
DT
51
GN
DT
50
GN
DT
5
GN
DT
47
GN
DT
46
GN
DT
40
GN
DT
36
GN
DT
31
GN
DT
26
GN
DT
21
GN
DT
2
GN
DT
12
GN
DT
1
GN
DR
8
GN
DR
7
GN
DR
49
GN
DR
48
GN
DR
45
GN
DR
44
GN
DR
41
GN
DR
40
GN
DR
4
GN
DR
3
GN
DR
28
GN
DR
23
GN
DR
18
GN
DR
13
GN
DR
12
GN
DR
11
GN
DP
6
GN
DP
51
GN
DP
50
GN
DP
5
GN
DP
47
GN
DP
46
GN
DP
40
GN
DP
35
GN
DP
25
GN
DP
20
GN
DP
2
GN
DP
12
GN
DP
1
GN
DN
8
GN
DN
7
GN
DN
49
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
38 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
38 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
38 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.1SM210H_UF53
U2Y
GNDE4
GNDE38
GNDE33
GNDE3
GNDE28
GNDE23
GNDE18
GNDE13
GNDD9
GNDD6
GNDD50
GNDD5
GNDD47
GNDD46
GNDD43
GNDD40
GNDD35
GNDD30
GNDD25
GNDD20
GNDD2
GNDD15
GNDD10
GNDD1
GNDC9
GNDC8
GNDC7
GNDC51
GNDC49
GNDC48
GNDC45
GNDC44
GNDC43
GNDC4
GNDC37
GNDC32
GNDC3
GNDC27
GNDC22
GNDC2
GNDC17
GNDC12
GNDC1
GNDBL9
GNDBL7
GNDBL50
GNDBL49
GNDBL48
GNDBL45
GNDBL41
GNDBL4
GNDBL36
GNDBL31
GNDBL3
GNDBL26
GNDBL21
GNDBL2
GNDBL16
GNDBL11
GNDBK8
GNDBK7
GNDBK6
GNDBK51
GNDBK50
GNDBK5
GNDBK47
GNDBK46
GNDBK45
GNDBK43
GNDBK38
GNDBK33
GNDBK28
GNDBK23
GNDBK2
GNDBK18
GNDBE7
GNDBE49
GNDBE48
GNDBE45
GNDBE44
GNDBE43
GNDBE4
GNDBE38
GNDBE33
GNDBE3
GNDBE28
GNDBE23
GNDBE18
GNDBE13
GNDBD9
GNDBD6
GNDBD51
GNDBD50
GNDBD5
GNDBD47
GNDBD46
GNDBD43
GNDBD40
GNDBD35
GNDBD25
GNDBD20
GNDBD2
GNDBD15
GNDBD1
GNDBC9
GNDBC8
GNDBC7
GNDBC49
GNDBC48
GNDBC45
GNDBC44
GNDBC43
GNDBC4
GNDBC37
GNDBC3
GNDBC22
GNDBC17
GNDBC12
GNDBB9
GNDBB6
GNDBB51
GNDBB50
GNDBB5
GNDBB47
GNDBB46
GNDBB43
GNDBB42
GNDBB41
GNDBB39
GNDBB38
GNDBB34
GNDBB24
GNDBB2
GNDBB14
GNDBB10
GNDBB1
GNDBA8
GNDBA7
GNDBA49
GNDBA48
GNDBA45
GNDBA44
GNDBA41
GNDBA40
GNDBA4
GNDBA31
GNDBA3
GNDBA21
GNDBA11
GNDB9
GN
DB
7
GN
DB
6
GN
DB
51
GN
DB
5
GN
DB
49
GN
DB
47
GN
DB
46
GN
DB
45
GN
DB
43
GN
DB
4
GN
DB
39
GN
DB
34
GN
DB
29
GN
DB
24
GN
DB
19
GN
DB
14
GN
DB
1
GN
DA
Y6
GN
DA
Y5
1
GN
DA
Y5
0
GN
DA
Y5
GN
DA
Y4
7
GN
DA
Y4
6
GN
DA
Y4
0
GN
DA
Y2
3
GN
DA
Y2
GN
DA
Y1
8
GN
DA
Y1
3
GN
DA
Y1
2
GN
DA
Y1
GN
DA
W8
GN
DA
W7
GN
DA
W4
9
GN
DA
W4
8
GN
DA
W4
5
GN
DA
W4
4
GN
DA
W4
1
GN
DA
W4
0
GN
DA
W4
GN
DA
W3
5
GN
DA
W3
0
GN
DA
W3
GN
DA
W2
5
GN
DA
W1
2
GN
DA
W1
1
GN
DA
V6
GN
DA
V5
1
GN
DA
V5
0
GN
DA
V5
GN
DA
V4
7
GN
DA
V4
6
GN
DA
V4
0
GN
DA
V2
2
GN
DA
V2
GN
DA
V1
7
GN
DA
V1
2
GN
DA
V1
GN
DA
U8
GN
DA
U7
GN
DA
U4
9
GN
DA
U4
8
GN
DA
U4
5
GN
DA
U4
4
GN
DA
U4
1
GN
DA
U4
0
GN
DA
U4
GN
DA
U3
9
GN
DA
U3
4
GN
DA
U3
GN
DA
U2
9
GN
DA
U2
4
GN
DA
U1
2
GN
DA
U1
1
GN
DA
T6
GN
DB
K1
3
GN
DB
K1
GN
DB
J9
GN
DB
J8
GN
DB
J7
GN
DB
J5
1
GN
DB
J5
0
GN
DB
J4
9
GN
DB
J4
8
GN
DB
J4
5
GN
DB
J4
4
GN
DB
J4
3
GN
DB
J4
0
GN
DB
J4
GN
DB
J3
5
GN
DB
J3
0
GN
DB
J3
GN
DB
J2
5
GN
DB
J2
0
GN
DB
J2
GN
DB
J1
5
GN
DB
J1
0
GN
DB
J1
GN
DB
H9
GN
DB
H6
GN
DB
H5
1
GN
DB
H5
0
GN
DB
H5
GN
DB
H4
7
GN
DB
H4
6
GN
DB
H4
3
GN
DB
H4
2
GN
DB
H3
7
GN
DB
H3
2
GN
DB
H2
7
GN
DB
H2
2
GN
DB
H2
GN
DB
H1
7
GN
DB
H1
2
GN
DB
H1
GN
DB
G9
GN
DB
G8
GN
DB
G7
GN
DB
G4
9
GN
DB
G4
8
GN
DB
G4
5
GN
DB
G4
4
GN
DB
G4
3
GN
DB
G4
GN
DB
G3
9
GN
DB
G3
4
GN
DB
G3
GN
DB
G2
9
GN
DB
G2
4
GN
DB
G1
9
GN
DB
G1
4
GN
DB
F9
GN
DB
F6
GN
DB
F5
1
GN
DB
F5
0
GN
DB
F5
GN
DB
F4
7
GN
DB
F4
6
GN
DB
F4
3
GN
DB
F4
1
GN
DB
F3
6
GN
DB
F3
1
GN
DB
F2
6
GN
DB
F2
1
GN
DB
F2
GN
DB
F1
6
GN
DB
F1
1
GN
DB
F1
GN
DB
E9
GN
DB
E8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
39 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
39 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
39 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
1SM210H_UF53
U2Z
GNDAT51
GNDAT50
GNDAT5
GNDAT47
GNDAT46
GNDAT40
GNDAT36
GNDAT31
GNDAT26
GNDAT21
GNDAT2
GNDAT12
GNDAT1
GNDAR8
GNDAR7
GNDAR49
GNDAR48
GNDAR45
GNDAR44
GNDAR41
GNDAR40
GNDAR4
GNDAR38
GNDAR33
GNDAR3
GNDAR28
GNDAR23
GNDAR18
GNDAR12
GNDAR11
GNDAP6
GNDAP51
GNDAP50
GNDAP5
GNDAP49
GNDAP48
GNDAP47
GNDAP46
GNDAP40
GNDAP35
GNDAP30
GNDAP25
GNDAP20
GNDAP2
GNDAP15
GNDAP12
GNDAP1
GNDAN8
GNDAN7
GNDAN49
GNDAN48
GNDAN47
GNDAN46
GNDAN45
GNDAN44
GNDAN41
GNDAN40
GNDAN4
GNDAN37
GNDAN32
GNDAN3
GNDAN27
GNDAN22
GNDAN17
GNDAN12
GNDAJ11
GNDAH6
GNDAH51
GNDAH50
GNDAH5
GNDAH47
GNDAH46
GNDAH40
GNDAH37
GNDAH32
GNDAH27
GNDAH22
GNDAH2
GNDAH17
GNDAH12
GNDAH1
GNDAG8
GNDAG7
GNDAG49
GNDAG48
GNDAG45
GNDAG44
GNDAG41
GNDAG40
GNDAG4
GNDAG39
GNDAG34
GNDAG3
GNDAG29
GNDAG24
GNDAG19
GNDAG14
GNDAG11
GNDAF6
GNDAF51
GNDAF50
GNDAF5
GNDAF47
GNDAF46
GNDAF40
GNDAF36
GNDAF31
GNDAF26
GNDAF25
GNDAF21
GNDAF2
GNDAF16
GNDAF12
GNDAF1
GNDAE8
GNDAE7
GNDAE49
GNDAE48
GNDAE45
GNDAE44
GNDAE41
GNDAE40
GNDAE4
GNDAE38
GNDAE33
GNDAE3
GNDAE28
GNDAE23
GNDAE18
GNDAE13
GN
DA
E1
2
GN
DA
E1
1
GN
DA
D6
GN
DA
D5
1
GN
DA
D5
0
GN
DA
D5
GN
DA
D4
7
GN
DA
D4
6
GN
DA
D4
0
GN
DA
D3
5
GN
DA
D3
0
GN
DA
D2
5
GN
DA
D2
0
GN
DA
D2
GN
DA
D1
5
GN
DA
D1
2
GN
DA
D1
GN
DA
C8
GN
DA
C7
GN
DA
C4
9
GN
DA
C4
8
GN
DA
C4
5
GN
DA
C4
4
GN
DA
C4
1
GN
DA
C4
GN
DA
C3
7
GN
DA
C3
2
GN
DA
C3
GN
DA
C2
7
GN
DA
C2
2
GN
DA
C1
7
GN
DA
C1
3
GN
DA
C1
2
GN
DA
C1
1
GN
DA
B6
GN
DA
B5
1
GN
DA
B5
0
GN
DA
B5
GN
DA
B4
7
GN
DA
B4
6
GN
DA
B4
0
GN
DA
B3
9
GN
DA
B3
4
GN
DA
B2
9
GN
DA
B2
4
GN
DA
B2
GN
DA
B1
9
GN
DA
B1
4
GN
DA
B1
3
GN
DA
B1
2
GN
DA
B1
GN
DA
A8
GN
DA
A7
GN
DA
A4
9
GN
DA
A4
8
GN
DA
A4
5
GN
DA
A4
4
GN
DA
A4
1
GN
DA
A4
GN
DA
A3
6
GN
DA
A3
1
GN
DA
A3
GN
DA
A2
6
GN
DA
A2
1
GN
DA
N1
1
GN
DA
M6
GN
DA
M5
1
GN
DA
M5
0
GN
DA
M5
GN
DA
M4
7
GN
DA
M4
6
GN
DA
M4
0
GN
DA
M3
9
GN
DA
M3
4
GN
DA
M2
9
GN
DA
M2
4
GN
DA
M2
GN
DA
M1
9
GN
DA
M1
4
GN
DA
M1
2
GN
DA
M1
GN
DA
L8
GN
DA
L7
GN
DA
L4
9
GN
DA
L4
8
GN
DA
L4
5
GN
DA
L4
4
GN
DA
L4
1
GN
DA
L4
0
GN
DA
L4
GN
DA
L3
6
GN
DA
L3
1
GN
DA
L3
GN
DA
L2
6
GN
DA
L2
1
GN
DA
L1
6
GN
DA
L1
2
GN
DA
L1
1
GN
DA
K6
GN
DA
K5
1
GN
DA
K5
0
GN
DA
K5
GN
DA
K4
7
GN
DA
K4
6
GN
DA
K4
0
GN
DA
K3
8
GN
DA
K3
3
GN
DA
K2
8
GN
DA
K2
3
GN
DA
K2
GN
DA
K1
8
GN
DA
K1
3
GN
DA
K1
2
GN
DA
K1
GN
DA
J8
GN
DA
J7
GN
DA
J4
9
GN
DA
J4
8
GN
DA
J4
5
GN
DA
J4
4
GN
DA
J4
1
GN
DA
J4
0
GN
DA
J4
GN
DA
J3
5
GN
DA
J3
0
GN
DA
J3
GN
DA
J2
5
GN
DA
J2
0
GN
DA
J1
5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Clock 1
Default LVDS 100 MHz
Default LVDS 644.53125 MHz
set IO_VDD_SEL = 0,select VDDIO = VDD
7-bit I2C Address 74h
Default LVDS 644.53125 MHz
Default LVDS 100 MHz
Default LVDS 100 MHz
Default LVDS 100 MHz
Default LVDS 100 MHz
Default LVDS 100 MHz
Default LVDS 100 MHz
Default LVDS 100 MHz
SI5341_XA
SI5341_XBSI5341_X2
SI5341_X1
SI5341_OUT0nSI5341_OUT0p
SI5341_A0
SI5341_ENnSI5341_IN_SEL0SI5341_IN_SEL1
SI5341_A1
SI5341_IN_SEL1SI5341_IN_SEL0
SI5341_RSTn
SI5341_I2C_SEL
SI5341_A1SI5341_A0
SI5341_OUT1nSI5341_OUT1p
SI5341_OUT7nSI5341_OUT7p
SI5341_OUT8pSI5341_OUT8n
SI5341_OUT9pSI5341_OUT9n
SI5341_1p8V_VDDO 1p8V
SI5341_VDDA
1p8V
1p8V
SI5341_VDD
3p3V
1p8V
3p3V_STBY
REFCLK_ZQSFP0_N 22REFCLK_ZQSFP0_P 22
REFCLK_ZQSFP1_N 24REFCLK_ZQSFP1_P 24
CLK_UIB0_N 33CLK_UIB0_P 33
CLK_UIB1_N 33CLK_UIB1_P 33
CLK_ESRAM0_N 33CLK_ESRAM0_P 33
CLK_ESRAM1_N 33CLK_ESRAM1_P 33
CLK_SYS_100M_N 32CLK_SYS_100M_P 32
REFCLK_PCIE_RT_N 24REFCLK_PCIE_RT_P 24
REFCLK_PCIE_RT_SYS_P 28REFCLK_PCIE_RT_SYS_N 28
REFCLK_PCIE_EP_P 22REFCLK_PCIE_EP_N 22
CLK_PWR_M10 49CLK_UBII_M10 44
MAIN_I2C_SCL32,41,42,45MAIN_I2C_SDA32,41,42,45
SI5341_RSTn45
SI5341_ENn42,45
SI5341_FINC45SI5341_FDEC45
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
40 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
40 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
40 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C322
1uF
R185 22
C328 0.1uF
C314
1uF
C327 0.1uF
FB21
220ohm
R182 4.7K
C315
1uFC317
1uF
R177 1K
FB20
220ohm
Y1 48MHz
13
24
C316
1uF
C334 0.1uF
C325 0.1uF
C308
1uF
C318
1uF
R183 4.7K
U16
Si5341A-D08682-GM
VDD32
VDD46
VDD60
VDDA13
SDA_SDIO18
SCLK16
A1_SDO17
A0_CSB19
I2C_SEL39
OEB11
IN_SEL03
IN_SEL14
RSTB6
IN063
IN0_N64
IN11
IN1_N2
IN214
IN2_N15
FBIN61
FBIN_N62
X17
XA8
XB9
X210
ePAD65
VDDO022
VDDO126
VDDO229
VDDO333
OUT024
OUT0B23
OUT1B27OUT128
OUT2B30OUT231
OUT335
OUT3B34
INTRB12 LOLB47 SYNCB
5
RS
VD
12
0
OUT438
OUT4B37
OUT542
OUT5B41
OUT645
OUT6B44
OUT751
OUT7B50
OUT854
OUT8B53
OUT959
OUT9B58
FDEC25 FINC48
RS
VD
22
1
RS
VD
35
5
RS
VD
45
6
VDDO436
VDDO540
VDDO643
VDDO749
VDDO852
VDDO957
C336
0.1uF
C326 0.1uF
C333 0.1uF
FB22
220ohm
C309
1uF
U17
510MCA50M0000AAGR
VDD6
GND3
NC1
CLKp4
CLKn5
OE2
C319
1uF
R180
10.0K
C323
1uF
C330 0.1uF
C332 0.1uF
C310
1uF
R179 4.7K
R181
10.0K
C320
1uF
C329 0.1uF
C312
1uF
C331 0.1uF
FB12
220ohm
C324
1uF
R184 22
R178 1K
C311
1uF
C335
4.7uF
C321
1uF
C313
1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Clock 2
I2C Address = 70h
Si5338 Programmable Oscillator Use Clock Control GUI (Defaults CLK[0:3] = 100MHz, 125MHz, 100MHz, 50MHzI2C Address 70 HEX
I2C Address = 73h
Si5338 Programmable Oscillator Use Clock Control GUI (Defaults CLK[0:3] = 133.333MHz, 133.333MHz, 133.333MHz, NCI2C Address 73 HEX
Default LVDS 133.333 MHz
Default LVDS 133.333 MHz
Default LVDS 133.333 MHz
Default LVDS 100 MHz
Default LVDS 100 MHz
Default LVCOMS 125 MHz
Default LVDS 50 MHz
SI5338_CLK1_NSI5338_CLK1_P
1p8V1p8V_SI5338_1
1p8V1p8V_SI5338_2
CLK_DDR4_DIMM_N 10CLK_DDR4_DIMM_P 10
CLK_DDR4_COMP_N 15CLK_DDR4_COMP_P 15
CLK_HILO_MEM_N 19CLK_HILO_MEM_P 19
MAIN_I2C_SCL32,40,41,42,45
MAIN_I2C_SDA32,40,41,42,45
MAIN_I2C_SCL32,40,41,42,45
MAIN_I2C_SDA32,40,41,42,45
CLK_CORE_BAK_N 11CLK_CORE_BAK_P 11
REFCLK_PCIE_EP1_N 22REFCLK_PCIE_EP1_P 22
S10_OSC_CLK_1 30
CLK_SYS_50M_N 31CLK_SYS_50M_P 31
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
41 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
41 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
41 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C345 0.1uF
C343
0.1uF
C353
0.1uF
C354
0.1uF
C351
0.1uF
C342
0.1uF
R187 22
C341
0.1uF
C339
0.1uF
Y3
25.00MHz
13
24 C352
0.1uFC356 DNI
Y2
25.00MHz
13
24 C340
0.1uFC344 DNI
R188 4.7K
U19
Si5338B-B08686-GM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
L5BLM15AG221SN1
U18
Si5338B-B08683-GM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
R186 4.7K
C349 DNI
C337 DNI L4BLM15AG221SN1
C355
0.1uF
C346 0.1uF
C338
0.1uF
C350
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C And PMBUS
OPEN = EnableClosed = Disable
Resevered for Multi-master
To PWR MAX10, PWR Module, PCIe Root
Place R830, R831 near to U20
MAIN_PMBUS_EN3V3_I2C_EN
S10_PMBUS_EN
CORE_PMBUS_SCLCORE_PMBUS_SDA
1p8V
3p3V
1p8V 3p3V
1p8V
3p3V
1p8V
1p8V
3p3V
3p3V
3p3V
1p8V
S10_SDM_SCL30S10_SDM_SDA30
CORE_PMBUS_SCL 53CORE_PMBUS_SDA 53
S10_PMBUS_EN 45
MAIN_I2C_SCL32,40,41,45MAIN_I2C_SDA32,40,41,45
MAIN_PMBUS_EN 45
I2C_3V3_SCL 28,48,49,52I2C_3V3_SDA 28,48,49,52
3V3_I2C_EN 45
SI5341_ENn40,45
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
42 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
42 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
42 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R195 10.0K
U21
FXMA2102UMX
A02
A13B0
7
B16
VCCA1
GND4
OE5
VCCB8
C361
0.1uF
R203 1KR202 1K
R196 10.0K
R199 10.0K
R197 10.0K
R205 1K
R200 10.0K
OPEN
SW1
DIPSWITCH4
1234 5
678
U20
FXMA2102UMX
A02
A13B0
7
B16
VCCA1
GND4
OE5
VCCB8
R193 DNI
R189 10.0K
C359
0.1uF
R201 10.0K
R206 10.0K
C362
0.1uF
R198 10.0K
R204 1K
C360
0.1uF
R194 DNI
R191 10.0K
C357
0.1uF
R830 0 04025%
C358
0.1uF
R190 10.0K
R831 0 04025%
R192 10.0K
U22
FXMA2102UMX
A02
A13B0
7
B16
VCCA1
GND4
OE5
VCCB8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LEDs And PushButtons
POWER LED
Large Mounting holes on the rear of board Small Mounting holes on the front of boardLarge Mounting holes on the front of board
1p8V
3p3V
3p3V
5V
3p3V
CPU_RESETn 32,45
S10_PCIE_PERSTn1 33
S10_LED011
S10_LED111
S10_LED211
S10_LED311
S10_CONF_DONE30,45
S10_CVP_CONFDONE30,45
PWR_LED_DR48
OVERTEMPn49
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
43 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
43 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
43 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R820
DNI
R825 10.0K
C1557DNI
D8
GREEN_LED
R828 1K
MTH2
GND1
MTH4
GND1
R822 10.0K
R215 56.2
Q3
FDV305N
MTH6
GND1
D9
GREEN_LED
R824 10.0K
R218 56.2
R207 56.2
R224 56.2
S11PB Switch1 2
C1551 1000pF
R826 10.0K
Q4
FDV305N
D10
GREEN_LEDD5 RED_LED
Q5
FDV305N
Q8
FDV305N
R821 49.9
R211 56.2
S10PB Switch1 2
R227 DNI
D4 BLUE LED
R823 10.0K
R225 56.2
MTH3
GND1
R819 1K
D14
GREEN_LED
Q1
FDV305N
MTH1
GND1
R835DNI
C1552 1000pF
Q10
FDV305N
R220
10.0K
MTH5
GND1
D7
GREEN_LED
Q2
FDV305N
R827 1K
R219
10.0KD16
GREEN_LED
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UBII-MAX10 1
PLACE NEAR CY7C68013A
IFCLK = 48MHz
External JTAG Header
Bank 3: 3.3V IO
FX2_PA0
FX2_D_NFX2_D_P
VBUS_5V
FX2_PD4FX2_PD3
FX2_PD0FX2_PD1FX2_PD2
FX2_PD5FX2_PD6FX2_PD7
24M_XTALIN24M_XTALOUT
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_RESETn
FX2_SDA MAX_SDA
FX2_FLAGCFX2_FLAGB
FX2_WAKEUP
FX2_SLWRnFX2_SLRDn
FX2_FLAGA
FX2_SCLFX2_SDA
FX2_RESETn
FX2_WAKEUPVBUS_5V
MAX_SDA
FX2_FLAGBFX2_PA1FX2_PA4FX2_PA2FX2_PA3FX2_PA6FX2_PA5FX2_PB5FX2_PB3FX2_PB2FX2_PD5FX2_PD4FX2_PD7FX2_PD6FX2_PA0FX2_PB6FX2_PA7FX2_PB0
FX2_PB4FX2_SLWRnFX2_SLRDnFX2_PB1FX2_PB7FX2_FLAGCFX2_FLAGAFX2_SCL
FX2_RESETn
USB_T_CLK
USB_MAX_TDO
USB_MAX_TCKUSB_MAX_TMS
FX2_PD0FX2_PD2FX2_PD3
FX2_PD1
USB_MAX_TDI
HEADER_TDOHEADER_TMS
HEADER_TDI
HEADER_TCK EXT_JTAG_TCKUSB_MAX_TCK
HEADER_TDO EXT_JTAG_TDOUSB_MAX_TDO
HEADER_TMS EXT_JTAG_TMSUSB_MAX_TMS
EXT_JTAG_TDIUSB_MAX_TDI
HEADER_TCK
HEADER_TDI
USB_DISABLEn
USB_DISABLEn
USB_T_CLK
3p3V_USBPHY
3p3V_USBPHY3p3V_USBPHY
3p3V_USBPHY
3p3V_USBPHY
3p3V_STBY
3p3V_STBY
3p3V_STBY 3p3V_STBY3p3V_STBY
EXT_JTAG_TCK 45
EXT_JTAG_TMS 45
EXT_JTAG_TDI 45
EXT_JTAG_TDO 45
CLK_UBII_M1040
EM_PMBUS_ALERTn48,52,60LT_PMBUS_ALERTn48,53
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
44 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
44 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
44 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R254 DNI 04025%
R246 DNI 04025%
R240 10.0K
C369
0.1uF
R257 1K
U26
CY7C68013A_QFN
RDY01
RDY12
XTALIN5
AVCC3
DMINUS9
AGND6
VCC11
GND12
PD752
CLKOUT54
XTALOUT4
AVCC7
DPLUS8
AGND10
IFCLK13
RESERVED14
PD550PD449
PD651
SCL15
SDA16
PB018
GND26
GND28
GND41
PB119
PB321PB220
VCC17
VCC27
PB624PB523PB422
PD348PD247
PA740
PA437
PA134
PB725
PD146
WAKEUP44
PA639
GND53
VCC43
PA336
CTL130CTL029
PD045
RESET42
PA538
GND56
VCC55
PA235
PA033
CTL231
VCC32
EXPOSED_PAD57
R228 0
R841 1K
J9
70247-1051
246810
13579
C368
0.1uF
C363 0.1uF
R235
10.0K
C374
0.1uF
R253 0 04025%
C366
12pF
C3644.7nF
R230100K
R249 DNI 04025%
R245 DNI
C375
0.1uF
R232 2.00K
R229 DNI
R237 0
C371
0.1uF
R248 0 04025%
MAX10 10M04SCU169
U24D
IO_3_L5/DIFFIO_TX_RX_B1NL5
IO_3_M4/DIFFIO_RX_B2NM4
IO_3_L4/DIFFIO_TX_RX_B1PL4
IO_3_M5/DIFFIO_RX_B2PM5
IO_3_K5/DIFFIO_TX_RX_B3NK5
IO_3_N4/DIFFIO_RX_B4NN4
IO_3_J5/DIFFIO_TX_RX_B3PJ5
IO_3_N5/DIFFIO_RX_B4PN5
IO_3_N6/DIFFIO_TX_RX_B5NN6
IO_3_N7/DIFFIO_RX_B6NN7
IO_3_M7/DIFFIO_TX_RX_B5PM7
IO_3_N8/DIFFIO_RX_B6PN8
IO_3_J6/DIFFIO_TX_RX_B7NJ6
IO_3_M8/DIFFIO_RX_B8NM8
IO_3_K6/DIFFIO_TX_RX_B7PK6
IO_3_M9/DIFFIO_RX_B8PM9
IO_3_J7/DIFFIO_TX_RX_B9NJ7
IO_3_K7/DIFFIO_TX_RX_B9PK7
IO_3_N12N12
IO_3_M13/DIFFIO_TX_RX_B10NM13
IO_3_N10/DIFFIO_RX_B11NN10
IO_3_M12/DIFFIO_TX_RX_B10PM12
IO_3_N9/DIFFIO_RX_B11PN9
IO_3_M11/DIFFIO_TX_RX_B12NM11
IO_3_L11/DIFFIO_TX_RX_B12PL11
IO_3_J8/DIFFIO_TX_RX_B14NJ8
IO_3_K8/DIFFIO_TX_RX_B14PK8
IO_3_M10/DIFFIO_TX_RX_B16NM10
IO_3_L10/DIFFIO_TX_RX_B16PL10
C1558
22uF0603
U23
MAX811
GND1
RESET2
VCC4
MR3
VBUSD-
D+
ID
J15MICRO_USB_CONN
12345
6789
R241 10.0K
C370
0.1uF
U25
TPD2EUSB30
D-2D+1
GND3
MAX10 10M04SCU169
U24I
IO_1B_E5/JTAGEN/DIFFIO_RX_L9PE5
IO_1B_G1/TMS/DIFFIO_RX_L11NG1
IO_1B_G2/TCK/DIFFIO_RX_L11PG2
IO_1B_F5/TDI/DIFFIO_RX_L12NF5
IO_1B_F6/TDO/DIFFIO_RX_L12PF6
IO_8_B9/DEV_CLRN/DIFFIO_RX_T16NB9
IO_8_D8/DEV_OE/DIFFIO_RX_T18PD8
IO_8_D7/BOOT_SELD7
IO_8_D6/CRC_ERROR/DIFFIO_RX_T22ND6
IO_8_C4/NSTATUS/DIFFIO_RX_T24PC4
IO_8_C5/CONF_DONE/DIFFIO_RX_T24NC5
INPUT_ONLY_8_E7/NCONFIGE7
R838 22
R250
20.0K
R238 0
MAX10 10M04SCU169
U24H
IO_2_G5/CLK0N/DIFFIO_RX_L18NG5
IO_2_H6/CLK0P/DIFFIO_RX_L18PH6
IO_2_H5/CLK1N/DIFFIO_RX_L20NH5
IO_2_H4/CLK1P/DIFFIO_RX_L20PH4
IO_2_N2/DPCLK0/DIFFIO_RX_L22NN2
IO_2_N3/DPCLK1/DIFFIO_RX_L22PN3
IO_6_G9/CLK2P/DIFFIO_RX_R14PG9
IO_6_G10/CLK2N/DIFFIO_RX_R14NG10
IO_6_F13/CLK3P/DIFFIO_RX_R16PF13
IO_6_E13/CLK3N/DIFFIO_RX_R16NE13
IO_6_F9/DPCLK3/DIFFIO_RX_R26PF9
IO_6_F10/DPCLK2/DIFFIO_RX_R26NF10
IO_1B_H1/VREFB1N0H1
IO_2_L1/VREFB2N0L1
IO_3_N11/VREFB3N0N11
IO_5_K13/VREFB5N0K13
IO_6_D13/VREFB6N0D13
IO_8_B7/VREFB8N0B7
R231
0
C373
0.1uF
R252 DNI 04025%
R242 10.0K
R247 10.0K
Y4
24.00MHz
1 3
24
R234 DNI
R239 0
S12
PB Switch1 2
C365
12pF
C372
0.1uF
R251 0 04025%
R236 0
R255 1K
R233 2.00K
R243 10.0K
R244 0 04025%
R256 1K
C367
0.1uF
R840 1K
FB23
600 Ohm, 0.5A, 0.35DCR
0603
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UBII-MAX10 2
PLACE CLOSE MAX II PWR PIN
JTAG Master Selection: USB_DISABLEn = 0: External JTAGUSB_DISABLEn = 1: On-Board UBII/PCIe EP Edge JTAG_INPUT_SOURCE = 0: PCIe EP edge JTAG_INPUT_SOURCE = 1: On-Board UBII
JTAG Chain:SW2_2/3/4 = Low : BypassSW2_2/3/4 = High: Enable
Bank 6: 1.8V IO
Bank 5: 1.8V IOBank 8: 3.3V IO
Bank 1A/1B: 3.3V IO
Bank 2: 3.3V IO
Place R808~R810 near to U27
PCIE_EP_JTAG_TCK
S10_JTAG_TDI
S10_JTAG_TDO
PCIE_RT_JTAG_TCK
PWR_MAX10_BYPASSnPCIE_RT_BYPASSnS10_BYPASSn
JTAG_INPUT_SOURCE
PCIE_RT_JTAG_TDIPCIE_RT_JTAG_TMSPCIE_RT_JTAG_TDO
S10_JTAG_TCK
S10_JTAG_TMS
PCIE_RT_JTAG_TRSTn
EXT_JTAG_TCK
EXT_JTAG_TMS
EXT_JTAG_TDO
EXT_JTAG_TDI
PCIE_EP_JTAG_TCK
PCIE_EP_JTAG_TMS
PCIE_EP_JTAG_TDI
PCIE_EP_JTAG_TDO
PWR_GOOD
JTAG_INPUT_SOURCE
PWR_MAX10_BYPASSn
PCIE_RT_BYPASSn
S10_BYPASSn
PWR_MAX10_JTAG_TCK
PWR_MAX10_JTAG_TDIPWR_MAX10_JTAG_TDO
PWR_MAX10_JTAG_TMS
PWR_GOOD
PWR_MAX10_JTAG_TCKPWR_MAX10_JTAG_TDIPWR_MAX10_JTAG_TMS
3p3V_STBY
UBII_M10_VCCA
1p8V_UBII
3p3V_STBY
1p8V_UBII3p3V_STBY
3p3V_STBY UBII_M10_VCCA
3p3V_STBY
3p3V_STBY
3p3V_STBY
1p8V_PRE
1p8V
S10_JTAG_TDI30
S10_JTAG_TDO30
PCIE_RT_JTAG_TCK28ZQSFP0_1V8_MODPRS_L32
ZQSFP0_1V8_INT_L32
ZQSFP0_1V8_RESET_L32
ZQSFP0_1V8_LPMODE32PCIE_RT_JTAG_TDI28PCIE_RT_JTAG_TMS28PCIE_RT_JTAG_TDO28
ZQSFP0_3V3_MODPRS_L25ZQSFP0_3V3_RESET_L25
ZQSFP0_3V3_LPMODE25ZQSFP0_3V3_INT_L25
ZQSFP1_3V3_MODPRS_L26ZQSFP1_3V3_RESET_L26
ZQSFP1_3V3_LPMODE26ZQSFP1_3V3_INT_L26
S10_JTAG_TCK30
S10_JTAG_TMS30
ZQSFP1_1V8_MODPRS_L32
ZQSFP1_1V8_INT_L32
ZQSFP1_1V8_RESET_L32
ZQSFP1_1V8_LPMODE32
ZQSFP0_1V8_MODSEL_L32ZQSFP1_1V8_MODSEL_L32 ZQSFP1_3V3_MODSEL_L26
ZQSFP0_3V3_MODSEL_L25
PCIE_RT_JTAG_TRSTn28
PCIE_RT_S10_WAKEN32
PCIE_RT_PERSTn28
PCIE_RT_S10_PERSTn32
PCIE_RT_PRSNT2n28,48
PCIE_RT_S10_PRSNT2n32
EXT_JTAG_TCK44
EXT_JTAG_TMS44
EXT_JTAG_TDO44
EXT_JTAG_TDI44
PCIE_EP_JTAG_TCK27
PCIE_EP_JTAG_TMS27
PCIE_EP_JTAG_TDI27
PCIE_EP_JTAG_TDO27
PCIE_EP_3V3_I2C_SCL27PCIE_EP_3V3_I2C_SDA27
MAIN_I2C_SCL32,40,41,42MAIN_I2C_SDA32,40,41,42
S10_PMBUS_EN42MAIN_PMBUS_EN423V3_I2C_EN42
S10_CVP_CONFDONE30,43S10_CONF_DONE30,43S10_INIT_DONE30
SI5341_ENn40,42SI5341_RSTn40SI5341_FINC40SI5341_FDEC40S10_NCONFIG30
PWR_MAX10_JTAG_TCK49
PWR_MAX10_JTAG_TDI49PWR_MAX10_JTAG_TDO49
PCIE_RT_WAKEN28
PWR_MAX10_JTAG_TMS49
PWR_GOOD48
CPU_RESETn32,43
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
45 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
45 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
45 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
MAX10 10M04SCU169
U24J
GND__A1A1
GND__A13A13
GND__B8B8
GND__C3C3
GND__D2D2
GND__D5D5
GND__E11E11
GND__E2E2
GND__F3F3
GND__G7G7
GND__H12H12
GND__J4J4
GND__L9L9
GND__M6M6
GND__N1N1
GND__N13N13
R264
1K
R259
1K
R262 1K
C402
0.1uF
C389
10uF
R263DNI
OPEN
SW2
TDA04H0SB1
1234 5
678
C377
10uF
C387
0.1uF
C398
0.1uF
C391
0.1uF
C393
0.1uF
C395
0.1uF
FB18 600 Ohm, 0.5A, 0.35DCR0603
C384
0.1uF
C378
0.1uF
C382
0.1uF
C380
0.1uF
MAX10 10M04SCU169
U24G
IO_8_C10/DIFFIO_RX_T14PC10
IO_8_A8/DIFFIO_RX_T15PA8
IO_8_C9/DIFFIO_RX_T14NC9
IO_8_A9/DIFFIO_RX_T15NA9
IO_8_B10/DIFFIO_RX_T16PB10
IO_8_A10/DIFFIO_RX_T17PA10
IO_8_A11/DIFFIO_RX_T17NA11
IO_8_E8/DIFFIO_RX_T18NE8
IO_8_A7/DIFFIO_RX_T19PA7
IO_8_A6/DIFFIO_RX_T19NA6
IO_8_B6/DIFFIO_RX_T20PB6
IO_8_A4/DIFFIO_RX_T21PA4
IO_8_B5/DIFFIO_RX_T20NB5
IO_8_A3/DIFFIO_RX_T21NA3
IO_8_E6/DIFFIO_RX_T22PE6
IO_8_B3/DIFFIO_RX_T23PB3
IO_8_B4/DIFFIO_RX_T23NB4
IO_8_A5/DIFFIO_RX_T25PA5
IO_8_A2/DIFFIO_RX_T26PA2
IO_8_B2/DIFFIO_RX_T26NB2
R258
1K
C399
0.1uFFB13
600 Ohm, 0.5A, 0.35DCR
0603
FB19 DNI0603
MAX10 10M04SCU169
U24A
VCCIO1A__F2F2
VCCIO1B__G3G3
VCCIO2__K3K3
VCCIO2__J3J3
VCCIO3__L8L8
VCCIO3__L7L7
VCCIO3__L6L6
VCCIO5__J11J11
VCCIO5__H11H11
VCCIO6__G11G11
VCCIO6__F11F11
VCCIO8__C8C8
VCCIO8__C7C7
VCCIO8__C6C6
VCCA3__D3D3
VCCA1__K4K4
VCCA2__D10D10
VCCA3__D4D4
VCCA4__K9K9
VCC_ONE__H7H7
VCC_ONE__G8G8
VCC_ONE__G6G6
VCC_ONE__F7F7
R809 1K
MAX10 10M04SCU169
U24F
IO_6_F12/DIFFIO_RX_R18PF12
IO_6_E12/DIFFIO_RX_R18NE12
IO_6_C13C13
IO_6_F8/DIFFIO_RX_R27PF8
IO_6_B12/DIFFIO_RX_R28PB12
IO_6_E9/DIFFIO_RX_R27NE9
IO_6_B11/DIFFIO_RX_R28NB11
IO_6_C12/DIFFIO_RX_R29PC12
IO_6_B13/DIFFIO_RX_R30PB13
IO_6_C11/DIFFIO_RX_R29NC11
IO_6_A12/DIFFIO_RX_R30NA12
IO_6_E10/DIFFIO_RX_R31PE10
IO_6_D9/DIFFIO_RX_R31ND9
IO_6_D12/DIFFIO_RX_R33PD12
IO_6_D11/DIFFIO_RX_R33ND11
MAX10 10M04SCU169
U24B
IO_1A_D1/DIFFIO_RX_L1ND1
IO_1A_C2/DIFFIO_RX_L1PC2
IO_1A_E3/DIFFIO_RX_L3NE3
IO_1A_E4/DIFFIO_RX_L3PE4
IO_1A_C1/DIFFIO_RX_L5NC1
IO_1A_B1/DIFFIO_RX_L5PB1
IO_1A_F1/DIFFIO_RX_L7NF1
IO_1A_E1/DIFFIO_RX_L7PE1
IO_1B_F4/DIFFIO_RX_L14NF4
IO_1B_G4/DIFFIO_RX_L14PG4
IO_1B_H2/DIFFIO_RX_L16NH2
IO_1B_H3/DIFFIO_RX_L16PH3
C386
0.1uF
C388
0.1uF
C400
0.1uF
R808 1K
C390
0.1uF
C392
0.1uF
C394
0.1uF
C396
0.1uF
C385
0.1uF
R810 1K
R261
1K
MAX10 10M04SCU169
U24E
IO_5_K10/DIFFIO_RX_R1PK10
IO_5_K11/DIFFIO_RX_R2PK11
IO_5_J10/DIFFIO_RX_R1NJ10
IO_5_L12/DIFFIO_RX_R2NL12
IO_5_K12/DIFFIO_RX_R7PK12
IO_5_L13L13
IO_5_J12/DIFFIO_RX_R7NJ12
IO_5_J9/DIFFIO_RX_R8PJ9
IO_5_J13/DIFFIO_RX_R9PJ13
IO_5_H10/DIFFIO_RX_R8NH10
IO_5_H13/DIFFIO_RX_R9NH13
IO_5_H9/DIFFIO_RX_R10PH9
IO_5_G13/DIFFIO_RX_R11PG13
IO_5_H8/DIFFIO_RX_R10NH8
IO_5_G12/DIFFIO_RX_R11NG12
C383
0.1uF
C379
0.1uF
C381
0.1uF
R260
1K
C401
10uF
C397
0.1uF
C376DNI
MAX10 10M04SCU169
U24C
IO_2_M3/PLL_L_CLKOUTN/DIFFIO_RX_L27NM3
IO_2_L3/PLL_L_CLKOUTP/DIFFIO_RX_L27PL3
IO_2_J1/DIFFIO_RX_L19NJ1
IO_2_J2/DIFFIO_RX_L19PJ2
IO_2_M1/DIFFIO_RX_L21NM1
IO_2_M2/DIFFIO_RX_L21PM2
IO_2_L2L2
IO_2_K1/DIFFIO_RX_L28NK1
IO_2_K2/DIFFIO_RX_L28PK2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
46 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
46 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
46 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
U41,U42 : EY1501
0.7A
System Power Connection Chart
U44,U45 : LTC3884EUK/LTC3874EUFD
PCIE_EP_12V
U47 : EN63A0I
U48 : EN63A0I
5.5AS10_VCCT (U49)
3p3V (U43)
1p8V (U50)
1.36A S10_VCCRR (U48)
U43 : EM2130H
U49 : EN63A0I
U50 : EN63A0I
U46 : EN63A0I
U58 : EN6337QI
U62 : EN6360QI
U61 : EN63A0QI
U58 : TPS51200
U53 : EN63A0QI
U54,U55 : TPS51200DRCR
1.37A S10_VCCERAM (U46)
S10MX_VCC/VCCP (U44,U45)
12V_G1(12.5A)
U31
12V_G2(6.25A) U36
12V_AUX
Q11
9.35A
5V(U40)3p3V_STBY (U41)
1p8V_PRE_STBY (U42)
S10_VCCRL (U47) [email protected]
S10_VCCH/VCCIO/VCCPT/VCCBAT [email protected]
S10_VCCA_PLL/VCCPLL_SDM
0.5A FAN (J11)0.5A@12V
2p5V DDR4 (U58)
DDR4_VCCP/DDR4_VCCSPD [email protected]
VCCIO_1.2V_ DDR4 (U53)
0p6V_DDR4_DIMM_VTT (U54)
0p6V_DDR4_COMP_VTT (U55)
1p2V_DDR4_DIMM
1p2V_DDR4_COMP
[email protected]( for 18W module)
5.5A
3A
HILO_VDD (U57) U57,U56 : EN6362QI
HILO_VDDQ (U56)
2.2A
0.7A U51 : EM2120L01QI
VCCM (U60)
U60 : EN6362QI
1.2A
2A
VCCIO_UIB (U51)
4.8A
1.1A
12V_DDRT_DIMM1.5A@12V (for 18W module)
1.5A
5.6A
12.45A
0.2A
12V_PCIe_Root (J7)
3p3V_ZQSFP0
3p3V_ZQSFP1
U8
U9
1.9A
1.9A
2.1A@12V (25W)2.1A
150W
75W
Q11 : PSMN1R0-30YLD
U8,U9 : TPS2557DRBR
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
47 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
47 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
47 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAX 10 PWR Manager 1
I2C Address = b'0010100'
RefVoltage = 0.3V
S10MX_VCC
I2C_3V3_SDAI2C_3V3_SCL
S10_VCCERAM
S10_VCCRL_GXB
S10_VCCRR_GXB
S10_VCCT_GXB
1p2V_VCCIO_UIB
1p8V
1p2V_DDR4
VCCM
MAX10_AGND
3p3V
3p3V
MAX10_AGNDS10MX_VCC
S10_VCCERAM
S10_VCCRL_GXB
S10_VCCRR_GXB
S10_VCCT_GXB
1p2V_VCCIO_UIB
3p3V_STBY
MAX10_AGND
1p8V
1p2V_DDR4
VCCM
I2C_3V3_SCL 28,42,48,49,52I2C_3V3_SDA 28,42,48,49,52
S10_VCC_PG 53,54S10_VCCERAM_PG 55S10_VCCRL_PG 56S10_VCCRR_PG 57S10_VCCT_PG 581p2V_VCCIO_UIB_PG 60
1p8V_PG 59VCCM_PG 61HILO_VDD_PG 65HILO_VDDQ_PG 641p2V_DDR4_PG 62
S10_VCCFAULT 53,54
S10_VCC_EN 53,54
S10_VCCRL_EN 56S10_VCCERAM_EN 55
S10_VCCRR_EN 57S10_VCCT_EN 581p8V_EN 59VCCIO_UIB_EN 60VCCM_EN 611p2V_DDR4_EN 62HILO_VDDQ_EN 64HILO_VDD_EN 652p5V_EN 66ZQSFP0_PWR_EN 25ZQSFP1_PWR_EN 26
ZQSFP0_FAULT_N 25ZQSFP1_FAULT_N 26
DIMM_VTT_EN 63COMP_VTT_EN 63
PCIE_RT_PRSNT2n 28,45
PWR_GOOD 45
3p3V_EN 52
12V_G1_PG 5012V_G2_PG 50
S10_VCCERAM_SENSE_P 55S10_VCCERAM_SENSE_N 55S10_VCCRL_SENSE_P 56S10_VCCRL_SENSE_N 56S10_VCCRR_SENSE_P 57S10_VCCRR_SENSE_N 57S10_VCCT_SENSE_P 58S10_VCCT_SENSE_N 58
I2C_3V3_SCL28,42,48,49,52I2C_3V3_SDA28,42,48,49,52 EM_PMBUS_ALERTn 44,52,60
LT_PMBUS_ALERTn 44,53
12V_G1_UV_PG 5012V_G1_OV_PG 50
POWER_ON 50
5V_PG 51
PWR_LED_DR 43
DIMM_VTT_PG 63
2p5V_PG 66
3p3V_PG 52
COMP_VTT_PG 63
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
48 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
48 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
48 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R266 49.9
R290 10
C406 1pF
R271 49.9
R628 10
C411 1pF
MAX10 10M16SA U169
U27G
IO_8_A8/DIFFIO_RX_T27PA8
IO_8_A9/DIFFIO_RX_T27NA9
IO_8_B10/DIFFIO_RX_T28PB10
IO_8_A10/DIFFIO_RX_T29PA10
IO_8_A11/DIFFIO_RX_T29NA11
IO_8_E8/DIFFIO_RX_T30NE8
IO_8_A7/DIFFIO_RX_T31PA7
IO_8_A6/DIFFIO_RX_T31NA6
IO_8_B6/DIFFIO_RX_T32PB6
IO_8_A4/DIFFIO_RX_T33PA4
IO_8_B5/DIFFIO_RX_T32NB5
IO_8_A3/DIFFIO_RX_T33NA3
IO_8_E6/DIFFIO_RX_T34PE6
IO_8_B3/DIFFIO_RX_T35PB3
IO_8_B4/DIFFIO_RX_T35NB4
IO_8_A5A5
IO_8_A2/DIFFIO_RX_T38PA2
IO_8_B2/DIFFIO_RX_T38NB2
R291
1K
R289 10
R275 49.9
R283 49.9
R627 0 04025%
R276 10
C410 1pF
R629 0
R269 49.9
R287 49.9
MAX10 10M16SA U169
U27F
IO_6_F12/DIFFIO_RX_R22PF12
IO_6_E12/DIFFIO_RX_R22NE12
IO_6_C13C13
IO_6_F8/DIFFIO_RX_R31PF8
IO_6_B12/DIFFIO_RX_R32PB12
IO_6_E9/DIFFIO_RX_R31NE9
IO_6_B11/DIFFIO_RX_R32NB11
IO_6_C12/DIFFIO_RX_R33PC12
IO_6_B13/DIFFIO_RX_R34PB13
IO_6_C11/DIFFIO_RX_R33NC11
IO_6_A12/DIFFIO_RX_R34NA12
IO_6_E10/DIFFIO_RX_R35PE10
IO_6_D9/DIFFIO_RX_R35ND9
IO_6_D12/DIFFIO_RX_R37PD12
IO_6_D11/DIFFIO_RX_R37ND11
R288 10
R272 49.9
C405 1pF
C1361 0.1uF
R273 10
R281 49.9
R284 49.9
MAX10 10M16SA U169
U27J
REFGND__E2E2
ADC_VREF__D3D3
ANAIN1__D2D2
R292
100
0402
C404 1pF
C409 1pF
R267 49.9
C413
0.1uF
R285 10
MAX10 10M16SA U169
U27B
IO_1A_D1/ADC1IN1/DIFFIO_RX_L1ND1
IO_1A_C2/ADC1IN2/DIFFIO_RX_L1PC2
IO_1A_E3/ADC1IN3/DIFFIO_RX_L3NE3
IO_1A_E4/ADC1IN4/DIFFIO_RX_L3PE4
IO_1A_C1/ADC1IN5/DIFFIO_RX_L5NC1
IO_1A_B1/ADC1IN6/DIFFIO_RX_L5PB1
IO_1A_F1/ADC1IN7/DIFFIO_RX_L7NF1
IO_1A_E1/ADC1IN8/DIFFIO_RX_L7PE1
IO_1B_F4/DIFFIO_RX_L14NF4
IO_1B_G4/DIFFIO_RX_L14PG4
IO_1B_H2/DIFFIO_RX_L16NH2
IO_1B_H3/DIFFIO_RX_L16PH3
R277 49.9
R286 49.9
R270 49.9
R265 10
MAX10 10M16SA U169
U27D
IO_3_L5/DIFFIO_TX_RX_B1NL5
IO_3_M4/DIFFIO_RX_B2NM4
IO_3_L4/DIFFIO_TX_RX_B1PL4
IO_3_M5/DIFFIO_RX_B2PM5
IO_3_K5/DIFFIO_TX_RX_B3NK5
IO_3_N4/DIFFIO_RX_B4NN4
IO_3_J5/DIFFIO_TX_RX_B3PJ5
IO_3_N5/DIFFIO_RX_B4PN5
IO_3_N6/DIFFIO_TX_RX_B5NN6
IO_3_N7/DIFFIO_RX_B6NN7
IO_3_M7/DIFFIO_TX_RX_B5PM7
IO_3_N8/DIFFIO_RX_B6PN8
IO_3_J6/DIFFIO_TX_RX_B13NJ6
IO_3_M8/DIFFIO_RX_B14NM8
IO_3_K6/DIFFIO_TX_RX_B13PK6
IO_3_M9/DIFFIO_RX_B14PM9
IO_3_J7/DIFFIO_TX_RX_B15NJ7
IO_3_K7/DIFFIO_TX_RX_B15PK7
IO_3_N12N12
IO_3_M13/DIFFIO_TX_RX_B16NM13
IO_3_N10/DIFFIO_RX_B17NN10
IO_3_M12/DIFFIO_TX_RX_B16PM12
IO_3_N9/DIFFIO_RX_B17PN9
IO_3_M10/DIFFIO_TX_RX_B22NM10
IO_3_L10/DIFFIO_TX_RX_B22PL10
C408 1pF
C414
10uF
C403 1pFR268 49.9
R282 49.9R280 10
R274 49.9
C412
220pF
U28
LTC2497
CN08
CN19
CN210
CN311
CH412
CH513
CH614
CH715
CH816
CH917
CH1018
CH1119
CH1220
CH1321
CH1422
CH1523
GND131
GND232
GND333
GND434
GND539
GND61
GND74
GND86
COM7
NC5
SCL2 SDA3
MUXOUTP24 MUXOUTN27
ADCINN26
ADCINP25
VCC28
REFN30
REFP29
CA036 CA137 CA238
f035
C407 1pF
R279 10R278 49.9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAX10 PWR Manager 2
I2C ADDR = 4C
Board Temp Sensor
H = 1.73mmPlace on Bottom side
FAN_CTRL
OVERTEMPnTSENSE_ALERTn
OVERTEMPnTSENSE_ALERTnFAN_CTRL
3p3V_STBY
3p3V_STBYPWR_M10_VCCA
3p3V_STBY
3p3V_STBY PWR_M10_VCCIO1A
12V_G1
3p3V_STBY
PWR_M10_VCCA
3p3V_STBY
3p3V_STBY
3p3V_STBY
PWR_M10_VCCIO1A
3p3V_STBY
3p3V_STBY
S10_TEMP0p30
I2C_3V3_SCL 28,42,48,52S10_TEMP0n30 I2C_3V3_SDA 28,42,48,52
PWR_MAX10_JTAG_TMS45PWR_MAX10_JTAG_TCK45PWR_MAX10_JTAG_TDI45PWR_MAX10_JTAG_TDO45
CLK_PWR_M10 40
1p2V_DDR4_DIS 67VCCIO_UIB_DIS 67HILO_VDD_DIS 67HILO_VDDQ_DIS 67
VCCM_DIS 671p8V_DIS 67VCCRL_GXB_DIS 67VCCRR_GXB_DIS 67VCCT_DIS 67VCCERAM_DIS 672p5V_DIS 673p3V_DIS 67
PCIE_EP_PERSTN 27
OVERTEMPn 43
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
49 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
49 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
49 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
FB14
220ohm, 2.0A1 2
C430
0.1uF
J10
FAN_Conn
PWM1TACH212V3GND4
R295 0
MAX10 10M16SA U169
U27K
GND__A1A1
GND__A13A13
GND__B8B8
GND__C3C3
GND__D5D5
GND__E11E11
GND__F3F3
GND__G7G7
GND__H12H12
GND__J4J4
GND__L9L9
GND__M6M6
GND__N1N1
GND__N13N13
L6
BLM15AG221SN1300mA
U29
MAX1619
ADD16
ADD010
SMBCLK14
SMBDATA12DXP
3
DXN4
VCC1
OVERTn9
ALERTn11
STBYn15 GND1
2
GND27
GND38
NC15
NC213
NC316
C418
0.1uF
C426
10uF
C419
0.1uF
R296 0
C417
10uF
MAX10 10M16SA U169
U27H
IO_2_G5/CLK0N/DIFFIO_RX_L20NG5
IO_2_H6/CLK0P/DIFFIO_RX_L20PH6
IO_2_H5/CLK1N/DIFFIO_RX_L22NH5
IO_2_H4/CLK1P/DIFFIO_RX_L22PH4
IO_2_N2/DPCLK0/DIFFIO_RX_L24NN2
IO_2_N3/DPCLK1/DIFFIO_RX_L24PN3
IO_3_M11/CLK6N/DIFFIO_TX_RX_B18NM11
IO_3_L11/CLK6P/DIFFIO_TX_RX_B18PL11
IO_3_J8/CLK7N/DIFFIO_TX_RX_B20NJ8
IO_3_K8/CLK7P/DIFFIO_TX_RX_B20PK8
IO_6_G9/CLK2P/DIFFIO_RX_R18PG9
IO_6_G10/CLK2N/DIFFIO_RX_R18NG10
IO_6_F13/CLK3P/DIFFIO_RX_R20PF13
IO_6_E13/CLK3N/DIFFIO_RX_R20NE13
IO_6_F9/DPCLK3/DIFFIO_RX_R30PF9
IO_6_F10/DPCLK2/DIFFIO_RX_R30NF10
IO_8_C10/CLK5P/DIFFIO_RX_T26PC10
IO_8_C9/CLK5N/DIFFIO_RX_T26NC9
IO_1B_H1/VREFB1N0H1
IO_2_L1/VREFB2N0L1
IO_3_N11/VREFB3N0N11
IO_5_K13/VREFB5N0K13
IO_6_D13/VREFB6N0D13
IO_8_B7/VREFB8N0B7
C4152200pF
C420
0.1uF
C4160.1uF
C431
0.1uF
C421
0.1uF
R817 10.0K
C432
0.1uF
R297 0
C422
0.1uF
C425
10uF
C433
0.1uF
C423
0.1uF
R3
01
10
.0K
C434
0.1uF
R293 10.0K
MAX10 10M16SA U169
U27A
VCCIO1A__F2F2
VCCIO1B__G3G3
VCCIO2__K3K3
VCCIO2__J3J3
VCCIO3__L8L8
VCCIO3__L7L7
VCCIO3__L6L6
VCCIO5__J11J11
VCCIO5__H11H11
VCCIO6__G11G11
VCCIO6__F11F11
VCCIO8__C8C8
VCCIO8__C7C7
VCCIO8__C6C6
VCCA1__K4K4
VCCA2__D10D10
VCCA3__D4D4
VCCA4__K9K9
VCC_ONE__H7H7
VCC_ONE__G8G8
VCC_ONE__G6G6
VCC_ONE__F7F7
R3
02
10
.0K
C424
0.1uF
MAX10 10M16SA U169
U27C
IO_2_M3/PLL_L_CLKOUTN/DIFFIO_RX_L31NM3
IO_2_L3/PLL_L_CLKOUTP/DIFFIO_RX_L31PL3
IO_2_J1/DIFFIO_RX_L21NJ1
IO_2_J2/DIFFIO_RX_L21PJ2
IO_2_M1/DIFFIO_RX_L23NM1
IO_2_M2/DIFFIO_RX_L23PM2
IO_2_L2L2
IO_2_K1/DIFFIO_RX_L32NK1
IO_2_K2/DIFFIO_RX_L32PK2
C435
0.1uF
MAX10 10M16SA U169
U27E
IO_5_K10/RUP/DIFFIO_RX_R1PK10
IO_5_J10/RDN/DIFFIO_RX_R1NJ10
IO_5_K11/DIFFIO_RX_R2PK11
IO_5_L12/DIFFIO_RX_R2NL12
IO_5_K12/DIFFIO_RX_R11PK12
IO_5_L13L13
IO_5_J12/DIFFIO_RX_R11NJ12
IO_5_J9/DIFFIO_RX_R12PJ9
IO_5_J13/DIFFIO_RX_R13PJ13
IO_5_H10/DIFFIO_RX_R12NH10
IO_5_H13/DIFFIO_RX_R13NH13
IO_5_H9/DIFFIO_RX_R14PH9
IO_5_G13/DIFFIO_RX_R15PG13
IO_5_H8/DIFFIO_RX_R14NH8
IO_5_G12/DIFFIO_RX_R15NG12
R304 0
R298 10.0K
C436
0.1uF
R303 0
C427
0.1uF
R299 10.0K
C428
0.1uF
MAX10 10M16SA U169
U27I
IO_1B_E5/JTAGENE5
IO_1B_G1/TMS/DIFFIO_RX_L11NG1
IO_1B_G2/TCK/DIFFIO_RX_L11PG2
IO_1B_F5/TDI/DIFFIO_RX_L12NF5
IO_1B_F6/TDO/DIFFIO_RX_L12PF6
IO_8_B9/DEV_CLRN/DIFFIO_RX_T28NB9
IO_8_D8/DEV_OE/DIFFIO_RX_T30PD8
IO_8_D7/CONFIG_SELD7
INPUT_ONLY_8_E7/NCONFIGE7
IO_8_D6/CRC_ERROR/DIFFIO_RX_T34ND6
IO_8_C4/NSTATUS/DIFFIO_RX_T36PC4
IO_8_C5/CONF_DONE/DIFFIO_RX_T36NC5
R294 0
C429
0.1uF
R300 10.0K
R305 200
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
When 12V_PCIE = 12VEN_12V_G1G2_L = 1.47V
VGS(th) max = 0.85V
12V from PCIe Slot
When 16V, EN = 1.96VWhen 15V, EN = 1.84VWhen 14V, EN = 1.72VWhen 13V, EN = 1.59VWhen 12V, EN = 1.47VWhen 11V, EN = 1.35VWhen 10V, EN = 1.23V
Power - Select Power Input
Vshdn_th = 0.6V/1.2V/2V
Vgs(th) = 2.5V/3.7V/4.5V
Vshdn_absmax = 100V
PCIe Specs: 12.5A +5%/-8%
H = 1.0mmPlace on bottom side
H = 1.1mmPlace on bottom side
H = 1.1mmPlace on bottom side
H = 1.0mmPlace on bottom side
OFF
Bench Y N ON 12V_G1_UV/OV_PG=YCondition Aux PCIe PWR_SW Start_SEQ
ON
Power On Switch
12V_G1 > 10.46V : OUTA = "1";12V_G2 < 13.77V: OUTB = "1";PWR MAX10 get both "1" to start the power seq
Bench Y N OFF NSLOT Y Y X 12V_G1_UV/OV_PG=YSLOT N Y ON NSLOT N Y OFF 12V_G1_UV/OV_PG=N
12V Holding Caps
Chold = 1160uF for 12_G1
Chold = 900uF for 12_G2
POWER_ON
POWER_ON
POWER_ON
12V_AUX
12V_G1
PCIE_EP_12V
PCIE_EP_12V
12V_G2
3p3V_STBY
12V_GROUP1
3p3V_STBY
12V_GROUP1
12V_GROUP2
PCIE_EP_12V
12V_G1
12V_G2
3p3V_STBY
12V_G1
12V_G2
12V_G1_PG 48
12V_G2_PG 48
12V_G1_UV_PG 48
12V_G1_OV_PG 48POWER_ON48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
50 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
50 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
50 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C1510
22uF
SW3
SW_SLIDE_DPDT
1
236
5
4
U37
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
R3065.49M
U38
LTC4365-1
VIN4
VOUT6
GA
TE
5
UV3
GND1
OV2
FAULT7SHDN
8
GND9
TAB
Q11PSMN1R0-30YLD
4G
5D
1
1S
12
S2
3S
3
U59
TPS3700
OUTA1
OUTB6
VDD5
INA+3
INB-4
GND2
1
2
3
Q12SI2302CDS-T1-GE3
SOT23
R6226.04K
C1509
22uF
C1527
150uF7343P
C437
4.7nF
D185p0SMDJ12A
R315 2400402 1%
R6240
U30FDMC2514SDC
5
123
4
U36FDMC2514SDC
5
123
4
C1512
DNI7343P
D175p0SMDJ12A
R32520.0K
R311
100K
U33
LTC4365-1
VIN4
VOUT6
GA
TE
5
UV3
GND1
OV2
FAULT7SHDN
8
GND9
C1513
680pF
R3145.76K04021%
C1516
150uF7343P
R626
10.0K
R6230
R320
100K
R308
10.0K
R307DNI
C1514
1uF
C1550
0.1uF
C1522
150uF7343P
R3175.49M
U32
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
C1517
150uF7343P
R32260.4K
C4400.01uF040225VX7R
R3091004021%
R815
200K
U34LTC4359
OU
T8
VS
S6
NC13
GA
TE
1
IN4
NC27SHDN
5
SR
C2
R316 1K
U35FDMC2514SDC
5
123
4
C441
4.7nF
C1523
150uF7343P
U31FDMC2514SDC
5
123
4
R318
DNI
R323200K
C1511
DNI7343P
J11
PCIe 2x4 ATX
12V1
12V2
12V3
GND8
SENSE14
SENSE06 GND5
GND7
R310
100K
C1559
150uF7343P
C1524
150uF7343P
C1521
150uF7343P
R31241.2K04021%
R620200K
C1508
22uF
C1525
150uF7343P
R319
10.0K
R625
10.0K
R32160.4K
C1515
150uF7343P
C1507
22uF
C1506560uF
ALUM POLY20%16V
12mm15m OHM8mm_CAN
C438 4.7nF0402 X7R
50V
R6211.91K
C4391.5uF120650VX6S
R313200K
C1526
150uF7343P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
12V to 5V, 3p3V STBY, 1p8V_PRE
5.0V
Rup
Rdn
ENth = 0.616V /0.8V / 0.95V
VDOmax = 185mV
Vout = 0.5V x (Rup/Rdn + 1)
VINabsmax = -0.3V to 6.5V
ENth = 0.616V /0.8V / 0.95V
VINabsmax = -0.3V to 6.5V
VDOmax = 185mV
Rup
Vout = 0.5V x (Rup/Rdn + 1)
Rdn
3p3V_STBY_PG 1p8V_PRE_PG
12V_G2
12V_G2
5V
5V_LDO1
3p3V_STBY
5V_AGND
5V_AGND
5V_AGND
5V_AGND
5V_AGND
5V_AGND
5V_LDO2
1p8V_PRE
LT4625_INTVCC LT4625_INTVCC
5V5V
5V_PG 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
51 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
51 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
51 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C443
1uF
C464
22uF0603
C448
0.1uF
C444
0.1uF
R3378.25K
1%
R343
1K
C44522uF
C455DNI
C463
22uF0603
C44947uF
C44622uF
TP1
FB24
80ohm @ 100Mhz5A, 10mOhm
C45047uF
R3392.61K04021%
C456
22uF
TP4
C44722uF
U41
EY1501di-adj
VOUT11
VOUT22
VFB3
GND5
POK4
EN7
SS6
VIN19
VIN210
EPAD11
NC8
R334
100K
C45147uF
R330
100K
R328
DNI
FB25
80ohm @ 100Mhz5A, 10mOhm
C462
22uF0603
C45247uF
C46610nF040250VX7R
TP2
R34010.0K0402
1%
R3350
R333
DNI
R327
10
C461
22uF0603
C45947pF040250VC0G/NPO
U40
LTM4625
FREQA4
PHMODEB2
MODEC4
FB
B1
TRACK/SSA2
COMPA1
RUNA3
PG
OO
DC
2
VOUT1C1
PG
ND
1B
3
VIN1D5
SV
INC
5
INT
VC
CE
4
SGNDB4
CL
KO
UT
B5
CL
KIN
A5
VIN2E5
VOUT2D1
VOUT3D2
VOUT4E1
VOUT5E2
PG
ND
2C
3
PG
ND
3D
3
PG
ND
4D
4
PG
ND
6E
3C457
22uF
U42
EY1501di-adj
VOUT11
VOUT22
VFB3
GND5
POK4
EN7
SS6
VIN19
VIN210
EPAD11
NC8
C453100pf
R336
49.9K
TP3
C465
22uF0603
C460
22uF0603
C45847pF040250VC0G/NPO
R816200K
C46710nF040250VX7R
R329
100K
R326
100K
R331DNI
R34271504021%
R3384.02K04021%
C454
0.1uF
R34110.0K0402
1%
R332DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
26A
PMBus Address = 0X4E
Place sense linesat the load
MAIN 12V to 3.3V
3.3V output
H = 6.6mmPlace on Top side
AGND PGND
Enpirion Dongle
(Top Side 30mil pad,No Via)
3.3V
EM_SCLEM_SDA
3p3V
3p3V_AGND
5V12V_G2
3p3V_AGND
3p3V_AGND
3p3V_AGND
3p3V_AGND
3p3V_AGND
3p3V_AGND
3p3V_AGND3p3V_AGND
3p3V_AGND
VDD33_OUT1
VDD33_OUT1
VDD33_OUT1
I2C_3V3_SCL 28,42,48,49I2C_3V3_SDA 28,42,48,49
3p3V_PG48
3p3V_EN48
EM_SCL60
EM_SDA60
EM_PMBUS_ALERTn44,48,60
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
52 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
52 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
52 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R35510.0K
R3621K04020.1%
C486
22uF
C471
47UF
R35610.0K
C472
47UF
J12
TSW-103-08-G-S
11
22
33
C469
220uF6.3V
C473
47UF
C468
220uF6.3V
R34810.0K
R3602K0402
C474
47UF
ST1
SHORT
11
22
R359 0
C475
47UF
C48710uF
1206
R36111K04020.1%
R354DNI
0402
C476
DNI
R364 0
R35110.0K
R34410.0K
C4771uF0
603
R357DNI 0402
C480
22uF
R352
3.3k
0402
U43EM2130H
AGND70
NC6868
VSENP71VSENN72
VOUT79
VOUT3
VTRACK77
ADDR17
VOUT80
ADDR08
RTUNE5
VOUT2
VCCSEN78
RVSET4
SCL15 SDA14
PG
ND
32
VDD3316
VCC66
NC7676
DGND69
PWM9
VOUT81
VINSEN6
VOUT1
SMBALERT13 CONTROL12 PGOOD11 SYNC10
PG
ND
33
PG
ND
34
PG
ND
35
PG
ND
36
PG
ND
37
PG
ND
38
PG
ND
39
PG
ND
40
PG
ND
42
PG
ND
43
PG
ND
44
PG
ND
45
PG
ND
46
PG
ND
47
PG
ND
48
PG
ND
49
PG
ND
50
PG
ND
41
PGND22
PGND23
PGND24
PGND25
PGND26
PGND27
PGND28
PGND29
PGND30
PGND31
PGND60
PGND59
PGND58
PGND57
PGND56
PGND55
PGND54
PGND53
PGND52
PGND51
PVIN61PVIN62PVIN63PVIN64
PVCC65
NC6767
NC7575
NC7474
NC7373
PVIN17
PVIN18
PVIN20
PVIN21
VO
UT
10
0
VO
UT
99
VO
UT
98
VO
UT
97
VO
UT
96
VO
UT
95
VO
UT
94
VO
UT
93
VO
UT
92
VO
UT
91
VO
UT
90
VO
UT
89
VO
UT
88
VO
UT
87
VO
UT
86
VO
UT
85
VO
UT
84
VO
UT
83
VO
UT
82
PVIN_PAD103
PGND_PAD104
AGND_PAD102
VO
UT
_P
AD
10
1
PVIN19
C481
22uF
C4790.1uF25VX6S
R3470
R3492.74K
0402
C478DNI
040
2
R3450
C482
22uF
R630
4.7K
R35022K
0402
R3581K
0402
C483
22uF
FB15742792780
0402
R363 0
C484
22uF
TP8
TESTPOINT
1T
P
R346576
040
2
R3530
C470
47UF
C485
22uF
C488DNI
040
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
12V to VCC Core (Phase 0,1)
0.9V
744301025
Need 0.85V core voltage
0.9V
744301025
Check Phase define
500Hz
I2C Address: 0X5A,0X5B and 0X47
0.85V
0.85VSW0
TG0
LTC3884_SCL LTC3884_SCL BST0
LTC3884_SDA LTC3884_SDA
LT3884_ALERTn
SHARE_CLK
WP1
TG1
BST1
BG1
ASEL0SW1
ASEL1
VOUT0_CFG
VOUT1_CFG
FREQ_CFG
PHASE_CFG
LTC3884_SCLLTC3884_SDA
LT3884_ALERTn
VCC_SENSE 34
VSS_SENSE 34
12V_G1 VDD33
GND_SIGNAL_core VDD25 VIN1 12V_G1VIN1
GND_SIGNAL_coreINTVCC1
EXTVCC
VDD33
VIN1S10MX_VCC
INTVCC1
VIN1
GND_SIGNAL_coreGND_SIGNAL_core GND_SIGNAL_core
GND_SIGNAL_core
INTVCC1 VIN1
GND_SIGNAL_coreVDD25
VDD33
GND_SIGNAL_core
VDD33
GND_SIGNAL_core
S10MX_VCC
S10MX_VCC
VIN1
VSENSE+53
VSENSE+ 53 VSENSE-53
VSENSE- 53
VSENSE+ 53
VSENSE- 53
CORE_PMBUS_SCL 42CORE_PMBUS_SDA 42
S10_VCC_PG 48,54
S10_VCCFAULT 48,54
S10_VCC_EN48,54
LT3884_ITH54
LT3884_SYNC54
LT_PMBUS_ALERTn 44,48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
53 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
53 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
53 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C502
100uF
R366
0.001
C508
0.22uF
C509 6800pf
+
C5061000uF2.5V7343
D20
CMDSH-3
C500 10uF
1210
R385 DNI
C495
22uF
R38924.9K
C49010uF1210
R371
DNI
R384 DNI
C496
22uF
J13
2x6HDR
11
22
33
44
55
66
77
88
99
1010
1212
1111
C515
0.01uF
R39324.9K
R39011.3K
C503
100uF
R380
0
Q18
BSG0811ND
4
5
3
1
10
72
8
6
9
R372DNI
C511
22uF
R3945.76K
C497
22uF
R631
10.0K
C4892.2uF
TP5
C510 330pF
R406 0
Q16
MMST3906-7-F
SOT-323
C498
22uF
C512
22uF
R3671
R407 0
R39924.9K
R396
DNI
R40110.0K04021%
C504
100uF
R374DNI
C513
22uF
R4005.76K
R379
715
R3
75
DN
I
C501
1uF DNI
C516
0.1uF
R368
0
C514
22uF
R39510.0K04021%
R4020
+
C5071000uF2.5V7343
R3
76
DN
I
L8 0.25uH
R3771K
C499 10uF
1210
C521
100uF
R369
0
R387
715
R382
DNI
R3780
R39124.9K
C491 1uF
C520
0.01uF
R388
0
Q13
BSG0811ND
4
5
3
1
10
72
8
6
9
R405 0
C522
100uF
R3925.76K
R39724.9K
C492
150uF7343P
D19
CMDSH-3
U44
LTC3884EUK
TG135
SW134
BOOST136
IIN
-4
7
PG
ND
41
BOOST043
SW045
ITH_R05
SYNC11
SCL12
SDA13
ALERTB14
SHARE_CLK27
RUN017
RUN118
ITH_R130
ITH129
TSNS010
TSNS19
ASEL019
ASEL120
VD
D3
32
8
ITH06
WP26
VD
D2
52
5
IIN
+4
6
FAULT015
FAULT116
BG137
ISENSE1+3
VOUT1_CFG22 VSENSE1-
31
VSENSE1+32
ISENSE1-4
VSENSE0+1
ISENSE0-8
ISENSE0+7
BG042
VOUT0_CFG21
VSENSE0-2
49
GN
D
FREQ_CFG23
PHASE_CFG24
PG
OO
D1
33
PG
OO
D0
48
TG044
INT
VC
C3
8
VIN
39
EXTVCC40
TP6
C505
0.1uF
+
C5181000uF2.5V7343
C517
0.22uF
R3985.76K
R40324.9K
C493
10uF1210
L7 0.25uH
R386
0
Q15
BSG0811ND
4
5
3
1
10
72
8
6
9
+
C5191000uF2.5V7343
R383
0
Q17
MMST3906-7-F
SOT-323
R3734.7K
R381
10
R4045.76K
R8390
R365
0.001
C494
10uF1210
Q14
BSG0811ND
4
5
3
1
10
72
8
6
9
R370
10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
744301025
12V to VCC Core (Phase 2,3)
744301025
NORMAL
Check EXTVCC
DCR SENSING
LOWDCR
0.85V
SW2
TG2
BST2
TG3
BST3
BG3
SW3
LTC3874_AC_DC
LTC3874_ILIM
INTVCC2 EXTVCC12V_G1
VIN1
INTVCC2
INTVCC2
GND_SIGNAL_core
GND_SIGNAL_core
INTVCC2INTVCC2
INTVCC2
VIN1
GND_SIGNAL_core
S10MX_VCC
VIN1
VIN1
S10_VCC_EN48,53
S10_VCC_PG48,53
LT3884_ITH53
LT3884_SYNC53
S10_VCCFAULT48,53
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
54 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
54 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
Custom
54 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R422
0
+
C5461000uF2.5V7343
C532
100uF
R408
2
C527 1uF
R409 0
C528
4.7uF
R417
0
R413 0
D21
CMDSH-3
C538
22uF
R415
10.0K
0402
1%
C529
4.7uF
C535
0.22uF
R419
10.0K04021%
C530
0.1uF
C539
22uF
U45
LTC3874EUFD
MODE01
ISENSE0+2
ISENSE0-3
RUN04
RUN15
ISENSE1-6
ISENSE1+7
MODE18
ITH19
FREQ10
ILIM11
SYNC12
PHASMD13
TG114
SW115
BOOST116
BG117
EX
TV
CC
18
INT
VC
C1
9
VIN
20
BG021
BOOST022
SW023
TG024
FAULT125
LOWDCR27
ITH028
GN
D2
9
FAULT026
C542
0.1uF
C540
22uF
R423
DNI
R421
715
R416 100K
C541
22uF
C523
22uF
R410
715
C524
22uF
R411
0
L9 0.25uH
Q20
BSG0811ND
4
5
3
1
10
72
8
6
9
C536 22pF
C525
22uF
Q22
BSG0811ND
4
5
3
1
10
72
8
6
9
C537
0.22uF
C526
22uF
L10 0.25uH
C543
100uF
Q21
BSG0811ND
4
5
3
1
10
72
8
6
9
R418
10.0K
0402
1%
R414
DNI
C544
100uF
R420
DNI
+
C5331000uF2.5V7343
Q19
BSG0811ND
4
5
3
1
10
72
8
6
9
R412 0
D22
CMDSH-3
+
C5451000uF2.5V7343
C531
100uF+
C5341000uF2.5V7343
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
12A
Startix10 - VCCERAM
PGNDAGND
0.9V 5A
0.9V
3p3VS10_VCCERAM_LOW S10_VCCERAM
3p3V
S10_VCCERAM_LOW
S10_VCCERAM
VCCERAM_AGND
VCCERAM_AGND
VCCERAM_AGND
VCCERAM_AGND
VCCERAM_AGND
VCCERAM_AGND
S10_VCCERAM_PG 48
S10_VCCERAM_EN 48
S10_VCCERAM_SENSE_P 48
S10_VCCERAM_SENSE_N 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
55 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
55 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
55 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C548
47uf
R431 0
R427
DNI
R436DNI
R4240.003
C549
47uf
R433
4.7K
C551
100uF
C550
47uf
V53SENSE_PAD
RSNS1
SNS2
R432332K
R426165K
ST2
SHORT
11
22
R801 10
C552
47uf
R4344.42K
R429 0
C553
47uf
R425
DNI
V54SENSE_PAD
RSNS1
SNS2
C554
0.015uF
R430
10.0K
C555
0.22uF
R435DNI
U46
EN63A0QI
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
PVIN44
PVIN45
PVIN46
PVIN47
PVIN48
PVIN49
PVIN50
PVIN51
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND(THRM)77
POK58
VFB63
ENABLE59 AVIN60
S_OUT57
AGND61
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC1515
NC1616
NC1717
NC1818
NC1919
NC2929
NC30(SW)3030
NC30(SW)3131
NC(SW)7070
NC(SW)7171
NC7272
NC7373
NC7474
NC7575
NC7676
SS65
EN_PB69
EAOUT64
S_IN56
BGND55
VDDB54
VSENSE66
FQADJ68
NC(XREF)67
M/S62
NC5252
NC5353
C547
27pF
R42812K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
12A
Startix10 - VCCRL (1.12V/5A)
AGND PGND
1.12V 4A
1.12V
3p3V
S10_VCCRL_LOW S10_VCCRL_GXB
3p3V
S10_VCCRL_LOW
S10_VCCRL_GXB
VCCRL_AGND
VCCRL_AGND
VCCRL_AGND
VCCRL_AGND
VCCRL_AGND
VCCRL_AGND
S10_VCCRL_PG 48
S10_VCCRL_EN 48
S10_VCCRL_SENSE_P 48
S10_VCCRL_SENSE_N 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
56 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
56 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
56 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R811 10
R443
10.0K
C564
0.22uF
R448DNI
R446
4.7K
U47
EN63A0QI
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
PVIN44
PVIN45
PVIN46
PVIN47
PVIN48
PVIN49
PVIN50
PVIN51
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND(THRM)77
POK58
VFB63
ENABLE59 AVIN60
S_OUT57
AGND61
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC1515
NC1616
NC1717
NC1818
NC1919
NC2929
NC30(SW)3030
NC30(SW)3131
NC(SW)7070
NC(SW)7171
NC7272
NC7373
NC7474
NC7575
NC7676
SS65
EN_PB69
EAOUT64
S_IN56
BGND55
VDDB54
VSENSE66
FQADJ68
NC(XREF)67
M/S62
NC5252
NC5353
C558
100uFC561
27pF
R44112K
C562
47uf
R444 0
R440
DNI
R449DNI
R4370.003
C556
47uf
ST3
SHORT
11
22
C557
47uf
V55SENSE_PAD
RSNS1
SNS2
R445191K
R439165K
C559
47uf
R4474.42K
R442 0
C560
47uf
R438
DNI
V56SENSE_PAD
RSNS1
SNS2
C563
0.015uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Startix10 - VCCRR (1.12V/5A)
12A
AGND PGND
1.12V
S10_VCCRR_PG
3p3VS10_VCCRR_LOW S10_VCCRR_GXB
3p3V
S10_VCCRR_LOW
S10_VCCRR_GXB
VCCRR_AGND
VCCRR_AGND
VCCRR_AGND
VCCRR_AGND
VCCRR_AGND
VCCRR_AGND
S10_VCCRR_PG 48
S10_VCCRR_EN 48
S10_VCCRR_SENSE_P 48
S10_VCCRR_SENSE_N 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
57 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
57 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
57 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R456
10.0K
C573
0.22uF
R461DNI
U48
EN63A0QI
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
PVIN44
PVIN45
PVIN46
PVIN47
PVIN48
PVIN49
PVIN50
PVIN51
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND(THRM)77
POK58
VFB63
ENABLE59 AVIN60
S_OUT57
AGND61
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC1515
NC1616
NC1717
NC1818
NC1919
NC2929
NC30(SW)3030
NC30(SW)3131
NC(SW)7070
NC(SW)7171
NC7272
NC7373
NC7474
NC7575
NC7676
SS65
EN_PB69
EAOUT64
S_IN56
BGND55
VDDB54
VSENSE66
FQADJ68
NC(XREF)67
M/S62
NC5252
NC5353
R459
4.7K
C570
27pF
R45412K
C567
100uF
R812 10
C571
47uf
R457 0
R453
DNI
R462DNI
R4500.003
C565
47uf
C566
47ufR452165K
V57SENSE_PAD
RSNS1
SNS2
ST4
SHORT
11
22
R458191K
C568
47uf
R4604.42K
R455 0
C569
47uf
R451
DNI
V58SENSE_PAD
RSNS1
SNS2
C572
0.015uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Startix10 - VCCT
12A
PGNDAGND
1.12V
3p3VS10_VCCT_LOW S10_VCCT_GXB
3p3V
S10_VCCT_LOW
S10_VCCT_GXB
VCCT_AGND
VCCT_AGND
VCCT_AGND
VCCT_AGND
VCCT_AGND
VCCT_AGND
S10_VCCT_PG 48
S10_VCCT_EN 48
S10_VCCT_SENSE_P 48
S10_VCCT_SENSE_N 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
58 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
58 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
58 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C576
47uf
C577
47uf
V59SENSE_PAD
RSNS1
SNS2
R472
4.7K
R471191K
C578
100uFC579
47uf
R4734.42K
R468 0
ST5
SHORT
11
22
C580
47uf
R813 10
R465
DNI
V60SENSE_PAD
RSNS1
SNS2
C581
0.015uF
R469
10.0K
C582
0.22uF
R474DNI
U49
EN63A0QI
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
PVIN44
PVIN45
PVIN46
PVIN47
PVIN48
PVIN49
PVIN50
PVIN51
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND(THRM)77
POK58
VFB63
ENABLE59 AVIN60
S_OUT57
AGND61
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC1515
NC1616
NC1717
NC1818
NC1919
NC2929
NC30(SW)3030
NC30(SW)3131
NC(SW)7070
NC(SW)7171
NC7272
NC7373
NC7474
NC7575
NC7676
SS65
EN_PB69
EAOUT64
S_IN56
BGND55
VDDB54
VSENSE66
FQADJ68
NC(XREF)67
M/S62
NC5252
NC5353
C574
27pF
R46712K
R466165K
C575
47uf
R470 0
R464
DNI
R475DNI
R4630.003
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - VCCH_GXB/VCCIO
12A
AGND PGND
1.8V
3p3V1p8V
3p3V
1p8V_AGND
1p8V_AGND
1p8V_AGND
1p8V_AGND
1p8V_AGND
1p8V_AGND
1p8V_PG 48
1p8V_EN 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
59 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
59 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
59 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C588
27pF
R47912K
U50
EN63A0QI
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
PVIN44
PVIN45
PVIN46
PVIN47
PVIN48
PVIN49
PVIN50
PVIN51
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND(THRM)77
POK58
VFB63
ENABLE59 AVIN60
S_OUT57
AGND61
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC1515
NC1616
NC1717
NC1818
NC1919
NC2929
NC30(SW)3030
NC30(SW)3131
NC(SW)7070
NC(SW)7171
NC7272
NC7373
NC7474
NC7575
NC7676
SS65
EN_PB69
EAOUT64
S_IN56
BGND55
VDDB54
VSENSE66
FQADJ68
NC(XREF)67
M/S62
NC5252
NC5353
C589
47uf
R482 0
R478
DNI
R487DNI
C583
47uf
R484
4.7K
C584
47uf
C585
100uF
R48382.5K
C591
0.22uF
C586
47uf
R4854.42K
R480 0
C587
47uf
R814 10
R476
DNI
C590
0.015uF
ST6
SHORT
11
22
R477165K
R481
10.0K
R486DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - VCCIO_UIB
Rtune = 0 for 1x BaseRtune = 392 for 2x Base
Raddr0
Raddr1
Rvset
Rsync
Remote sense at FPGA
PGND
Rdiv1
I2C ADDR = 31H
Cout = 2xBase = 1528uF
PLACE Output decoupling capsclose to the device. ConnectAGND and PGND at the point of cap GND connection.
(Top Side 30mil pad,No Via)
H = 6.76 mmPlace on Top side
Rdiv2
Place closeto EM2130
AGND
1.2V
1V2_VCCSEN1v2_RVSET 1V2_VTRACK1v2_RTUNE1v2_VINSEN1V2_ADDR11V2_ADDR01V2_PWM 1V2_VSENN1V2_SYNC 1V2_VSENP 1V2_VSENP_R
1V2_SMBALERT
1V2_VCC
3p3V
5V
12V_G1
1V2_VCCIO_UIB_AGND
12V_G1
1V2_VCCIO_UIB_AGND
1p2V_VCCIO_UIB
1V2_VCCIO_UIB_AGND
1V2_VCCIO_UIB_AGND
1V2_VCCIO_UIB_AGND1V2_VCCIO_UIB_AGND
1V2_VCCIO_UIB_AGND
VCCIO_UIB_EN48
EM_SDA52EM_SCL52
1p2V_VCCIO_UIB_PG48
EM_PMBUS_ALERTn44,48,52
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
60 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
60 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
60 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C6030.1uF, DNI040225VX6S
ST7
SHORT
11
22
R48910.0K0402
1%
R493 00402 5%
C600470uF29172.5VAlum Poly
C59447uF DNI120610VX6S
R49010.0K0402
1%
FB16600 Ohm, 0.5A, 0.35DCR
0603
C607
22uF
C599100uF DNI12066.3VX6T
R497 680 ohm0402 1%
C59247uF120610VX6S
R632 4.7K
C613100uF2917_4p3mm25VTant Poly
R494 10.0K0402 1%
C59347uF120610VX6S
U51EM2120L01QI
AGND70
NC6868
VSENP71VSENN72
VOUT79
VOUT3
VTRACK77
ADDR17
VOUT80
ADDR08
RTUNE5
VOUT2
VCCSEN78
RVSET4
SCL15 SDA14
PG
ND
32
VDD3316
VCC66
NC7676
DGND69
PWM9
VOUT81
VINSEN6
VOUT1
SMBALERT13 CONTROL12 PGOOD11 SYNC10
PG
ND
33
PG
ND
34
PG
ND
35
PG
ND
36
PG
ND
37
PG
ND
38
PG
ND
39
PG
ND
40
PG
ND
42
PG
ND
43
PG
ND
44
PG
ND
45
PG
ND
46
PG
ND
47
PG
ND
48
PG
ND
49
PG
ND
50
PG
ND
41
PGND22
PGND23
PGND24
PGND25
PGND26
PGND27
PGND28
PGND29
PGND30
PGND31
PGND60
PGND59
PGND58
PGND57
PGND56
PGND55
PGND54
PGND53
PGND52
PGND51
PVIN61PVIN62PVIN63PVIN64
PVCC65
NC6767
NC7575
NC7474
NC7373
PVIN17
PVIN18
PVIN20
PVIN21
VO
UT
10
0
VO
UT
99
VO
UT
98
VO
UT
97
VO
UT
96
VO
UT
95
VO
UT
94
VO
UT
93
VO
UT
92
VO
UT
91
VO
UT
90
VO
UT
89
VO
UT
88
VO
UT
87
VO
UT
86
VO
UT
85
VO
UT
84
VO
UT
83
VO
UT
82
PVIN_PAD103
PGND_PAD104
AGND_PAD102
VO
UT
_P
AD
10
1
PVIN19
C609
22uF
R495 3.3K0402 1%
C6111uF040225VX6S
C6101uF040225VX6S
C598100uF DNI12066.3VX6T
TP7TESTPOINT
1T
P
C606
22uF
C601470uF DNI29172.5VAlum Poly
R498 0, DNI0402 5%
C6040.1uF040225VX6S
ST8
SHORT
11
22
ST9
SHORT
11
22
C6120.1uF040225VX6S
C605
22uF
R50211K04020.1%
R491 2.43K0402 0.1%
C597100uF12066.3VX6T
C596100uF12066.3VX6T
R5012K, DNI04020.1%
R5031K04020.1%
C608
22uF
R492 1.8K0402 1%
C6021000pF, DNI040250VX7R
R500 0
R496 0, DNI0402 5%
R499 2K
04020.1%
C59547uF DNI120610VX6S
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCM
6A
2A
AGND PGND
2.5V 2.5V
3p3V
VCCM
3p3V
VCCM_AGND
VCCM_AGND
VCCM_AGND
VCCM_EN 48
VCCM_PG 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
61 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
61 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
61 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C620
100uF
C618
22uF
C621
15nF
C617
22uF
C616
15pF
R505160K
R516
5.49K
R507 0
C622
0.22uF
C615
22uF
ST10
SHORT
11
22
R506
15K
EN6362QI
U60
EN6362QI
PVIN129
PVIN230
PVIN331
PVIN432
PVIN533
PVIN634
PVIN735
PVIN836
PVIN9 DNC59
ENABLE41
AVIN43
VOUT115
VOUT216
VOUT317
VOUT418
VOUT5 DNC58
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
PGND124
PGND225
PGND326
PGND427
PGND528
NC1111
NC1212
NC1313
NC1414
NC1519
NC1620
NC1721
NC1822
NC1937
NC2038
NC2153
NC2254
NC2355
NC2456
NC(SW)123
NC(SW)249
NC(SW)350
NC(SW)451
VFB42
AGND44
VDDB39
BGND40
PGOOD48
PGND(THRM)57
SS46
FQADJ45
VSENSE47
NC(SW)552
NC60
R508
4.7K
C619
47uf
R5
13
0
C614
100uF
R806 10
R504
DNI
R5
11
49
.9K
R510
100K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - VCCIO_1.2V_DDR4
12A
AGND PGND
1.2V
3p3V1p2V_DDR4
3p3V
1p2V_DDR4_AGND
1p2V_DDR4_AGND
1p2V_DDR4_AGND
1p2V_DDR4_AGND
1p2V_DDR4_AGND
1p2V_DDR4_AGND
1p2V_DDR4_PG 48
1p2V_DDR4_EN 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
62 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
62 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
62 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R519160K
C628
47uf
R5264.42K
R521 0
C629
47uf
R518
DNI
C630
0.015uF
U53
EN63A0QI
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
PVIN44
PVIN45
PVIN46
PVIN47
PVIN48
PVIN49
PVIN50
PVIN51
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND(THRM)77
POK58
VFB63
ENABLE59 AVIN60
S_OUT57
AGND61
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC1515
NC1616
NC1717
NC1818
NC1919
NC2929
NC30(SW)3030
NC30(SW)3131
NC(SW)7070
NC(SW)7171
NC7272
NC7373
NC7474
NC7575
NC7676
SS65
EN_PB69
EAOUT64
S_IN56
BGND55
VDDB54
VSENSE66
FQADJ68
NC(XREF)67
M/S62
NC5252
NC5353
R522
10.0K
C631
0.22uF
C627
100uF
R527DNI
R525
4.7K
C624
27pF
C625
47uf
R52012K
ST11
SHORT
11
22
R524160K
R523 0
C626
47uf
R517
DNI
R528DNI
R807 10
C623
47uf
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0.6V
0.6V
Vih=1.7, Vil = 0.3
Vih=1.7, Vil = 0.3
0.6V
0.6V
DIMM_VTT_PG
COMP_VTT_PG
0p6V_DDR4_DIMM_VTT
3p3V1p2V_DDR4
0p6V_DDR4_DIMM_VTT
1p2V_DDR4
0p6V_DDR4_COMP_VTT
3p3V1p2V_DDR4
0p6V_DDR4_COMP_VREF 0p6V_DDR4_COMP_VTT
1p2V_DDR4
0p6V_DDR4_DIMM_VREF
3p3V
3p3V
DIMM_VTT_EN48
COMP_VTT_EN48
DIMM_VTT_PG 48
COMP_VTT_PG 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
63 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
63 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
63 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C632 2.2uF0402 10V
X6S
U54
TPS51200DRCR
VSON-11
VIN10
VLDOIN2
EN7
REFIN1
PGOOD9
VO3
VOSNS5
REFOUT6
GND8
PGND4
MPAD11
C647
22uF0603
C640
22uF0603
C638
22uF0603
R633 10.0K0402 1%
R530 DNI0402 1%
C6410.1uF040225VX6S
C652
22uF0603
R536 0 C655
22uF0603
C649
22uF0603
C6560.1uF040225VX6S
R53310.0K04021%
C645 2.2uF0402 10V
X6S
C635
22uF0603
U55
TPS51200DRCR
VSON-11
VIN10
VLDOIN2
EN7
REFIN1
PGOOD9
VO3
VOSNS5
REFOUT6
GND8
PGND4
MPAD11
C646
22uF0603
C64410nF040250VX7R
R53810.0K04021%
R535 DNI0402 1%
C651
22uF0603
R532 10.0K0402 1%
C65710nF040250VX7R
C642
22uF0603
C639
22uF0603
R634 10.0K0402 1%
C654
22uF0603
C648
22uF0603
C634
22uF0603
R531 0
C653
22uF0603
R52910.0K04021%
R537 10.0K0402 1%
R53410.0K04021%
C650
22uF0603
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PGND
PLACE Output decoupling capsclose to the device. ConnectAGND and PGND at the point of cap GND connection.
AGND
Pwr - HiLo VDDQ
H = 3.00mmPlace on Top side
HILO will GND the required SET pin togenerate VDDQ voltage for memory interface. The default vaule is 1.2V.
S10 HILO_VDDQ & VCCIO_HILOVariable 1.2V, 1.25V, 1.35V, 1.5V, 1.8V
HILO_VDDQ
HILO_VDDQ_AGND
3p3V
3p3V
HILO_VDDQ_AGND
HILO_VDDQ_AGND
HILO_VDDQ_PG 48
HILO_VDDQ_1p5V_SET 18
HILO_VDDQ_1p35V_SET 18
HILO_VDDQ_1p25V_SET 18
HILO_VDDQ_1p3V_SET 18
HILO_VDDQ_1p8V_SET 18
HILO_VDDQ_EN 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
64 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
64 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
64 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C659
47uf
R54510.0K
C660
100uF
R5525.49K
C662
22uF
C666
47nF
C663
22pF
R546294K
R539
DNI
C665
100uF
R542 0
R544
4.7K
R547
3.48M
C661
22uF
ST12
SHORT
11
22
C664
47uf
R543 10
C667
0.22uF
R5481.69M
R5491.15M
R540294K
R550
576K
EN6362QI
U56
EN6362QI
PVIN129
PVIN230
PVIN331
PVIN432
PVIN533
PVIN634
PVIN735
PVIN836
PVIN9 DNC59
ENABLE41
AVIN43
VOUT115
VOUT216
VOUT317
VOUT418
VOUT5 DNC58
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
PGND124
PGND225
PGND326
PGND427
PGND528
NC1111
NC1212
NC1313
NC1414
NC1519
NC1620
NC1721
NC1822
NC1937
NC2038
NC2153
NC2254
NC2355
NC2456
NC(SW)123
NC(SW)249
NC(SW)350
NC(SW)451
VFB42
AGND44
VDDB39
BGND40
PGOOD48
PGND(THRM)57
SS46
FQADJ45
VSENSE47
NC(SW)552
NC60
R54115K
R551294K
C658
47uf
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H = 3.00mmPlace on Top side
HILO VDD
S10 HILO_VDDVariable 1.2V, 1.25V, 1.3V, 1.35V, 1.5V, 1.8V
HILO will GND the required SET pin to generate VDDQ voltage for memory interface. The default vaule is 1.2V.
AGND PGND
PLACE Output decoupling capsclose to the device. ConnectAGND and PGND at the point of cap GND connection.
3p3V
HILO_VDD
3p3V
HILO_VDD_AGND
HILO_VDD_AGND
HILO_VDD_AGND HILO_VDD_1p5V_SET 18
HILO_VDD_1p8V_SET 18
HILO_VDD_1p35V_SET 18
HILO_VDD_1p3V_SET 18
HILO_VDD_1p25V_SET 18
HILO_VDD_PG 48
HILO_VDD_EN 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
65 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
65 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
65 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R561
3.48M
R5621.69M
R55810
C675
0.22uF
R559
4.7K
R5631.15M
R564
576K
C669
22uF
R565294K
R555294K
R557
10.0K
R55615K
EN6362QI
U57
EN6362QI
PVIN129
PVIN230
PVIN331
PVIN432
PVIN533
PVIN634
PVIN735
PVIN836
PVIN9 DNC59
ENABLE41
AVIN43
VOUT115
VOUT216
VOUT317
VOUT418
VOUT5 DNC58
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
PGND124
PGND225
PGND326
PGND427
PGND528
NC1111
NC1212
NC1313
NC1414
NC1519
NC1620
NC1721
NC1822
NC1937
NC2038
NC2153
NC2254
NC2355
NC2456
NC(SW)123
NC(SW)249
NC(SW)350
NC(SW)451
VFB42
AGND44
VDDB39
BGND40
PGOOD48
PGND(THRM)57
SS46
FQADJ45
VSENSE47
NC(SW)552
NC60
C672100uF12066.3VX6T
C670
47uf
R5665.49K
C674
47nF
C671
47uf
ST13
SHORT
11
22
C668
22uF
R560294K
C673
22pFR553
DNI
R554 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0402
VIN = 2.4 - 6.6 VDC
Connect the input cap to the GND plane through multiple vias.(see the Gerber files)
1206
0402
Connect the output cap to the GND plane through multiple vias
1206 X5R
0402
X5R
0402
PGND
PLACE Output decoupling capsclose to the device. ConnectAGND and PGND at the point of cap GND connection.
AGND
Pwr - 2.5V VDDR4
2.5V
3p3V
2p5V
2p5V_AGND
2p5V_AGND
2p5V_AGND
3p3V
2p5V_PG 48
2p5V_EN 48
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
66 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
66 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
66 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R572DNI
R570 4.7K
R574
0
R5690
C680 47uF
R568 DNI
C677
15pF
R573
200k
C67615nF
C678 47uF
U58
EN6337QI
NC(SW)71
NC(SW)62
NC33
NC44
VOUT5
VOUT6
VO
UT
7
VO
UT
8
VO
UT
9
VO
UT
10
VO
UT
11
NC
(SW
)1
2
PG
ND
13
PG
ND
14
PG
ND
15
PG
ND
16
PG
ND
17
PG
ND
18
PV
IN1
9
NC2525
NC2424
NC2323
NC2222
PVIN21
PVIN20
NC
(SW
)13
8
NC
(SW
)23
7
NC
(SW
)33
6
NC
(SW
)43
5
NC
(SW
)53
4
AV
IN3
3
AG
ND
32
VF
B3
1
SS
30
RL
LM
29
PO
K2
8
EN
AB
LE
27
LL
M/S
YN
C2
6
GN
D_
PA
D3
9
ST14
SHORT
11
22
C679 22uF
R567
100k
R571
84.5K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Fast Power-Down Discharge
S10_VCCT_GXB
S10_VCCRR_GXB
S10_VCCERAM
1p2V_DDR4
1p2V_VCCIO_UIB
HILO_VDD
HILO_VDDQ
3p3V
2p5V
VCCM
1p8V
S10_VCCRL_GXB
1p2V_DDR4_DIS49
VCCIO_UIB_DIS49
HILO_VDD_DIS49
HILO_VDDQ_DIS49
3p3V_DIS49
2p5V_DIS49
VCCM_DIS49
1p8V_DIS49
VCCRL_GXB_DIS49
VCCRR_GXB_DIS49
VCCT_DIS49
VCCERAM_DIS49
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
67 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
67 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
67 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Q35NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R57910
04021%
R77310
04021%
Q38NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R79210.0K04021%
R78310.0K04021%
R787 2.2 Ohm5%
2W
R77410.0K04021%
R595 2.2 OhmCRM2512 5%
2W
R768 0.5
R79310
04021%
R57710.0K04021%
Q34NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
Q37NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R58910
04021%
R78010.0K04021%
R77510
04021%
Q27NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
Q33NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R771 1 OhmL2512 1%
2W
R76910.0K04021%
R800 0.5
R794 0.5
Q30NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R77010
04021%
Q36NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R78910.0K04021%
R77710.0K04021%
R791 0.5
R79810.0K04021%
Q32NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R79010
04021%
Q28NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R78510
04021%
R79910
04021%
R781 2.2 OhmCRM2512 5%
2W
R58710.0K04021%
R767 0.5
R79510.0K04021%
R797 0.5
R78210
04021%
Q29NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R772 1 OhmL2512 1%
2W
Q31NFET_CSD17313Q2T3 G
1D12D25D36D48D5
4S17S2
R77810
04021%
R788 1 OhmL2512 1%
2W
R78610.0K04021%
R79610
04021%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Decoupling - page 1S10MX_VCC
1p8V
S10_VCCERAM
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
68 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
68 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
68 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C794
330uF
C871
0.047uF
C1478
0.1uF
C720
0.47uF
C1377
330uF
C698
0.22uF
C764
4.7uF
C766
100uF
C684
0.22uF
C738
1uF
C767
100uF
C1576
0.22uF
C695
0.22uF
C1309
0.22uF
C779
220uF
C802
330uF
C1320
0.22uF
C879
100uF
C877
0.47uF
C1479
0.1uF
C868
0.022uF
C783
220uF
C719
0.47uF
C875
0.1uF
C737
1uF
C801
330uF
C1577
0.22uF
C1469
0.47uF
C880
220uF6.3V
C706
0.47uF
C1382
330uF
C1310
0.22uF
C711
0.47uF
C1321
0.22uF
C1376
330uF
C1367
220uF
C800
330uF
C696
0.22uF
C1371
220uF
C864
0.01uF
C1466
0.47uF
C739
1uF
C1578
0.22uF
C873
0.047uF
C1311
0.22uF
C776
100uF
C1322
0.22uF
C712
0.47uF
C760
4.7uF
C861
0.01uF
C746
1uF
C732
1uF
C731
1uF
C798
330uF
C1366
220uF
C740
1uF
C1375
330uF
C1579
0.22uF
C782
220uF
C1312
0.22uF
C713
0.47uF
C1374
330uF
C795
330uF
C748
1uF
C775
100uF
C700
0.22uF
C685
0.22uF
C799
330uF
C1381
330uF
C1580
0.22uF
C733
1uF
C1470
0.1uF
C715
0.47uF
C797
330uF
C683
0.22uF
C774
100uF
C747
1uF
C866
0.01uF
C788
220uF
C692
0.22uF
C876
0.22uF
C721
0.47uF
C707
0.47uF
C1581
0.22uF
C1471
0.1uF
C694
0.22uF
C1467
0.47uF
C714
0.47uF
C867
0.022uF
C682
0.22uF
C773
100uF
C749
1uF
C1569
0.22uF
C1370
220uF
C1380
330uF
C734
1uF
C722
0.47uF
C1313
0.22uF
C1582
0.22uF
C1472
0.1uF
C750
1uF
C787
220uF
C708
0.47uF
C693
0.22uF
C1570
0.22uF
C1303
0.22uF
C781
220uF
C863
0.01uF
C1314
0.22uF
C872
0.047uF
C723
0.47uF
C741
1uF
C878
2.2uF
C1583
0.22uF
C772
100uF
C1473
0.1uF
C735
1uF
C761
4.7uF
C1571
0.22uF
C687
0.22uF
C1304
0.22uF
C725
0.47uF
C1315
0.22uF
C1584
0.22uF
C743
1uF
C786
220uF
C1474
0.1uF
C709
0.47uF
C686
0.22uF
C771
100uF
C796
330uF
C869
0.022uF
C1379
330uF
C870
0.022uF
C697
0.22uF
C1572
0.22uF
C1305
0.22uF
C1316
0.22uF
C724
0.47uF
C742
1uF
C1585
0.22uF
C1369
220uF
C1475
0.1uF
C762
4.7uF
C874
0.1uF
C699
0.22uF
C1383
220uF
C1468
0.47uF
C716
0.47uF
C681
0.22uF
C785
220uF
C765
100uF
C770
100uF
C1573
0.22uF
C710
0.47uF
C689
0.22uF
C1306
0.22uF
C1317
0.22uF
C1586
0.22uF
C865
0.01uF
C744
1uF
C778
220uF
C1476
0.1uF
C690
0.22uF
C1378
330uF
C717
0.47uF
C780
220uF
C1574
0.22uF
C1307
0.22uF
C862
0.01uF
C763
4.7uF
C1318
0.22uF
C688
0.22uF
C1373
330uF
C745
1uF
C769
100uF
C1587
0.22uF
C784
220uF
C1477
0.1uF
C718
0.47uF
C736
1uF
C768
100uF
C1575
0.22uF
C691
0.22uF
C777
220uF
C1308
0.22uF
C803
330uF
C1319
0.22uF
C1368
220uF
C1372
220uF
C1588
0.22uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Decoupling - page 2
1p8V_FLTR
S10_VCCRL_GXB
S10_VCCRR_GXB
S10_VCCT_GXB
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
69 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
69 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
69 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C986
0.1uF
C1063
0.1uF
C936
0.047uF
C1268
0.1uF
C953
0.22uF
C975
330uF
C1244
0.047uF
C1282
1uF
C1491
0.022uF
C1257
0.047uF
C1489
0.047uF
C937
0.047uF
C1064
0.1uF
C1018
0.022uF
C1483
0.022uF
C1269
0.1uF
C1245
0.047uF
C932
0.047uF
C1065
0.1uF
C1019
0.022uF
C1270
0.1uF
C933
0.047uF
C1246
0.047uF
C941
0.1uF
C1488
0.047uF
C1066
0.1uF
C1020
0.022uF
C944
0.1uF
C1482
0.022uF
C1271
0.1uF
C1247
0.047uF
C989
2.2uF
C942
0.1uF
C901
0.022uF
C1021
0.022uF
C945
0.1uF
C1492
0.047uF
C1073
0.22uF
C1272
0.22uF
C1248
0.047uF
C988
1uF
C927
0.047uF
C934
0.047uF
C1481
0.022uF
C1074
0.22uF
C1022
0.022uF
C946
0.1uF
C1487
0.047uF
C1273
0.22uF
C1249
0.047uF
C943
0.1uF
C935
0.047uF
C1493
0.047uF
C1038
0.047uF
C1075
0.22uF
C1274
0.22uF
C1250
0.047uF
C1480
0.022uF
C987
0.22uF
C1076
0.22uF
C1039
0.047uF
C1275
0.22uF
C902
0.022uF
C1494
0.047uF
C947
0.1uF
C1251
0.047uF
C928
0.047uF
C1465
330uF
C1486
0.022uF
C955
0.47uF
C1238
0.022uF
C950
0.22uF
C1077
0.47uF
C1040
0.047uF
C1276
0.22uF
C948
0.1uF
C1252
0.047uF
C929
0.047uF
C949
0.22uF
C1264
0.1uF
C1239
0.022uF
C1495
0.047uF
C1078
0.47uF
C1041
0.047uF
C1278
0.47uF
C1253
0.047uF
C903
0.022uF
C939
0.047uF
C951
0.22uF
C1485
0.022uF
C1265
0.1uF
C1240
0.022uF
C1057
0.022uF
C1080
1uF
C1042
0.047uF
C1279
0.47uF
C1254
0.047uF
C991
100uF
C938
0.047uF
C930
0.047uF
C959
1uF
C956
0.47uF
C1266
0.1uF
C958
1uF
C1241
0.022uF
C1043
0.047uF
C1280
0.47uF
C952
0.22uF
C1058
0.022uF
C1255
0.047uF
C1100
330uF
C1484
0.022uF
C957
0.47uF
C940
0.047uF
C931
0.047uF
C1490
0.022uF
C1062
0.1uF
C904
0.022uF
C1267
0.1uF
C1242
0.022uF
C1281
1uF
C1059
0.022uF
C1256
0.047uF
C905
0.022uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Decoupling - page 3
Place C1529~C1545 under FPGA BGA
HILO_VDD
2p5V
3p3V
HILO_VDDQ
VCCPLL_SDM
VCCPLLDIG_SDM
1p2V_VCCIO_UIB
VCCM 0p6V_DDR4_DIMM_VREF 0p6V_DDR4_COMP_VREF
1p2V_DDR4
HILO_VDDQ
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
70 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
70 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
A0
Stratix 10 MX FPGA Dev Kit
B
70 70Friday, February 09, 2018
150-0330648 (6XX-44584R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C1126
0.047uF
C1184
0.022uF
C1540
0.22uF
C1401
0.22uFC1181
0.01uF
C1188
0.1uF
C1103
0.047uF
C1335
2.2uF
C1392
0.1uF
C1141
1uF
C1258
0.022uF C1547
22uF
C1533
0.1uF
C1125
0.047uF
C1562
0.22uF
C1336
2.2uF
C1261
0.047uF
C1179
0.01uF
C1541
0.22uF
C1161
0.022uF
C1115
0.047uF
C1101
0.01uF
C1393
0.1uF
C1102
0.022uF
C1342
0.22uF
C1341
0.22uF
C1136
0.047uF
C1182
0.01uF
C1259
0.047uF
C1534
0.22uF
C1111
0.022uF
C1343
0.47uF
C1394
0.1uF
C1135
0.047uF
C1163
10uF
C1505
220uF6.3V
C1549
22uF
C1418
1uF
C1165
22uF0603
C1124
0.047uF
C1196
220uF6.3V
C1402
0.22uF
C1114
0.047uF
C1187
0.047uF
C1158
0.47uF
C1395
0.1uF
C1134
220uF6.3V
C1284
1uF
C1563
0.22uF
C1504
220uF6.3V
C1286
100uF
C1423
2.2uF
C1409
0.47uF
C1535
0.22uF
C1192
100uF
C1194
100uF
C1197
220uF6.3V
C1403
0.22uF
C1146
1uF
C1120
0.022uFC1133
220uF6.3V
C1113
0.022uF
C1496
0.047uF
C1128
0.1uF
C1542
0.22uF
C1285
10uF
C1564
0.22uF
C1410
0.47uF
C1185
0.022uF
C1123
0.047uF
C1404
0.22uF
C1112
0.022uF
C1497
0.047uF
C1424
4.7uF
C1129
0.1uF
C1543
0.22uF
C1565
0.22uF
C1419
1uF
C1536
0.22uF
C1546
22uF
C1396
0.1uF
C1411
0.47uF
C1405
0.22uF
C1122
0.022uF
C1162
0.1uF
C1425
4.7uF
C1109
0.022uF
C1138
0.1uF
C1498
0.1uF
C1183
0.022uF
C1544
0.22uF
C1529
0.1uF
C1397
0.1uF
C1412
0.47uF
C1384
0.1uF
C1121
0.022uF
C1537
0.22uF
C1406
0.22uF
C1107
0.022uF
C1139
0.1uF
C1499
0.1uF
C1426
4.7uF
C1545
0.22uF
C1420
1uF
C1398
0.1uF
C1413
0.47uF
C1548
22uF
C1387
0.1uF
C1407
0.22uF
C1118
0.022uF
C1143
220uF6.3V
C1130
0.47uF
C1108
0.022uF
C1500
0.1uF
C1530
0.1uF
C1566
0.22uF
C1191
1uF
C1262
0.47uF
C1357
0.1uF
C1160
0.01uF
C1337
0.1uF
C1414
0.47uF
C1388
0.1uF
C1116
0.022uF
C1408
0.22uF
C1132
4.7uF
C1110
0.022uF
C1501
0.47uF
C1567
0.22uF
C1358
0.1uF
C1421
1uF
C1415
0.47uF
C1560
0.22uF
C1145
0.022uF
C1389
0.1uF
C1531
0.1uF
C1195
100uF
C1193
100uF
C1345
2.2uF
C1140
0.47uF
C1144
220uF6.3V
C1117
0.022uF
C1260
0.1uF
C1127
0.1uF
C1105
22uF0603
C1502
1uF
C1568
0.22uF
C1180
0.01uF
C1186
0.047uF
C1538
0.22uF
C1263
1uF
C1399
0.22uF
C1359
0.1uF
C1416
0.47uF C1189
0.22uF
C1390
0.1uF
C1142
4.7uF
C1119
0.022uFC1131
1uF
C1503
4.7uF
C1338
0.1uF
C1532
0.1uF
C1539
0.22uF
C1561
0.22uF
C1400
0.22uF
C1360
0.1uF
C1190
1uF
C1417
0.47uF
C1422
1uF
C1391
0.1uF
C1157
0.47uF
C1137
0.1uF