presentation title goes here - applied materials · 2017-07-11 · samsung exynos iot chip (28nm)...

JULY 10, 2017

WELCOME Maydan Technology Center Event

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Forward-Looking Statements and Other Information

These presentations contain forward-looking statements, including those regarding anticipated growth and trends in our

businesses and markets, industry outlooks, technology inflections, our strategies, our development of new products and

technologies, the anticipated demand for our products, growth in our market share positions and opportunities, our business

and financial performance and outlook, and other statements that are not historical facts. These statements and their

underlying assumptions are subject to risks and uncertainties and are not guarantees of future performance. Factors that could

cause actual results to differ materially from those expressed or implied by such statements include, without limitation: the level

of demand for our products; global economic and industry conditions; consumer demand for electronic products; customers’

technology and capacity requirements; the introduction of new and innovative technologies, and the timing of technology

inflections; our ability to develop, deliver and support new products, expand our markets and increase market share; the

concentrated nature of our customer base; market acceptance of existing and newly developed products; our ability to obtain

and protect intellectual property rights in key technologies; our ability to achieve the objectives of operational and strategic

initiatives, and attract, motivate and retain key employees; the variability of operating expenses and results among products

and segments, and our ability to accurately forecast future results, market conditions, customer requirements and business

needs; and other risks and uncertainties described in our most recent Form 10-Q and other SEC filings. All forward-looking

statements are based on management’s estimates, projections and assumptions as of July 10, 2017, and we assume no

obligation to update them. All information and data that speaks as of a future date are based on management’s estimates,

projections and assumptions, unless otherwise noted.

These presentations also include non-GAAP adjusted financial measures, along with reconciliations to GAAP measures.

Applied Materials, the Applied Materials logo, and other trademarks so designated as product names are trademarks of Applied

Materials, Inc. Other names and brands are the property of third parties.

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JULY 10, 2017 MAYDAN TECHNOLOGY CENTER EVENT

IntroductionMike Sullivan | Vice President, Investor Relations

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WELCOME

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Markets are

growing and playing

to our strengths

We are better

positioned than

ever before

“OVERALL MARKET”

Emerging trends (IoT,

Big Data, AI) shifting

value to semi and display

“APPLIED’S MARKETS”

Semi and display

roadmaps increasingly

enabled by materials

We have a

platform for

sustainable growth

Broadest and

deepest capabilities

Inflection-focused

innovation strategy

Growing investment

in new, enabling

products

Operating system for

repeatable success –Product Development

Engine

Strong organization,

teams and execution

WHAT YOU’LL HEAR TODAY….

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AG

EN

DA 1:00 Introduction | Mike Sullivan

1:15 Memory Technology and 3D Scaling | Raman Achutharaman, Gill Lee, Sundeep Bajikar

2:10 Break

2:25 Disruptive Patterning for Next Generation Devices | Uday Mitra, Regina Freed

3:20 Investment in Innovative Products | Bob Halliday

3:40 Innovation Leadership and the Maydan Technology Center | Steve Ghanayem

4:10 Maydan Technology Center Tours

5:00 Executive Reception

6:00 Optional Transportation to San Francisco

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www

7

Rising WFE Driven

by New Devices

and Applications

Artificial Intelligence

+ Visual Computing

* 2000 – 2009 ** 2010 – 2016

2000 2010 2016

Av. WFE = $25.5B*

σ = $8.0B

Av. WFE = $32.4B**

σ = $3.0B

Av. WFE =

σ =

Internet of Things

Machine Learning

Autonomous Vehicles

Big Data

AR / VR

PC + Internet

Mobile +

Social Media

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IoT + AI Targeting Trillion-Dollar Opportunities

Industry 4.0 Digital

Health

Autonomous

Vehicles

Smart Grids

and Cities

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www

9

New Devices and

Applications Require

New Architectures

2000 2010 2016

PROCESSOR: ARM SOC

MEMORY: Stacked

STORAGE: NAND

DISPLAY: LTPS LCD

PROCESSOR: GPU / TPU / ASIC

MEMORY: Specialty

STORAGE: 3D NAND

DISPLAY: OLED

Artificial Intelligence

+ Visual Computing

PC + Internet

Mobile +

Social Media

PROCESSOR: X86 CPU

MEMORY: DIMM

STORAGE: HDD

DISPLAY: LCD

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Bigger Opportunities from Next Gen Architectures

SENSORS 3D NAND DISPLAYPROCESSORS + DRAM

Applied 2017 Equipment TAM >$57B

~$6B≥14nm

~$12B≤10nm

~$7B ~$13B~$2BAGS

200mm

>$17B

NVIDIA GV100 Volta GPUSamsung Exynos IoT Chip (28nm) EMC Unity All Flash Server using 3D NAND OLED screen of Samsung Galaxy S7

Applied

2017 TAM

* 2017 Estimated Total Available Market

*

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Rising WFE Intensity from Next Gen Architectures


SENSORS 3D NAND DISPLAYDRAM

28nm

~$9B

WFE

Intensity(100k WSPM,

Greenfield)

7nm

~$18B1Y

~$6B64L

~$6B

OLED

* WSPM = Wafer Starts Per Month

*

PROCESSORS

Processors ~3x more

WFE intensive

than memory

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Applied Enabling Next Gen Architectures



3D PatterningPatterning & New Materials

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Markets are

growing and playing

to our strengths

We are better

positioned than

ever before






Semi and display



We have a

platform for

sustainable growth

Broadest and

deepest capabilities

Inflection-focused

innovation strategy

Investment in new,

enabling products


repeatable success –Product Development

Engine


teams and execution

WHAT YOU’LL HEAR TODAY….

NEXT UP: Technology Masterclasses

Memory

Data explosion fueling demand for memory and logic

Applied enabling 3D NAND scaling to 144 pairs and beyond

2013 to 2017E:

► Our memory business growing at 2X rate of the market

► Memory share up 8 points

Patterning

A key enabler to extending the logic, foundry and memory roadmaps

Edge placement error is the key challenge to continued scaling

► Can only be solved with materials engineering

2012 to 2017E:

► Gaining ~16 points of patterning share in logic/foundry/DRAM

External Use


Memory Technology

and 3D ScalingRaman Achutharaman, PhD | VP and GM, Etch Business Unit, PPG

Sundeep Bajikar | Market Intelligence, PPG

Gill Lee | CTO, PPG

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Outline and Key Messages

PART 1

KEY MEMORY

MARKET DYNAMICS

Data explosion + architecture inflections towards Artificial

Intelligence fueling strong demand for memory (AND logic)

► Higher performance driving architecture innovations

► Lower costs driving data center inflection from HDD to SSD

PART 2

3D NAND ROADMAP

Advanced materials engineering uniquely enables

4 levers for 3D NAND scaling roadmap

PART 3

APPLIED’S

OPPORTUNITY

AND MOMENTUM

Strong share gains amplifying positive effect of secular

growth trends

► +8 points of total memory market share ’13 to ’17E1

► 47% revenue CAGR from ’13 to ’17E (2x market growth)2

15

1) CY13 based on Gartner, CY17 based on Applied estimates 2) Revenue CAGR on FY basis, market growth on CY basis

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PART 1

KEY MEMORY

MARKET DYNAMICS





PART 2

3D NAND ROADMAP



PART 3

APPLIED’S

OPPORTUNITY

AND MOMENTUM


growth trends





16

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MEMORY DEMAND: CONTEXT

Big Data and Artificial Intelligence can

transform entire industries – happening

faster than many people think

Explosion of data storage requirements

created by IoT, Big Data, AI and streaming

video has only just begun

Data generation from new categories can

potentially dwarf existing applications

within a few years

Source: The Economist, May 2017

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EXPLOSION OF DATAA city of 1M people will generate 200M GB of data per day by 2020

(SOURCE: CISCO, INTEL, WDC)

SMART BUILDINGS

55MGB/day

SMART FACTORIES

50MGB/day

PUBLIC SAFETY SYSTEMS

50MGB/day

SMART VEHICLES

40MGB/day

SMART AIRPLANES

4MGB/day

SOCIAL MEDIA+ OTHER

2MGB/day

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EXPLOSION OF DATAA city of 1M people will generate 200M GB of data per day by 2020

SMART BUILDINGS

55MGB/day

SMART FACTORIES

50MGB/day

PUBLIC SAFETY SYSTEMS

50MGB/day

SMART VEHICLES

40MGB/day

SMART AIRPLANES

4MGB/day

SOCIAL MEDIA+ OTHER

2MGB/day

(SOURCE: CISCO, INTEL, WDC)

19

IN CISCO’S MODEL…

Only 1% of data is

generated by humans

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“Mainstream Forecast” for Data Growth

-

1,000

2,000

3,000

4,000

5,000

6,000

7,000

2000 2003 2006 2009 2012 2015 2018E 2021E 2024E

Exa

byte

s (

EB

) p

er

Ye

ar

Internet

Data Traffic

Mobile

IOT / AI

69 76

146

1,392

24,940

1

10

100

1,000

10,000

100,000

GartnerIoT

Cisco VNIIoT

VLSIIoT

SmartCar

SmartFactory

20

20

Exa

byte

s (

EB

) p

er

Ye

ar

Source: VLSI Research, Cisco Source: Gartner, Cisco, VLSI Research, Applied Materials

1,400

25,000

IoT Forecasts for 2020

“What if?”

Scenarios

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y = 0.0081x1.3065

R² = 0.9563

-

5

10

15

20

25

- 100 200 300 400 500

DR

AM

Sh

ipm

en

ts (

EB

)

Incremental Data Generation (EB)

21

Data Generation to Memory Relationship | Historical

y = 0.0022x2.0399

R² = 0.9569

-

100

200

300

400

500

- 100 200 300 400 500

NA

ND

Sh

ipm

en

ts (

EB

)


DRAM NAND

Source: Cisco VNI, Cisco, Gartner, Factset, Applied Materials internal analysis

2006 to 2016 data from Cisco and Gartner. 2017 to 2020 projections from Cisco for data generation (VNI IP traffic), and industry average estimates for DRAM and NAND content shipments

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y = 0.0081x1.3065

R² = 0.9563

-

20

40

60

80

100

120

140

160

180

- 500 1,000 1,500 2,000 2,500

DR

AM

Sh

ipm

en

ts (

EB

)


1% adoption

of L4/L5

Smart Car

y = 0.0022x2.0399

R² = 0.9569

-

2,000

4,000

6,000

8,000

10,000

12,000

14,000

- 500 1,000 1,500 2,000 2,500

NA

ND

Sh

ipm

en

ts (

EB

)


1% adoption

of L4/L5

Smart Car

22

Projecting Future Memory Demand | One New Category

Source: Cisco VNI, Cisco, Gartner, Factset, Applied Materials internal analysis

2006 to 2016 data from Cisco and Gartner. 2017 to 2020 projections from Cisco for data generation (VNI IP traffic), and industry average estimates for DRAM and NAND content shipments

CONCLUSION: Data Explosion Drives Memory AND Logic

1%SMART CAR

ADOPTION

5X MORE DATA

8XMORE DRAM

IN 2020

1%SMART CAR

ADOPTION

5X MORE DATA

25XMORE NAND

IN 2020

DRAM NAND

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Architecture Inflection | More Efficient Use of Memory

Industry Average Server (Today)

Xeon

DRAM 176GB

DR

AM

DRAM

DR

AM

Host CPU456mm2 (per die)

~2x Higher Logic per Memory (mm2)Source: NVIDIA, Intel, Applied Materials Internal Analysis

Chip Type Die Size Total Size

8x Tesla V100 GPU 815mm2 x 8 6,520mm2

Intel Xeon E5 – v4 CPU 456mm2 x 2 912mm2

Total Logic 7,432mm2

GPU Memory DRAM 86mm2 (1GB) x 128 11,008mm2

CPU Memory DRAM 42mm2 (1GB) x 512 21,504mm2

Total Memory 32,512mm2

Logic / Memory: 23%

Chip Type Die Size Total Size

Intel Xeon E5 – v4 CPU 456mm2 x 2 912mm2

Total Logic 912mm2

CPU Memory DRAM 42mm2 (1GB) x 176 7,392mm2

Total Memory 7,392mm2

Logic / Memory: 12%

8x

4x

NVIDIA DGX-1 (AI / DL)

DR

AM

12

8 G

B

GPU

815 mm2 (per die)

Xeon

DRAM 512GB

DR

AM

DRAM

Host CPU456mm2 (per die)

PCI

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Memory Market Segmentation | Speed

Access time Scaled Access time Cost ($) per GB Scaled cost per GB

SRAM Cache(Embedded, Level 1)

Nanoseconds 1 second x xx

DRAM Cache(Embedded)

10-8 seconds 11 seconds x xx

DRAM DIMM 10-7 seconds 1.5 minutes ~6 6

SSD 10-5 seconds 3 hours ~0.3 3

HDD 10 milliseconds 4 weeks <0.1 1

NYC

Mexico

City

TRAVELING FROM

NYC to MEXICO CITY

at mach 1

on foot

Source: VLSI Research, Micron, Applied Materials

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Memory Market Segmentation | Speed and Cost

Access time Scaled Access time Cost ($) per GB Scaled cost per GB

SRAM Cache(Embedded, Level 1)

Nanoseconds 1 second 320 $1,000

DRAM Cache(Embedded)

10-8 seconds 11 seconds 80 $260

DRAM DIMM 10-7 seconds 1.5 minutes ~6 $20

SSD 10-5 seconds 3 hours ~0.3 $1

HDD 10 milliseconds 4 weeks <0.1 30¢


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Widening Memory Speed Gap | Creates new markets

10-10 10-9

Nanoseconds

10-8 10-7 10-6 10-5 10-4 10-3 0.01 0.1

2000

2010

2015

2017

2020

Embedded

SRAMDRAM HDD

Embd SRAMDRAM

Embd DRAMSDD

Embedded

SRAM DRAM SSDEmbedded

DRAM

Embedded

SRAMDRAM SSD

Embedded

DRAM

Embedded

SRAMDRAM SSD

Embedded

DRAM

Storage Class Memory

Milliseconds

HDD

HDD

HDD

HDD

ACCESS

SPEEDS


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SSD to HDD Cost Tipping Points

0

1

10

100

2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020 2022

SSD cross over

point with 15k HDD

SSD cross over

point with 10k HDD

SSD cost15k HDD costs

10k HDD costs

As 3D NAND costs

fall new applications

are opening up

15k + 10k drives

represent ~35% of

Enterprise HDD

shipments today

Source: Gartner, EMC, Applied Materials

EEE

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Cost of Ownership

Advantage Example:Applied’s Data

Center Storage

OLD

EMC VMAX40k

NEW

All Flash Array

ADVANTAGE

All Flash

Storage Array Model VAMX 40k EMC Unity All Flash All Flash

Disk Technology Spinning Disk 3D NAND (Samsung disks) 10-30x faster

10-15x denser

Usable Capacity / Effective Capacity 300TB / 300TB 250TB / 500TB (with deduplication) 66% more capacity

Floor Space 126 Rack Units

(3 full racks)

6U Rack Space

(1/7th of a Rack space)

95% less DC space

Heat Distribution (BTU) 41,200 2,600 93% less heat

Power Consumption (kVA) 12.97kVA 900VA 94% less power

Annual energy cost (Est) $31,776 $1,519 94% reduction

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PART 1

KEY MEMORY

MARKET DYNAMICS





PART 2

3D NAND ROADMAP



PART 3

APPLIED’S

OPPORTUNITY

AND MOMENTUM


growth trends





29

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3D NAND Schematic

Parallel to Wordline (WL)

Cell

Word Line

DecoderMemory

Cell

PERIPHERAL TRANSISTORS STAIRCASE MEMORY CELL

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3D NAND Schematic

Memory

Cell

STAIRCASE MEMORY CELL

Source: Images from ChipWorks

Word Line

Decoder

STAIRCASE MEMORY CELLPERIPHERAL TRANSISTORS

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3D NAND Roadmap

Node (pair) Stack Height (µm) Pair Thickness (nm) Key Structure Inflections

2015 32 / 36 ~2.5 ~70 CUA1

2016 48 ~3.5 ~62

2017 64 / 72 ~5 ~60 2 Tier, Staircase Opt.2

2018 >90 ~7 50~60 CUA, Cell Design3

2020 >120 >8 ~50

2021 >140 >9 45~50 >2 Tier, New Materials

Scaling

Methods MORE PAIRS MULTI-TIERS VERTICAL SCALING LATERAL SCALING

1) CUA: CMOS Under Array, 2) Staircase optimization for area saving, 3) Cell layout intensification

+

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MATERIALS-ENABLED SCALING

MULTI-TIERS

+

VERTICAL SCALING LATERAL SCALING

33

4 Levers for 3D NAND Scaling

MORE PAIRS

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MULTI-TIERS

+



34


MORE PAIRS

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Enabling More Pairs

More Pairs

Taller Structures

Need New Materials and Etch Technologies

Key Scaling Challenges Enabling Solutions

Structure integrityDisruptive new thinner hardmasks

(Precision CVD)Thick masks

Slanted profilesInnovative Etch technology

(Sym3)Elliptical holes

Top-to-bottom uniformity

Damage-free radical etch

(Selectra)Uniform horizontal removal

Deep clean capability

48 / 64

pairs

>90

pairs

hard

mask*

* Hardmask removed after pattern formation

hard

mask*

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Precision CVD

Innovative hardmask

material

High strength and

low stress hardmask

High selectivity

36

MORE PAIRS | Drive Need for New Hardmask MaterialsH

IGH

VA

LU

E P

RO

BL

EM

S

> 60 pairs

3.6µm 7.0µm 7.0µm

HM*

HM*

48pairs

New HM

>60% thinner

hardmask

enabling continued

3D NAND scaling

Increasing

hardmask

thickness

hinders

scaling

>90pairs

>90pairs

* Hardmask

AP

PL

IED

SO

LU

TIO

NS

DTOR at Advanced

3D NAND Nodes

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MORE PAIRS | Drive Need for New Etch Technology

Sym3

Ion energy / angle

control through

sync pulsing

High conductance for

by-product control

Symmetric design

for uniformity

HIG

H V

AL

UE

PR

OB

LE

MS

AP

PL

IED

SO

LU

TIO

NS

DTOR at Advanced

3D NAND Nodes

~30:1

HAR HM

Applied Internal data

No Bending, Circularity, Uniformity

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MORE PAIRS

38


MULTI-TIERS

+

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Multiple Tiers

More Pairs

39

Enabling Multi-Tiers Schemes

Need New Materials and Planarization Technologies


Top to bottom tier alignmentInnovative vertical etch technology

(Selectra)

Sacrificial layers and selective

removal of them

Damage-free radical etch

technology (Selectra)

Global planarityPrecise planarization technology

(Reflexion® LK Prime)

48 / 64

pairs

>90

pairs

1

2

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MULTI-TIERS | Selective Removal without Line of SightH

IGH

VA

LU

E P

RO

BL

EM

S

AP

PL

IED

SO

LU

TIO

NS Selectra SRP

Vertical and

horizontal removal

Zero energy /

radical assisted

Removal extreme

selectivity

Aligning of tiers drive requirement for

high selectivity removal

Selective sacrificial

layer removal

Selective Oxide /

Nitride/Si removal

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MULTI-TIERS | Precise Planarization is Key EnablerH

IGH

VA

LU

E P

RO

BL

EM

S

AP

PL

IED

SO

LU

TIO

NS Reflexion LK Prime

In-situ process control

for performance

14 processing stations

for productivity

Advanced pad conditioning

for cost control

Planarization for high incoming step

height (µm) at wide space (mm)

Gap Fill Thick Ox

CMP

~mm

>3µm

8

16 16

30

PlanarNAND

3D NAND>24P

3D NAND>40P

3D NAND>60P

Number of CMP Steps

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MULTI-TIERS

+

LATERAL SCALING


MORE PAIRS

42


VERTICAL SCALING

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Enabling Vertical Scaling

Need Materials Engineering Technologies


More uniform, lower stress,

denser layers

Higher plasma density CVD

(Precision CVD)

Higher quality layersHighly concentrated

radical oxidation (RadOx)

Standard

Scaled

for same number of pairs

Thinner layers

Shorter structures

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HIG

H V

AL

UE

PR

OB

LE

MS

AP

PL

IED

SO

LU

TIO

NS Precision CVD

Higher plasma density

with new plasma source

Low H content in films

44

VERTICAL SCALING | Enabling thinner ONON / OPOP

Stress control, uniformity,

productivity due to more stack

Thinner ON pair required

>90-stack

~7µm

More Layers

Taller Structures

0

50

100

150

CY2014 CY2015 CY2016

Gate Stack Installed Base

Ch

am

be

r

32-stack

2.5.µm

48-stack

3.6µm

64-stack

~5µm

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VERTICAL SCALING | Drives Need for Uniform OxidationH

IGH

VA

LU

E P

RO

BL

EM

S

AP

PL

IED

SO

LU

TIO

NS RadOx (RTP)

Higher-temperature

radical based oxidation

Multi-zone, closed-loop

temperature control

High-quality, high-uniformity (top to bottom)

oxide in high aspect ratio memory hole

High

quality

oxide48p >60p >90p

Customer A

Customer B

Customer C

Customer D

PTOR DTOR

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MULTI-TIERS

+

VERTICAL SCALING


MORE PAIRS

46


LATERAL SCALING

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Enabling Lateral Scaling

Need Innovative Etch and Materials Technologies


More efficient staircase formationInnovative etch technology

(Sym3)

CMOS under array structure

(CUA)

More etch resistant metal oxide

deposition technology (Olympia)

Area savings (~15%)

More cells / unit area

CUA Non CUA*

* CUA = CMOS Under Array

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What is Staircase Etch (Trim)?

Litho Etch LithoEtch Litho Etch

CONVENTIONAL PATTERNING

STAIRCASE

PATTERNING

Etch a Step

Trim Resist

Etch a Step

Trim Resist

Etch a Step

Strip Resist

Staircase patterning

reduces multiple

lithography steps

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HIG

H V

AL

UE

PR

OB

LE

MS

AP

PL

IED

SO

LU

TIO

NS

LATERAL SCALING | More Precise Staircase Formation

More pairs drive need for more steps on

staircase + ‘spiral staircase’ structure Precise, productive staircase formation required

area

savings

Sym3

Symmetric design

for uniformity

High conductance for

by-product control

Ion energy / angle control

through synch pulsing

48p >60p >90p

Customer A

Customer B

Customer C

Customer D

PTOR DTOR

49

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LATERAL SCALING | CMOS Under ArrayH

IGH

VA

LU

E P

RO

BL

EM

S

AP

PL

IED

SO

LU

TIO

NS

Protect CMOS under

cell from memory

cell etch process

Olympia ALD (Metal Oxide)

High dry etch selectivity

over oxide

Complete removal by wet

High productivity

Metal Oxide

Etch Stop Layer

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3D NAND Roadmap

Scaling

Methods MORE PAIRS MULTI-TIERS VERTICAL SCALING LATERAL SCALING

High Value

Problems

Highly selective hardmask Selective removal and

precise planarization

Higher quality layers of

NAND pairs

More efficient staircase and

CMOS under array structure

Applied

Products

Precision Hardmask

Sym3 Etch

Selectra Selective Removal

Reflexion LK Prime CMP

Precision ON / OP

RadOx

Sym3 Etch

Olympia ALD

+

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PART 1

KEY MEMORY

MARKET DYNAMICS





PART 2

3D NAND ROADMAP



PART 3

APPLIED’S

OPPORTUNITY

AND MOMENTUM


growth trends




52


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Memory Market Outlook | Strength + Upside

CY12 - CY15 CY16 CY17F

$35.2B

DRAM

Logic

Foundry

$30.3B$32.0B

NAND

>$40B

15 to

20%

30 to

35%

14%

9%

WFE by Device NAND WFE Scenarios

Expect Memory to Remain ~50% of WFE Spending

0

5

10

15

20

12 13 14 15 16 17 18 19 20 21

60% bit growth scenario

40% bit growth scenario

$B

Source: CY12 to 16 based on Gartner, CY17 based on Applied estimates. Device percentages are Applied estimates.

NAND WFE scenarios based on VLSI Research, Applied estimates.

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NAND Density ExpectationsC

hip

Den

sit

y

Time

1Gb

128Gb

256Gb512Gb

Chip density increase from

generation to generation is

slower for 3D than planarPlanar NAND

3D NAND

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Applied’s Growth and Momentum in Memory

Memory Revenue Growth1 Memory Revenue Mix Memory Share Gain2

FY13 FY17E FY13 FY17E

+27%

pts

NAND

DRAM

+47% CAGR

2X Market

Growth

~48%

21%

CY13 CY17E

+8pts

>22%

14%

1) Revenue CAGR on FY basis, market growth on CY basis, device estimates are Applied. 2) CY13 based on Gartner, CY17 based on Applied estimates

55

External Use


Disruptive Patterning for

Next Generation DevicesUday Mitra, PhD | Vice President, Etch Business Unit and Patterning Module

Regina Freed | Senior Director, Patterning Technology


| External Use59

Let’s Start with a Few Definitions….

patterning

1. process steps (including

deposition, etch, removal) that

create the template to define

the features of a device

2. typically not permanent films

3. excludes lithography

resolution

smallest feature

that can be printed

placement

act of positioning a

template in one location

relative to another

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Patterning market1

growing significantly,

even in most aggressive

EUV adoption case

Applied’s patterning

revenues240% YoY

Gained ~16 points

of share since 20123

Patterning is a key enabler to advance

logic / foundry and memory roadmaps

Litho-resolution gap has existed for

many generations and will continue

with EUV – addressed by materials

engineering / multi-patterning

Scaling increasingly limited by

edge placement error (EPE), not

resolution – addressed by materials


KEY MESSAGESIMPLICATIONS

1) Time period 2016 – 2020. CY16 Gartner, 17 – 20 Applied estimates. 2) Foundry, Logic and DRAM only, CY16 - CY17 estimate

3) Share is Foundry, Logic and DRAM only based on Gartner CY12 and Applied estimates for CY17

| External Use61

WHAT WE’LL COVER TODAY…

Patterning fundamentals

Addressing resolution limit with multi-patterning

New scaling challenge: Edge Placement Error

Patterning opportunity

Q&A

| External Use62

In the Past….

SCALING DELIVERED

Higher performance (smaller transistors and interconnects)

Lower power consumption (smaller transistors and interconnects)

Lower cost (more functionality per area)

N=2300 x 2^[0.5(y-1971)]

| External Use

LOGIC / FOUNDRY NAND DRAM

high n/a some

high high medium

to high

high n/a n/a

medium high medium

high some highMulti-patterning SADP

SADP + SAQP

SADP + SAQP + materials engineering

63

Today and in the Future | More Levers Required

Litho scaling 193

193 + 193i

193 + 193i + EUV

Advanced materials

and materials

modification

EXAMPLES:

Strained SiGe

High k metal gate

ZrO2 / Al2O3 / ZrO2

Design layouts Bidirectional Unidirectional

Device

architectures

MEMORY:

2D NAND 3D NAND

LOGIC / FOUNDRY:

2D FinFET Hyperscaling

CRITICALITY TO ROADMAP

TIM

E

| External Use64

What’s in a Name? (Or a Node…)

Physical Gate Lengthreduction driven by Logic

“Node” now = improvements in power, performance and area

Metal 1 Half-Pitchreduction driven by DRAM

350nm

10

100

1,000

500nm 350nm 250nm 180nm 130nm 90nm 65nm 45nm 32nm 22nm 14nm 10nm

Original “node” definition:

Gate Length or M1 Half Pitch

Design layouts start to

shift to unidirectional

At “32nm node”

Half-pitch = 52nm

| External Use65





Q&A


| External Use

Era of Materials-

Enabled Scaling

66

Litho Gap to Minimum Pitch Across Multiple Device Generations

Materials Innovations Bridged Litho Resolution Gap

for Last 4 Device Generations

Resolution Limit k𝜆

NA

193i Litho Etch 80nm

SADP 40nm

SAQP 20nm

EUV 25nm

l/N

A /

Min

imu

m C

D (

mic

ron

)

0.001

0.01

0.1

1

10

1980 1985 1990 1995 2000 2005 2010 2015 2020 2025

g-line

193 (dry)

DUV

EUV

193 (immersion)

i-line

LITHO GAP

0.18µm

90nm

45nm22nm

14nm

l/NA

min CD

| External Use67

Shift to Unidirectional | Design for Manufacturability and Yield

ADVANTAGES LIMITATIONS

Bidirectional

► Freedom for designers

► Potential to reduce die size,

total number of metal layers

► Expensive to scale beyond 80nm pitch

► Large edge placement error

► Litho tool-to-tool variation in X-Y

directions

Unidirectional

► Lower cost - less expensive

litho and process steps

► Better device performance

► Better patterning yield

► Enables hyperscaling

► Requires investment to convert from

bi-to unidirectional layout

► Additional non-litho process steps

| External Use68

Unidirectional Design Rules Drive 2 Discrete Processes

LINES / GRATING CUTS / VIAS

POTENTIAL

APPROACHESSpacer based patterning with 193i (SADP, SAQP)

Spacer based patterning with EUV (SADP)

EUV litho-etch

CHALLENGES Process uniformity

Deconvolution of yield limiters –

all process steps and co-interaction

POTENTIAL

APPROACHES193i multiple litho-etch

EUV litho-etch

CHALLENGES Edge placement error

Local variation / LCDU

| External Use

Building a 14nm Device

69

12 metal layers

11 via layers

Lower layers

use multi-

patterning

Upper layers

use older litho

ANIMATION

| External Use70

Self-Aligned Quadruple Patterning for Lines | State-of-the-Art

193i Litho

SADP | Double resolution by

1 spacer and 1 etch

SAQP | Quadruple resolution by

2 spacers and 2 etch

| External Use71

Self-Aligned Quadruple Patterning for Lines | State-of-the-Art

1 Litho

3 Etch

2 Spacers

2 HardmasksLines formed

in this layer

ANIMATION

| External Use

1

1

2 2

3

3

4

72

Multiple Litho-Etch for Cuts and Vias | State-of-the-Art

Repeat Litho-etch to Overcome Litho Resolution Limits

| External Use73

Multiple Litho-Etch for Cuts and Vias | State-of-the-Art

Repeat Litho-etch to Overcome Litho Resolution Limits

4 Litho

4 Etch

0 Spacers

4 Hardmasks

ANIMATION

| External Use74





Q&A


| External Use75

| External Use76

Most Critical Factor Limiting Scaling is Not Resolution…

Today’s chips have

up to 100B vias

Edge Placement Error (EPE)

is the movement of an edge

in any direction

Contributors are litho overlay

and process variation

Results in vertical misalignment

between layers

1 via off usually is

a dead chipPartial misalignment

impacts chip reliability

| External Use77

-5

0

5

10

15

020406080100

EP

E M

arg

in (

nm

)

Logic Device Node

193i

EUV

Zero margin line

Via/contact pitch (smaller)

32nm 22nm 14 10 7 5nm

Smaller node Smaller pitch Smaller resolution

EPE Margin for Multi-patterning Approaches

EPE increases with smaller nodes

Litho alignment error stack up

Process variation stack up

𝜎𝐸𝑃𝐸

=

𝑖=1→𝑚

(𝜎𝐿𝑖𝑡ℎ𝑜𝑖𝐸𝑃𝐸)2+

𝑗=1→𝑛

(𝜎𝐸𝑡𝑐ℎ𝑗𝐸𝑃𝐸)2+

𝑘=1→𝑜

(𝜎𝐷𝑒𝑝𝑘𝐸𝑃𝐸)2

EPE

Margincurrent

EPE

maximum

allowable EPE= –

Maximum

Allowable EPE = ¼ pitch

| External Use

Uniformity and conformality

Material quality of hardmask,

spacer, mandrel, gapfill

► Grain size

► Etch rate

► Roughness

► Composition

Stress

Overlay

CD uniformity

LER (photon dosing,

stochastics - issue for EUV)

78

Sources of Edge Placement Error

Mandrel profile

Limited selectivity for

spacer etch / mandrel removal

Microloading or dimensional

dependent etch

Local CD

LITHO ETCH DEPOSITION

| External Use79

Self-Aligned Double Patterning HIGH VALUE PROBLEMS

DESIGN Side View

HVPs Side View

DESIGN Top View

HVPsTop View

CD Nonuniformity Line Edge

Roughness

Overlay Necking

| External Use80

Addressing EPE from Etch Process Variations

Benchmark

20nm

Sym3

DEVICE LEVEL

WAFER LEVEL

Issues:

Profile

Depth loading

CD loading

Line edge roughness

Selectivity

Etch Process Variables:

Ion energy

Ion / neutral flux ratio

Reactive species formation

Issues:

Within wafer

uniformity

Wafer-to-wafer

repeatability

Etch Process Variables:

Plasma uniformity –

ion and radical distribution

Wafer temperature

Flow

Plasma / wall interaction

Sym3 Etch

Pulsed RF

Dual frequency bias

High conductance

Perfect symmetry:

RF, flow,

temperature

*

* Source: XXVIProc. of SPIE Vol. 8324 83241Y (2012). All other images Applied Materials internal

| External Use81

Addressing EPE from Deposition Process Variations

Benchmark AppliedDEVICE LEVEL

WAFER LEVEL

Issues:

Profile

Material quality

CD loading

Line edge roughness

Selectivity

Bending

Deposition Process Variables:

RF control and plasma

uniformity

Chemistry and film composition

Temperature

Stress / modulus

Issues:

Within wafer uniformity

Wafer-to-wafer

repeatability

Stress

Overlay

Deposition Process Variables:

Temperature uniformity

Plasma uniformity

Flow

Unique

Applied

Solutions

Broadest and

deepest film library

for etch and

integration needs

Reactor designed for:

Symmetric plasma, flow

Independent chamber-to-

chamber control

Precise multi-zone

temperature control

Low roughness

No bending

Uniformity

| External Use82

Addressing EPE through Materials Co-Optimization

EXAMPLE: SQUARE SPACER

Co-optimize film deposition

and etch process

Identify high quality films for

mandrel/spacer from broad

portfolio of materials and

techniques

Optimize etch for selectivity

and local uniformity control

CURRENT SQUARE SPACER

| External Use

DEVICE LEVEL

WAFER LEVEL

83

EBEAM INSPECTION Deconvolving Contribution to EPE

Benchmark PROVisionIssues:

Measure to <1nm

resolution

Measure on-device,

in-die

eBeam Design:

High electron density

Small spot size

Issues:

Slow measurement

Massive sampling

eBeam Design:

High beam current

High electron density

PROVision

1nm resolution

Real-time process

monitoring

Million samples

in 1 hour

| External Use

Multicolor Solution for Edge Placement Error

Materials-based approach eliminating

all sources of EPE

Multicolor = multiple materials

Enables 3D layout

New removal processes require

► Tunable selectivity

► Precision to 0.5nm

► No damage to surrounding materials

► Uniform removal

84

| External Use85




Q&A



| External Use86

All Layers in

Device Scale…

Some steps

will move to

SADP or

SAQP, some

to EUV

14nm 7nm

| External Use87

Sample Flow* 14nm 10nm 7nm

Fin SADP SAQP SAQP

Fin Cut 2 LE 4 LE 4 LE

Fin Via 2 LE 4 LE 4 LE

Gate SADP SADP SADP

Gate Cut 2 LE 2 LE 2 LE

Gate Via 2 LE 2 LE 2 LE

Metal 0 SADP SAQP SAQP

Metal 0 Cut 2 LE 4 LE 4 LE

Metal 0 Contact LE 4 LE 4 LE

Metal 0 Via LE 4 LE 4 LE

Metal 1 SADP SADP SAQP

Metal 1 Cut LE 2 LE 4 LE

Via 1 LE 2 LE 4 LE


Metal 2 Cut 2LE 2 LE 4 LE

Via 2 LE 2 LE 4 LE


Metal 3 Cut 2 LE 2 LE 4 LE

Via 3 LE 2 LE 4 LE

Metal 4 LE SADP SADP

Metal 4 Cut LE LE 2 LE

Via 4 LE 2 LE 2 LE



Via 5 LE 2 LE 2 LE

Metal 6 LE LE SADP

Metal 6 Cut NA N/A 2 LE

Via 6 LE LE 2 LE

Metal 7 LE LE LE

Metal 7 Cut N/A N/A LE

Via 7 LE LE LE

Metal 8 LE LE LE


Metal 8 Via LE LE LE


Fin SADP SAQP SAQP



Gate SADP SADP SADP




Metal 0 Cut 2 LE 4 LE EUV

Metal 0 Contact LE 4 LE EUV

Metal 0 Via LE 4 LE EUV

Metal 1 SADP SADP SADP

Metal 1 Cut LE 2 LE 4 LE

Via 1 LE 2 LE 4 LE


Metal 2 Cut 2LE 4 LE EUV

Via 2 LE 4 LE EUV



Via 3 LE 4 LE EUV



Via 4 LE 2 LE 2 LE



Via 5 LE 2 LE 2 LE

Metal 6 LE LE LE

Metal 6 Cut NA N/A LE

Via 6 LE LE LE

Metal 7 LE LE LE


Via 7 LE LE LE

Metal 8 LE LE LE


Metal 8 Via LE LE LE

Frequency of Patterning Technique

*Assumes 0.7 scaling

Maximum Mask Count Scenario

14nm 10nm 7nm

Litho Etch 18 8 6

2x Litho Etch 7 10 8


EUV Litho Etch 0 0 0

SADP 6 4 4

SAQP 0 4 5

Frequency of

Patterning Technique

Minimum Mask Count Scenario

14nm 10nm 7nm

Litho Etch 18 8 6


4x Litho Etch 0 5 3

EUV Litho Etch 0 0 8

SADP 6 4 4

SAQP 0 4 5

Frequency of

Patterning Technique


Fin SADP SAQP SAQP



Gate SADP SADP SADP





Metal 0 Contact LE 4 LE 4 LE

Metal 0 Via LE 4 LE EUV

Metal 1 SADP SADP SAQP

Metal 1 Cut LE 2 LE EUV

Via 1 LE 2 LE EUV


Metal 2 Cut 2LE 2 LE EUV

Via 2 LE 2 LE EUV



Via 3 LE 2 LE EUV



Via 4 LE 2 LE 2 LE



Via 5 LE 2 LE 2 LE

Metal 6 LE LE SADP

Metal 6 Cut NA N/A 2 LE

Via 6 LE LE 2 LE

Metal 7 LE LE LE


Via 7 LE LE LE

Metal 8 LE LE LE


Metal 8 Via LE LE LE14 nm 10 nm 7 nm

Litho

Etch

Dep

14 nm 10 nm 7 nm

Litho

Etch

Dep

EUV

| External Use88

Overall Market Segmentation

80% of Patterning Market Will Depend On Materials-Enabled Solutions

WFE (semi)

Architectural

ChangesScaling

Logic / Foundry

NAND(Architectural Changes)

DRAM(Scaling)

SCM(Architectural Changes)

Memory

MATERIALS-ENABLED SOLUTIONS

Advanced litho

solutions

Limited need for

advanced litho

| External Use

12 14 16 17E 20F

89

Growing Opportunity + Share Gains + Momentum

1.31.5

2.5

3.2

4.0 – 4.4

PATTERNING MARKET OPPORTUNITY* ($B)

12 14 16 17E 20F

<0.1

0.2

0.4

0.6

>1.4

APPLIED’S PATTERNING REVENUE ($B)

* Patterning market opportunity includes: Logic, Foundry and DRAM. Applied estimates

12 – 16 CAGR

19%

16 – 20 CAGR

12% to 15%

share

in 2012

<3%

share17%

share by 2020

“mid 30s”%

| External Use90

TECHNOLOGY APPLIED’S POSITION

CVD Leader

ALD High growth

PVD Leader

Etch Highest growth

SRP (Selectra) Leader

CMP Leader

eBeam Inspection Highest growth

Breadth of portfolio accelerates and

MAKES POSSIBLE new solutions

Innovative film

s,

rem

oval,

metr

olo

gy a

nd inspection

| External Use91

Patterning market1

growing significantly,

even in most aggressive

EUV adoption case

Applied’s patterning

revenues240% YoY

Gained ~16 points

of share since 20123

Patterning is a key enabler to advance

logic / foundry and memory roadmaps

Litho-resolution gap has existed for

many generations and will continue

with EUV – addressed by materials


Scaling increasingly limited by

edge placement error (EPE), not

resolution – addressed by materials


KEY MESSAGESIMPLICATIONS

1) Time period 2016 – 2020. CY16 Gartner, 17 – 20 Applied estimates. 2) Foundry, Logic and DRAM only, CY16 - CY17 estimate

3) Share is Foundry, Logic and DRAM only based on Gartner CY12 and Applied estimates for CY17

External Use


Investment in Innovative

ProductsBob Halliday | Chief Financial Officer


| External Use94

Innovation

Leadership

+ Win at

Inflections

Broad and deep

portfolio and

capabilities

Investments to

accelerate innovation

and growth

Operating model for

sustainable success

R&D investment* 40% in past 5 years

R&D* increased to ~70% of operating expenses

Winning team

“Product development engine”

Optimized cost structure

* Based on Non-GAAP adjusted R&D, plus Field Technical Support costs reported in SG&A.

For reconciliations of GAAP to adjusted Non-GAAP measures, see slides at the end of the presentation.

Leadership semi BUs + Services

High growth semi BUs

Display

| External Use95

What You’ve Heard So Far …



1. Emerging trends (IoT, Big Data, AI) are shifting value to semi and display

2. Materials Engineering / Applied’s technologies are critical to enabling roadmaps

3D ScalingPatterning & New Materials

| External Use96

Applied Benefits from Rising Capital Intensity

Planar 3D (64L) 25nm 14-16nm 28nm 7nm

FOUNDRYDRAMNAND

38%60%

87%

WFE ($B)Greenfield

100k WSPM

Based on Applied estimates. WSPM = Wafer Starts Per Month

~3xCapital Intensity

of Memory

| External Use

Applied’s Growth and Momentum in Memory

Memory Revenue Growth1 Memory Revenue Mix Memory Share Gain2

FY13 FY17E FY13 FY17E

+27%

pts

NAND

DRAM

+47% CAGR

2X Market

Growth

~48%

21%

CY13 CY17E

+8pts

>22%

14%

1) Revenue CAGR on FY basis, market growth on CY basis, device estimates are Applied. 2) CY13 based on Gartner, CY17 based on Applied estimates

97

| External Use98

Fueling Growth through Investment in Innovation

Allocated more spending to R&DR&D % of Opex 56% (FY’12) 66% (FY’16)

Focused R&D on most attractive marketsSemi + Display R&D3 up >50% (FY’12 – FY’17E)

Invested in disruptive products3X leverage in new disruptive products

Increased new product success rateby 66%

1) For reconciliations of GAAP to adjusted Non-GAAP measures, see slides at the end of the presentation

2) Field Technical Support costs are reported in SG&A

3) Includes, Semi + Display + Advanced Technologies

FY'12 FY'13 FY'14 FY'15 FY'16 FY17 LE

70% including

Field Technical Support2

$1.23B

(56%)(R&D%

of Opex)Non-GAAP1

$1.31B

(62%)

$1.42B

(64%)

$1.45B

(65%)

$1.54B

(66%)

R&DNon-GAAP1

| External Use99

Superior Growth and Very Strong, Diversified Positions

Leadership

Semi BUs

ServicesDisplay

& Other

FY 2016 Revenue Composition

FY13 - FY17E

Rev CAGR

Leadership Semi BUs (1) 14%

Services 10%

High-Growth Semi BUs (2) 27%

Display & Other 28%

Total Applied >17%

(1) Leadership Semi Products: Epitaxy, PVD, Implant, CMP, Thermal, ECD

(2) High-Growth Semi Products: CVD, Etch, Process Control, ALD

High-growth

Semi BUs

| External Use100

Leadership Semi: Strong Market Positions

ServicesDisplay

& Other

High-growth

Semi BUs

Very Strong and Growing Positions

Leadership

Semi BUs

PRODUCTS 2016 2017E

Epi 90%

PVD 74%

Implant 73% ~

CMP 66%

Thermal 50%

Source: 2016 based on Gartner. 2017 based on Applied estimates. All market share data is calendar year.

MARKET SHARE

| External Use101

High-Growth Semi: Superior Growth

Leadership

Semi BUs

ServicesDisplay

& Other

High-growth

Semi BUs

Growing up to 4X Faster Than

the High-Growth Market

Products

TAM

Growth

Applied

Revenue

Growth

Etch 89% 270%

CVD 70% 82%

PDC 6% 24%

2012 – 2016

Source: Gartner

ALD 2016 share

7pts y/y

EBI 2016 share

23pts y/y

Conductor

2016 share

5pts y/y

Sub-segment

| External Use102

GM Expansion through Execution

Gross Margin (Non-GAAP)*Shifted accountability to GMs

+More valuable products

+Operational improvements

=GM expansion in every

business unit since FY13

40.9%

42.1%

43.2%

46.0%

FY12 FY13 FY16 FY17E

~46%

* For reconciliations of GAAP to adjusted Non-GAAP measures, see slides at the end of the presentation

| External Use103

IN SUMMARY…

Markets are

growing and playing

to our strengths

We are better

positioned than

ever before






Semi and display



We have a

Platform for

sustainable growth

Broadest and deepest

capabilities

Inflection-focused

innovation strategy

Growing investment

in new, enabling

products


repeatable success –

Product Development

Engine


teams and execution

90% REVENUE +4% GM* POINTSFinancial Performance

FY’13 – FY’17E

* Non-GAAP adjusted gross margin

External Use


Innovation Leadershipand the Maydan Technology Center

Steve Ghanayem | Group Vice President and General Manager, TIG

| External Use

Operating Model for repeatable success

105

Key Messages

Innovation

Leadership

Increase Speed /

Learning Rates

Broad and Deep

Capabilities

Investment

Early Phase R&D

Technology Transition

Volume Ramp

CASE STUDIES

Operating Model

Product Development

Engine

Maydan Technology

Center

| External Use106

Portfolio Competitive Advantage

BROADEST

DE

EP

ES

T

RF PVD

MC PVD

DC PVD

Ionized PVD

Pulsed DC

PVD

Spatial ALD

Radical Enhanced ALD

ALD Funnel

Thermal CVD

Thermal CVD w Plasma

A B

METAL

CVD/ALD

Radical Enhanced Plasma

CCP Plasma

ICP Plasma

Chemical Clean

DRY

CLEANS

Standard

Dual Mode

DEGAS

CCP Etch

ICP Etch

Radical Enhanced

Mask Etch

ETCH

Next Gen RP Epi

RP Epi

ATM Epi

EPI

DualDamascene

Packaging Plating

PLATING

Spatial ALD

A B

ALD funnel

Thermal CVD

Radical Enhanced CVD

HD Plasma CVD

Plasma Enhanced CVD

DIELECTRIC

CVD/ALD

Mask Blank Cleans

CMP Pre-Clean

Brush Box

IPA MarangoniSRD

WET

CLEANS

Triple Platens

Dual Platen

POLISHING

Laser Anneal

ATM Thermal

Backside Thermal

Laser Anneal

UV Cure

ANNEALS

RP Thermal

Decoupled Plasma

NITRIDATION/

OXIDATION

Plasma Doping

Medium Current

High Current

High Energy

IMPLANT

eBeamReview

eBeamMetrology

eBeamInspection

Optical Mask Inspection

Optical Wafer Inspection

METROLOGY/

INSPECTION

| External Use107

Investment to Accelerate Innovations

MAYDAN TECHNOLOGY CENTER

APPLIED VENTURES

R&D INVESTMENTS*

$1.2B

2012 2017E

$1.5BTotal R&D

investment

40% since 2012

$300M invested in past 3 years

>$200M assets

under management

>30 active companies2016

>$1.7B

* Non-GAAP R&D. For reconciliations of GAAP to adjusted Non-GAAP measures, see slides at the end of the presentation.

| External Use

See inflections

early

108

Operating Model: How We Work With Customers

Develop

Differentiated

Valuable Sustainable

products

Customer engagement

► Early, deep collaboration

► Understand customers’

customer roadmap

Product development engine

► Define winning products

► Develop and release product

faster, better and at lower cost

Global customer support

► Device Performance and

Yield Services and Parts

► Output, yield and

cost optimization

Ensure

customer

success

Generate

residual

value

Identify customers’

High Value

Problems

| External Use109

Maydan Technology Center Plays Many Roles….

► Accelerating technology transfer from lab to pilot

► Accelerating new product development

► Accelerating new product introduction

► Supporting high volume ramp PRIMARY GOALS

Increase learning rate

Reduce cycles of learning

► Early phase R&D: Exploratory, n+2, n+1

See inflections

early

Develop

Differentiated

Valuable Sustainable

products

Ensure

customer

success

Generate

residual

value

Identify customers’

High Value

Problems

| External Use111

Leading edge capabilities

120 process tools

Advanced litho (193, 193i*, EUV*)

80 analytical and reliability tools

>100 leading-edge test vehicles

Best in class R&D cycle times

500 engineers with 24 / 7 operation

>2,000 integrated wafers / month

>750 electrical samples / month

>1,000 analytical samples / month

* through ‘Virtual Fab’ partnerships

| External Use

Applied MTC

Full

Device

Array

Electrical Testing

Integration

Process

Hardware Development

Materials R&D

112

What Makes Maydan Technology Center Unique?

Chemistry and new materials development lab

Fast HW customization for new materials and processes

Fast turnaround in process optimization

Flexibility to process new materials in the line

Short loops for customer-relevant electrical test vehicles

Parametric yield readiness – process control, uniformity

Not a focus today

STRENGTHS

LINKAGES

| External Use113

What Makes Maydan Technology Center Unique?

Applied MTC

Full

Device

Array

Electrical Testing

Integration

Process

Hardware Development

Materials R&D

Other

Equipment

Vendors

Industry

Consortia

Semiconductor

Manufacturers

| External Use

CASE STUDY:

CVD Cobalt (Co)New product life cycle: from idea to customer adoption

114

| External Use

In 2013…

115

How did it

play out?

| External Use

GOOD RELIABILITYAT INTERFACES

Selective Cobalt has

excellent adhesion to copper

and dielectric interfacesVOID FREEGAPFILL

Cobalt has superior

wetting property to

Copper films

116

Complete encapsulation of copper lines with

cobalt for ≤20nm interconnects

May 2014: CVD Cobalt Enables Interconnect Scaling

Cu

Co

Biggest material change to interconnects in 15 years + industry’s

first selective CVD metal system for high volume manufacturing

| External Use117

CVD Cobalt: Customer Adoption

2013 2015 2017E

Cumulative Count of CVD Cobalt Chambers

Became an industry-standard

metallization scheme,

adopted by all advanced

foundries

>$400M cumulative revenues*

>50

>200

~400

* Since launch

| External Use

CVD Cobalt Liners Improve Copper Fill

With CVD Cobalt LinerConventional Technology

Applied Materials 25nm opening trench, represents 20nm node feature

118

Lower Defects and More Robust Cu Fill with Co Liner

PVD Ta(N) + PVD Cu

Customer-relevant

structures and pitch

made in MTC

Demonstrate limits of

conventional technology

and enable development

of new solutions

| External Use

Module Level Integration

CVD Co showed good fill on coupons, many pits on full wafer

Conducted CMP studies to identify root cause

Slurry change solved the issue

PE CVD CoPVD Only

CMP

slurry

change

Without MTC full

suite of tools and

process integration,

customer may have

given up on Co liner

119

| External Use

4

22

No Cobalt With CVD Co

120

Selective CVD Cobalt Cap Improves Reliability

Selective CVD Cobalt immobilizes atoms on copper surface and improves copper-to-dielectric

adhesion resulting in reduction of electro-migration defects, improving overall performance

0.05

0.1

0.25

0.5

0.75

0.90.95

0.99

0.1 1.0 10.0 100.0 1000.0

Pro

ba

bil

ity

(%)

Electro-migration Failure Time (Hours)

MTC electrical test

vehicles showed

additional value,

especially for

foundry customers

Adhesion Energy

5X

Conventional

Technology

Precision Engineered

Selective CVD Co Cap

Better than 10X

Demonstrated

| External Use

Cross Over at ~10nm CD

Developing the Future – Cobalt Fill

Lower resistance from Cobalt metallization leads to increased device performance with

lower power requirements, allowing for continued scaling of lower interconnect levels

Less Scattering and Vertical Resistance for Cobalt Dual Damascene

0 10 20 30 40

Lin

e R

es

isti

vit

y (

uΩ

-cm

)

Trench CD (nm)

Applied Materials Internal Resistivity Benchmark

Cobalt Metallization Allows Scaling Below ~10nm CD

121

Co

Copper wires have

lower resistance

Cobalt

wires have

lower

resistance

Cu

| External Use

CASE STUDY:

STT MRAMModule level integration and customer collaboration

122

| External Use

Embedded STT (Spin Transfer Torque) MRAM

123

(Magnetic Tunnel Junction)

FL antiparallel

to RL high

resistance

(“1” state)

FL parallel

to RL low

resistance

(“0” state)

Seeing the Need, STT-MRAM Module was Developed at MTC

► High speed performance: read and write cycle 100ns or below

► High Endurance

► Low power CMOS logic compatibility

► Scalable

STT-MRAM is the best

candidate for embedded

nonvolatile memory

Standard LogicRead: ~0.1V

Write: 0.3 – 0.5V

Memory Element

Bottom Electrode

Top Electrode

Free Layer

Barrier Layer

Reference Layer

Seed Layer

Bit Line

Source

Line

Access NMOS

MTJ

| External Use

300mm STT MRAM Module at Maydan Tech Center

LK

CMP

Endura Multi-Cathode

MTJ PVD

Vacuum

Anneal

ASML

Scanner

Centura

New MTJ Etch, Liner

Producer

Dielectric

Applied

Tools

3rd Party

Tools

Centura

HM Etch

STT MRAM Module

Integrated STT-MRAM Module (structural and eTest) Developed to Drive HVM Product

124

Bottom Pad CMP

MTJ Pillar Litho

Hard Mask CVD

Oxide Fill

Oxide CMP

Multi-Cathode PVD MTJ

HM RIE Etch

MTJ Etch and passivation

| External Use

STT MRAM Module from Materials to Electrical Performance

TMR> 180% on 1Gb

Film Stack Array Parametric Yield

Enabled by the Breadth of Technologies and Testing Capabilities at MTC

125

Cell

20 nm

MgO

MgO

Ta

CoFeB/Ta/CoFeB

Ta/CoFeB

Co/Pt multilayer-based SAF

Bottom electrode/seed layer

5 nm

| External Use126

IEDM 2015 with Qualcomm:

“Pitch of 130 nm is smallest

reported by far for embedded STT-

MRAM applications, high device

performance and reliability achieved.”

| External Use

Customer Engagement Successful Demonstration of MRAM Stack for Memory and Foundry Customers

Customer Benefits

► Access to latest process and

material innovation

► Accelerated R&D learning

► Integration and early yield and

reliability optimization

127

Applied Benefits

► Accelerated learning

► Optimization of new materials, processes,

hardware

► Surpassing competition performance

► Opening the door for deep engagement

with customers

► Stepping stone for new emerging market

| External Use

Takeaway

Messages

Maydan Technology Center a unique asset for Applied and

the industry – built upon >20 years of experience

Center supports Applied’s Innovation Leadership and is

focused on collaboration and increasing learning rates

Next generation technologies driving need for faster cycles of

learning that link device, process, hardware, and materials

Maydan Center supports rapid optimization of complex

technologies across Applied’s broad product portfolio

Center opens up new ways of working with our customers

128

“Makes possible

new devices and

new ways of

building devices”

| External Use132

(In millions) Oct 30, 2016 Oct 27, 2013 Oct 28, 2012

Non-GAAP Adjusted Gross Profit

Reported gross profit - GAAP basis 4,511$ 2,991$ 3,313$

Certain items associated with acquisitions1

167 166 253

Acquisition integration and deal costs2

- 3 -

Inventory charges (reversals) related to restructuring3

(2) - -

Other significant gains, losses or charges, net - - -

Non-GAAP adjusted gross profit 4,676$ 3,160$ 3,566$

Non-GAAP adjusted gross margin 43.2% 42.1% 40.9%

3 Results for fiscal 2016 primarily included benefit from sales of solar equipment tools for which inventory had been previously reserved

related to the cost reductions in the solar business.

APPLIED MATERIALS, INC.

UNAUDITED RECONCILIATION OF GAAP TO NON-GAAP GROSS PROFIT

Twelve Months Ended

1 These items are incremental charges attributable to completed acquisitions, consisting of amortization of purchased intangible assets.

2 These items are incremental charges related to the terminated business combination agreement with Tokyo Electron Limited, consisting

of acquisition related and integrateion planning costs.

| External Use133

(In millions) Oct 30, 2016 Oct 25, 2015 Oct 26, 2014 Oct 27, 2013 Oct 28, 2012

RD&E expenses (GAAP basis) 1,540$ 1,451$ 1,428$ 1,320$ 1,237$


- - (1) (3) (4)

Acquisition integration costs - (1) (3) (6) (3)

Certain items associated with terminated business combination2

- - (1) - -

Other significant gains, losses or charges, net5

- 2 - - -

Non-GAAP adjusted RD&E expenses 1,540$ 1,452$ 1,423$ 1,311$ 1,230$

Operating expenses (GAAP basis) 2,359$ 2,259$ 2,323$ 2,559$ 2,902$


(21) (23) (25) (35) (45)

Acquisition integration and deal costs (2) (2) (33) (35) (81)

Impairment of goodwill and intangible assets - - - (278) (421)

Restructuring charges (reversals) and asset impairments3

1 (14) (5) (63) (168)

Gain (loss) on derivatives associated with terminated business combination, net - 89 30 (7) -

Certain items associated with terminated business combination2

- (50) (73) (17) -

Other significant gains, losses or charges, net4, 5

(8) (8) 4 4 -

Non-GAAP adjusted operating expenses 2,329$ 2,251$ 2,221$ 2,128$ 2,187$

RD&E expense as a percentage of operating expenses 65.3% 64.2% 61.5% 51.6% 42.6%

Non-GAAP adjusted RD&E expenses as a percentage of operating expenses 66.1% 64.5% 64.1% 61.6% 56.2%

4 Results for fiscal 2016 included a loss of $8 million due to discontinuance of cash flow hedges that were probable not to occur by the end of the originally specified time period.

5 Results for fiscal 2015 included immaterial correction of errors related to prior periods, partially offset by costs related to executive termination.

APPLIED MATERIALS, INC.

UNAUDITED RECONCILIATION OF GAAP TO NON-GAAP ADJUSTED RD&E AND OPERATING EXPENSES

Twelve Months Ended

1 These items are incremental charges attributable to completed acquisitions, consisting of amortization of purchased intangible assets.

2 These items are incremental charges related to the terminated business combination agreement with Tokyo Electron Limited, consisting of acquisition-related and integration planning costs.

3 Results for fiscal 2012 included employee-related costs of $106 million related to the restructuring program announced on October 3, 2012, restructuring and asset impairment charges of

$48 million related to the estructuring program announced on May 10, 2012, and severance charges of $14 million related to the integration of Varian.

presentation title goes here - applied materials · 2017-07-11 · samsung exynos iot chip (28nm)...

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