Presenter : Ching-Hua Huang

2013/9/16

Visibility Enhancement for Silicon DebugCited count : 62

Yu-Chin Hsu;  Furshing Tsai; Wells Jong; Ying-Tsai ChangNovas Software, San Jose, CA Design Automation Conference (DAC), 2006 43rd ACM/IEEE

National Sun Yat-sen University

Embedded System Laboratory

Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require the instrumentation of on-chip logic for extracting the internal register data from in situ silicon. Unfortunately, lack of visibility of the combinational network values impedes the ability to functionally debug the silicon part.

Visibility enhancement techniques enable the virtual observation of combinational nodes with minimal computational overhead. These techniques also cover the register selection analysis for DFD and multi-level design abstraction correlation for viewing values at the register transfer level (RTL).

Abstract

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Experimental results show that visibility enhancement techniques can leverage a small amount of extracted data to provide a high amount of computed combinational signal data. Visibility enhancement provides the needed connection between data obtained from the DFD logic and HDL simulation-related debug systems.

Abstract (Cont.)

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Introduction

The process of IC designs can be broken into two stages

Key factors which make silicon debug difficult include: Limited silicon signal data visibility Silicon errors may either be functional bugs or physical defects Silicon debug data is usually associated with a gate-level netlist

|--------First stage------||----Second stage---|

Decreasing Increasing

Introduction (Cont.)

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Manufacturing Test To check the physical defects Based on DFT and ATPG

System Validation To ensure the silicon operates according to specification Based on DFD logic

。Many DFD implementations leverage DFT circuitry.。DFD is the access mechanism that provides in-situ scan register

visibility Data to Debug Flow

Scancontrol

Combinationallogic

Combinationallogic

DFTDFT

DFDDFD

Real-timeclock &reset

control

What’s the problem

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Finding and analyzing the problems in silicon is dreadfully tedious and time consuming. DFD provide very limited signal access and visibility into a device. DFT allows observation of states in scan chain, but it is still limited by

only the register signals.

The data extracted from device is usually mapped to gate-level netlist. Designers normally implement the design at the behavioral- level.

This paper propose a methodology to resolve the above issues.

Related Work

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[1] [2] User Wants and

Needs

The time required to move from prototype to volume production is increasing

This paper:Visibility Enhancement for Silicon Debug

[5] DFT and ATPG

A common methodology utilized in approximately 82% of designs

[8] DFD

[4][16] More sophisticatedDFD methodologies

[17] A Reconfigurable Design-for-Debug

Infrastructure

Add internal monitoring and breakpoints

Extract values to be observedduring run real-time observation

Around five percent of all designs contain some type of DFD

Proposed method

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Proposed method This methodology includes three main steps:

Essential Signal Analysis: 。Analyze design (RTL, gate) and provide optimal

(minimal and sufficient) set of signals to be observed

Data expansion: 。Using the knowledge of the design function to

computes the missing data. Gate-to-RTL Correlation:

。Map the gate level signals back to RTL

Essential Signal Analysis

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ESA starts by inferring the HDL description ◦ It recursively traverses inferred logic netlist, analyzes the

logic equations for each functional block.

The ESA technology can also be applied in regression simulation.◦ For regression simulation

1.ESA analyzes the RTL or netlist code to find the storage elements, memory elements, and the primary inputs.

2.Only dumping the essential signals 3.Full visibility can be achieved using the data expansion

technology◦ The regression simulation methodology can reduce the total

simulation times for debug.

Data expansion

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To obtain the maximal visibility of a device.◦ The quality of essential signal analysis is closely related to

the capability of data expansion.

Translate Data for the HDL Domain◦ The captured data must be translate to properly format for

debugging tools◦ There are a number of steps to this process:

Temporal transformation Correlate time or cycle to the captured data from silicon world to virtual

world Signal mapping

The data must be associated with the signal names in the HDL design Format transformation

The data is made available in standard VCD format or Novas FSDB format

Data expansion (Cont.)

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Expand Captured Data◦ Computes the missing data by using the knowledge of the

design function.

There are two primary differences with the simulation◦ Data expansion where only the needed value will be

computed is a must for users.◦ The time-processing is not necessary.

Data expansion

Data expansion

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Cycle N Cycle N+1 Cycle N Cycle N+1

Gate-to-RTL Correlation

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In general, Silicon signal data is usually easy to assign to gate-level signals

Gate-level netlist and values are difficult for RTL designers to understand and debug◦ One-to-one correspondence is not always the case after

synthesis transformations

Correlation

0100101110010110 11010110001101101000011111000000

Correlation

Gate-level

RTL

Silicon extracted easy difficult

Before the experiment…

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Essential Signal Analysis How many Percentage of signals can reach the full

visibilty ? As described in ESA, the regression simulation can

reduce the total simulation times ?

Gate-to-RTL Correlation If synthesized an RTL design into gates both with and

without preserving hierarchy. Is this difference will effect our debug ?

Essential signal analysis technology

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Working scope

# of signals

# of essential signals

% of signals

Case 1 138842 13190 9.5%

Case 2 6808801 992248 14.6%

Case 3 4568074 173544 3.8%

Case 1 Case 2

Simulation time

FSDB filesize

Simulationtime

FSDB file size

Full dump

506 sec. 290 MB 6 hr. 39 min.

2.1 GB

No dump 132 sec. N/A 2 hr. 12 min.

N/A

ES dump 174 sec. 25 MB 2 hr. 29 min.

61.7 MB

Effectiveness of essential signal analysis technology

The regression simulation can reduce the total simulation

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Gate to RTL correlation Effectiveness of the gate to RTL correlation technology

Count Percentage

Total 990

Can be mapped 207 21%

1 statement 684 69%

2-3 statements 54 5.4%

More than 3 statements 21 2.1%

Other (floating, scan chain …)

24 2.5%

Count Percentage

Total 952

Can be mapped 180 19%

1 statement 307 32%

2-3 statements 194 20%

More than 3 statements 213 22%

Other (floating, scan chain …)

58 6%

With preserving hierarchy

Without preserving hierarchy

It is useful for silicon debug.

It will make the silicon debug difficultly.

Conclusions and My comments

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Conclusions These technologies provide the ability to

。Analyze the essential signals 。Expand the captured data 。Correlation to present gate-level data at the RTL

This experiments show 。The proposed technology is effective。It greatly enhance the comprehension of silicon prototype

operation

My comments This paper was cited from many papers which proposed the

approaches of silicon debug. It discuss about the Gate-to-RTL Correlation

。Some issues are similar with my work.