presenters: genady paikin, ariel tsror. supervisors : inna rivkin, rolf hilgendorf. high speed...
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Presenters:Genady Paikin, Ariel Tsror.
Supervisors : Inna Rivkin, Rolf Hilgendorf.
High Speed Digital Systems Lab
Yearly ProjectPart A
Sub-Nyquist Sampling Algorithm Implementation on Flex Rio
Mid Presentation
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Agenda: Project overviewGoalsHardwareLearning ProcessSampling stageCTF moduleDSP moduleSCD moduleLearning LabViewAdjusting Xlinx Chipscope to NI's FlexRioDSP module FormationGantt Chart
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Project OverviewThe project is part of the Sub-
Nyquist sampling and reconstruction card.
Our goal is to implement 2 units – CTF & DSP, on FlexRio FPGA cards under NI LabView environment.
The unit also includes the Xampling sampling card And the Expand unit.
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Hardware: NI chassis with 4* FlexRio FPGA modules
◦FlexRio : Model : NI PXIe 7965R Bus : PXI Express FPGA : Virtex-5 SX95T (Xilinx) FPGA memory : 8,784 Kbits Onboard Memory : 512MB FPGA Slices : 14,720 FPGA DSP Slices : 640
A/D.Xampling sampling card.
* Expand, DSP, CTF, Reconstruction
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Learning Process: Learning process composed of 2
independent processes :◦Algorithm :
System main concept. Sampling stage (Xampling and Expand). CTF module. DSP module (inc. SCD).
◦LabView : LabView main concepts. FPGA under LabView. Integration. Implementing Basic unit as training.
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High Level Architecture:
Xampling
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NI Chassis
FlexRio – Expand
FlexRio – CTF
FlexRio – DSP+SCD
FlexRio – Analog Back-End
4 X A/D
Signal Generat
or
MWC / Xamping
HostPXIe
LVDS300 MB/s
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Sampling stage: The sampling stage contain two
units ◦Xampling sampling card.◦Expand.
Expand
1:3
Analog in
4X62.5 Mhzdigital
12X20.8 Mhzdigital
A/D62.5 Mhz(250 1:4 decim.)
Xampling
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CTF module: Task : Detects the Support of x(t)
and forward it to DSP unit.Triggered at :
◦Initiation.◦SCD interrupt.
The unit based on OMP (Orthogonal Matching Pursuit) algorithm.
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Block Diagram:
A
Qframe
calculation
MPy[n]
A
Supp
0
:fN
HQ
n
frame n n
Q y y AU
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DSP module: Task: Reconstructs the signal from the
samples. The unit receives the samples from the
memory (latency fifo), matrix A from the memory, and signal support from the CTF unit.
The support and samples are coordinated by the latency fifo.
The unit performs pseudo-inverse of matrix A (calculates As) using the signal support, that is received from the CTF. The inverse is done by QR Decomposition algorithm.
Finally the unit multiply the delayed signal with matrix As.
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DSP module: DSP
Pseudo Inverse
Multiplication
Signal’s sample (from
memory)
Matrix A (from memory)
Signal support(from CTF)
Reconstructedsignal
As+
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SCD module: Task: Detects if there is a change
of the signal support.The unit uses the signal energy
to decide if the CTF needs to recalculate the signal support.
Support Change Detector
Signal’s sample (from
expand)
Recalculate support (to CTF)
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Learning LabView:
Basic level ◦ We ran a simple application using LabView basic
tools.
VHDL in LabView◦ We added a simple VHDL component using IP
integration node.◦ We added a simple VHDL component
using Component-Level IP (FPGA Module).
We used "host VI" to open "target VI“ We used FPGA methods from the host.
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Adjusting Xlinx Chipscope to NI's FlexRio:
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Adjusting Xlinx Chipscope to NI's FlexRio:We created chipscope component
using Xilinx core generator (ILA, ICON).
We generated CLIP+xml file using CLIP node xml generator.
We defined chipscope component as CLIP node.
We connected manually JTAG cable to fit NI 5781 digital outputs/inputs (PFI).
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Adjusting Xlinx Chipscope to NI's FlexRio:We connected the chipscope
component with the basic VHDL component that we had created earlier on FPGA target.
We connected the required outputs/inputs of the chipscope component with the PFIs.
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Adjusting Xlinx Chipscope to NI's FlexRio:
Problems:◦We tried to run whole things together,
however the chipscope analyzer couldn't recognize the device.
◦There are no tutorials on this theme except the one we used, and it isn’t compatible with Xilinx or LabView versions that exist in the lab.
Ways to solve it:◦We wait for official answer from NI.
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Adjusting Xlinx Chipscope to NI's FlexRio: Target VI Implementation
IP integration node
Component Level IP (CLIP)
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Adjusting Xlinx Chipscope to NI's FlexRio: Host VI Implementation
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Multi-Clock Domain:
Creating example with different clock rates in the same design.
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DSP module Formation:Steps:
◦Learning previous implementation.◦Coding blocks with VHDL. ◦Creating needed blocks in COREGEN.◦Debugging blocks with Model Sim.◦Importing VHDL components into
LabView.◦Assembling the whole module in
LabView.◦Debugging the module on the FPGA.
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Gantt:
1.2 Learning x ampling card 09/03/11 22/03/11 14 100% 10 14 0
1.3 Learning ex pand unit 18/03/11 07/04/11 21 100% 15 21 0
1.4 Learning CTF unit 18/03/11 07/04/11 21 100% 15 21 0
1.5 Learning DSP unit 18/03/11 07/04/11 21 100% 15 21 0
1.6 Learning SCD unit 18/03/11 07/04/11 21 100% 15 21 0
2 Learning LabView 23/03/11 06/05/11 45 100% 33 45 0
2.1 Basic lev el 23/03/11 12/04/11 21 100% 15 21 0
2.2 VHDL in LabView 07/04/11 06/05/11 30 100% 22 30 0
3
Adjusting Xlinx Chipscope to
NI FlexRio 07/05/11 14/06/11 39 60% 27 23 16
3.1 Creating 07/05/11 24/05/11 18 100% 12 18 0
3.2 Debuging 25/05/11 14/06/11 21 25% 15 5 16
4 Exams' Period 15/06/11 22/07/11 38 0% 28 0 38
4.1 Ex ams' Period 15/06/11 22/07/11 38 0% 28 0 38
5 Multi Clock Example 23/07/11 05/08/11 14 0% 10 0 14
5.1 Multi Clock Ex ample 23/07/11 05/08/11 14 0% 10 0 14
6 DSP Unit 06/08/11 16/11/11 103 0% 73 0 103
6.1 Prev ious Code Rev iew 06/08/11 19/08/11 14 0% 10 0 14
6.2 Coding Blocks 19/08/11 08/09/11 21 0% 15 0 21
6.3 Debuging Blocks 01/09/11 21/09/11 21 0% 15 0 21
6.4 Creating Vis 22/09/11 12/10/11 21 0% 15 0 21
6.5 Debuging All 13/10/11 16/11/11 35 0% 25 0 35