prm™ regulator - vicor corporationcdn.vicorpower.com/documents/datasheets/prm48b_4… · ·...

Rev. 1.2

07 / 2012 of 22

PRM48BF480T400A00 (Formerly VIP0001TFJ)

V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200

PRM™

Regulator

FEATURES DESCRIPTION 45 V (38 to 55), non-isolated ZVS buck-boost regulator 5 to 55 V adjustable output range Building block for high efficiency DC-DC systems 400W output power in 1.1 in2 footprint 97% typical efficiency, at full load 1,360 W/in3 (83 W/cm3) Power Density Enables a 48 V to 1.5 V, 230 A isolated, regulated

solution with total footprint of 3.3 in2 (21 cm2) Flexible “Remote Sense” architecture optimizes

regulation / feedback loop design to fit application requirements

Current feedback signal allows dynamic adjustment of current limit setpoint

3.61 MHrs MTBF (MIL-HDBK-217Plus Parts Count) TYPICAL APPLICATIONS High Efficiency Server Processor and Memory Power High Density ATE System DC-DC Power Telecom NPU and ASIC Core Power LED Drivers High Density Power Supply DC-DC Rail Outputs Non-isolated Power Converters

The V•I Chip™ PRM™ Regulator is a high efficiency converter, operating from a 38 to 55 Vdc input to generate a regulated 5 to 55 Vdc output. The ZVS buck – boost topology enables high switching frequency (~1 MHz) operation with high conversion efficiency. High switching frequency reduces the size of reactive components enabling power density up to 1,360 W/in3. The full V•I Chip package is compatible with standard pick-and-place and surface mount assembly processes with a planar thermal interface area and superior thermal conductivity. In a Factorized Power Architecture™ system, the PRM48BF480T400A00 and downstream VTM™ current multiplier minimize distribution and conversion losses in a high power solution. An external control loop and current sensor maintain regulation and enable flexibility both in the design of voltage and current compensation loops to control of output voltages and currents.

PRPC TM

+IN

-INIF RE SG VC

-OUT

+OUT

Load

38 to 55Vdc Input

CurrentSense

Enable/Disable

Feedback

VoltageReference

VoltageControl

PC

+IN

-INVC

+OUT1+OUT2

-OUT1-OUT2

PC

+IN

-INVC

+OUT1+OUT2

-OUT1-OUT2

Constant Vc

48 V to 1.5 V, 230A Voltage Regulator

PRMTM Regulator VTMTM Current

Multiplier

VTMTM Current Multiplier

Not Recommended for New Designs

Rev. 1.2

07 / 2012 of 22



1.0 ABSOLUTE MAXIMUM RATINGS The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. All voltages are specified relative to SG unless otherwise noted. Positive pin current represents current flowing out of the pin.

Min Max Unit-0.3 10.5 V

±10 mA-0.3 5.7 V

±10 mA-0.3 5.7 V

±1 mA-1 62 V

-0.5 10.5 V±100 mA±100 mA

-0.5 5.7 V-0.3 5 V-0.5 18 V

±1.8 A-1 62 V

±11 A-40 125 ºC-40 125 ºC

+IN to –IN

………………………………………………………………………..VC to –OUT

……………………………………………………………………………

……………………………………………………………………………

……………………………………………………………………………

…………………………………………………………………………………………………………………………………………………………IF

+OUT to –OUT

VS

RE

……………………………………………………………………………

SG

PR

PC

TM ………………………………………………………………………..

………………………………………………………………………..

………………………………………………………………………..

……………………………………………………………………………

………………………………………………………………………..

Operating Analog IC Junction TemperatureStorage Temperature ……………………………………………………………………………

Output Current

2.0 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and output voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade). Attribute Symbol Min Typ Max Unit

POWER INPUT SPECIFICATION

Input Voltage Range VIN 38 45 55 VVIN Slew Rate dVIN/dt 0.001 1000 V/msNo Load Power Dissipation PNL 2.4 4 WInput Quiescent Current IQC 4.5 8.5 mAInput Current IIN DC 10.9 11.0 AInput Capacitance (Internal) CIN INT 4 FInput Capacitance (Internal) ESR RCin 1.5 mΩ

POWER OUTPUT SPECIFICATION

Output Voltage Range VOUT 5 48 55 VOutput Current IOUT 8.33 AOutput Power POUT 400 W

±10 %

±24 %

±35 %

96.5 97.4 %94.8 %90.0 %

Output Discharge current IOD 13 mAOutput Voltage Ripple VOUT PP 960 1500 mVOutput Inductance (Parasitic) LOUT PAR 1.9 nHOutput Capacitance (Internal) COUT INT 4 FOutput Capacitance (Internal) ESR RCout 1.5 mΩ

POWERTRAIN PROTECTIONS

Input Undervoltage Turn-ON VIN UVLO+ 35.75 37.13 VInput Undervoltage Turn-OFF VIN UVLO- 31.97 33.56 VInput Overvoltage Turn-ON VIN OVLO+ 55.91 57.24 VInput Overvoltage Turn-OFF VIN OVLO- 58.44 59.91 VOvercurrent (IF) and Input Over/Undervoltage Blanking Time

TBLNK 50 120 150 s

Output Overvoltage Threshold VOUT OVLO+ 55.25 56.57 59.04 VThermal Shutdown Setpoint TJ OTP 130 ºCOvertemperature, Output Overvoltage and PC Shutdown Response Time

TPROT 2 s

Short Circuit Vout Threshold VSC VOUT 3.0 VShort Circuit Vout Recovery Threshold VSC VOUTR 4.0 VShort Circuit Vpr Threshold VSC VPR 7.2 VShort Circuit Vpr Recovery Threshold VSC VPRR 7.1 VShort Circuit Timeout TSC 20 msShort Circuit Recovery Time TSCR 0.1 msOutput Power Limit PPROT 400 W

Conditions / Notes

Output Turn-ON Delay

>50% load; over temperature

Equal input, output and PR voltage at full load;Over line and trim, with 25°C < TC < 100°C but negligible part-part temp mismatch

See Fig.16, SOASee Fig.16, SOA

0 < VIN < 18 VPC HIGH, VIN = 45 V

Instantanous powertrain shutdown, latched after TBLNK

Instantanous powertrain shutdown, latched after TBLNK

Short circuit fault latched after VSC_VOUT and VSC_VPR thresholds persist for this time

Effective value, VIN = 45 V (see Fig. 20)

From VIN applied, PC floating

PC LOW, VIN = 45 VIOUT = 8.33A, VIN = 38 V, VOUT = 48 V

s

Frequency @ 1 MHz, Simulated J-Lead modelCOUT_EXT = 0 F, IOUT = 8.33 A, VIN = 45 V, VOUT = 48 V, 20 MHz BW

20From PC pin release, VIN applied, TOFF expired

Effective value, VOUT = 48 V (see Fig. 20)

Nominal line, full load, VOUT = 48V

TON

50% load and VOUT = 48 V; over temperature

Section 4.0

Current Sharing Difference(exclusive of current limit)

IOUT_SHARE

Equal input, output and PR voltage at full load;VIN = 45 V, VOUT = 48 V

Equal input, output and PR voltage at full load;Over line and trim, with 25°C < TC < 100°C and <= 75°C part-part temp. mismatch (worst case)

Efficiency

Instantaneous, latched shutdownInstantaneous, latched shutdown; guaranteed by design, not production tested; VTM = 4.03V

η


Rev. 1.2

07 / 2012 of 22



3.0 SIGNAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade). Primary Control PC

Signal Type State Attribute Symbol Conditions / Notes Min Typ Max UnitPC Voltage VPC 4.7 5 5.3 V

PC Available Current IPC_OP 1.8 mA

PC Source Current IPC_EN After TOFF 90 A

Minimum Time to Start TOFF Section 5.0 10.0 18.0 30.0 msStartup PC Enable Threshold VPC_EN 2.50 3.20 V

PC Disable Threshold VPC_DIS 1.75 2.40 VPC Resistance (External) RPC_EXT Resistance to SG required to disable the PRM 300 Ω

Digital Output [Short Circuit Fault] Fault PC Sink Current to SG IPC_SC Short circuit, PC voltage 1 V or above 25 mADigital Output [All other Faults] Fault PC Sink Current to ~1V IPC_FAULT Tempature, over- and undervoltage, overcurrent 10

• The PC pin enables and disables the PRM• In PRM array configurations, PC pins should be connected in order to synchronize startup.• It is a weak pull-down during any fault mode excluding short circuit. PC is a strong pull-down to SG if a short circuit fault is latched.

RegularOperation

Standby

Startup

Analog Output

Digital Input / Output

Voltage Source VS

Signal Type State Attribute Symbol Conditions / Notes Min Typ Max UnitVS Voltage VVS 8.55 9.00 9.45 VVS Available Current IVS 5 mA

VS Voltage Ripple VVS_PPIout = 0A, Cvs_ext=0. Maximum specification includes powertrain operation in burst mode.

100 400 mV

VS Capacitance (External) CVS_EXT 0.04 FVS Fault Response Time TFR_VS From fault recognition to VS = 1.5 V 30 s

RegularOperation

Analog Output

• Intended to power feedback components and/or auxiliary circuits.• 9 V, 5mA regulated voltage source• With > 5% output load, VS ripple typically 100mV

Transition

Reference Enable RE

Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit

RE Voltage VRE 3.0 3.3 3.6 V

RE Available Current IRE 8.0 mARE Regulation %RE across load and temperature 2.5 %RE Voltage Ripple VRE_PP in burst mode 100 mVPC to RE Delay TPC_RE Fault detected 100 sRE Capacitance (External) CRE_EXT 0.1 F

VS to RE Delay TVS_RE VS = 8.1 V to RE high, VIN > VIN_UVLO- 1 ms

Transition

RegularOperation

• RE signals successful startup and a powertrain that is ready for operation• Regulated, delayed voltage source intended to power the feedback circuit voltage reference and current monitor

Analog Output

Control Node PR

Signal Type State Attribute Symbol Conditions / Notes Min Typ Max UnitPR Voltage Active Range VPR 0.79 7.40 V

PR Source Current IPR VPR 0.79V 2 mA

PR Sink Current IPR_Low VPR 0.79V 250 500 750 A

PR Resistance to SG RPR 93.3 kΩ

Analog Input

• Modulator control node input• Sinks constant current when externally driven in active range• Sources current when pulled below active range

RegularOperation

Current Feedback IF

Signal Type State Attribute Symbol Conditions / Notes Min Typ Max UnitCurrent Limit (clamp) Threshold VIF_IL VIN = 45 V; TJ = 25 °C 1.90 2.00 2.10

Overcurrent Protection Threshold VIF_OCNot Production Tested; Guaranted by Design;TJ = 25 °C

2.58 2.69 2.80

IF Input Impedance RIF 2.11 2.13 2.15 kΩCurrent Limit Bandwidth BWIL 2 kHz

• A voltage proportional to the PRM output current must be supplied externally to the IF pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp)• Overcurrent protection trip will cause instantaneous powertrain disable, latched after TBLNK

Analog InputV

RegularOperation


Rev. 1.2

07 / 2012 of 22



Temperature Monitor TM

Signal Type State Attribute Symbol Conditions / Notes Min Typ Max UnitTM Voltage VTM Full temperature range 2.12 4.04 V

TM Voltage reference VTM_AMB TJ = 27 °C 2.94 3.00 3.06 V

TM Voltage Ripple VVS_PP Powertrain in burst mode 200 mVTM Available Current ITM 100 A

TM Gain ATM 10 mV/°C

Digital Output [Fault Flag] Fault or Standby TM Disabled Current ITM_DISDC state with TM Voltage +/- 0.5V. This is a high impedance state.

0.0 mA

• The TM pin monitors the internal temperature of the PRM analog control IC.• "Power Good" flag to verify that the PRM is operating

Analog OutputRegular

Operation

Signal Ground SG

Signal Type State Attribute Symbol Conditions / Notes Min Typ Max UnitAnalog Input / Output Any Maximum Allowable Current ISG -100 100 mA

• All control signals must be referenced to this pin, with the exception of VC• SG is internally connected to -IN and -OUT

VTM Control VC

Signal Type State Attribute Symbol Conditions / Notes Min Typ Max UnitVC Voltage VVC RVC_EXT = 68 13 V

VC Available Current IVC VC <=14 V, VIN > 20 V 200 mA

VC duration TVC 7 10 16 ms

VC Slew Rate dVC/dt RVC = 1k 20 V/s

• Pulsed voltage source used to power and synchronize downstream VTM• If not used, must be resistively terminated to -OUT

Analog Output Startup


Rev. 1.2

07 / 2012 of 22



4.0 FUNCTIONAL BLOCK DIAGRAM

+Vout

-Vout

+Vin

TM

PC

Temperature dependent voltage

source

-Vin

VPC_EN

100uA

5V2mA max

16V

Internal Vcc

Regulator

3V

Vref (130°C)

Fault LogicTOFF

delay

R

L

Overtemperature Protection

Modulator

Enable

Q1

Q2

Q3

Q4

CoutCin

PR

0.5mA

2.5mA Min

9V

Vin(OV, UV)Vout

(OV)

IF

Current Limit

OvercurrentProtection

VIF_IL

VIF_OC

8.2V

RE

3 V @ 27°C

RE

VC

VTM Vc Start up pulse

Vs

9V0.01uF

SG

uC 8051

3.3V Linear

Regulator

PC

RE

Vout

Var. Vclamp

Vcc

14V

10ms

+Vout

Output Discharge

(OD)

3.3V

Vcc3.3V

Instant latch

Latch after 120us

PR

Q

QSET

CLR

S

R

10uA

Vcc

93.3k

PC

PR

Enable


Rev. 1.2

07 / 2012 of 22



5.0 HIGH LEVEL FUNCTIONAL STATE DIAGRAM Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.


Rev. 1.2

07 / 2012 of 22



6.0 TIMING DIAGRAMS Module Inputs are shown in blue; Module Outputs are shown in brown; Timing diagrams assumes the following:

Single PRM (no array) VS powers error amplifier RE powers voltage reference and output current transducer IOUT is sensed, scaled, and fed back to IF pin such that IF = 2.00 V at full load

RE

VOUT

PC

PR

VIN

VC

VS

TM

IF

InputInput/ O

utputO

utput

UV

OV

Vpc_en

Vpc

Vvc

Vpr_max

Vvs_amb

Vtm_amb

Vre_amb

TVC

VIF_OC

TBLNK

1Start up with

1.2V/ms < dVIN/dt < maximum

Vpr_min

t < TBLNK

OV

2Quick OC

(t<TBLNK)

3Input OV

VIF_IL

4Input OV

recovery

5PC

disable

6PC

release

7Full load

applied

8Load release and

Output OV (slow f/b)

OT

18 V

1 V

TOFF

TOFF

TON

TON

TBLNK

TBLNK

TPC_RETVS_RE

TOFF TPROT

TPROT

TPC_RE TPC_RE


Rev. 1.2

07 / 2012 of 22



RE

VOUT

PC

PR

VIN

VC

VS

TM

IF

InputO

utputInput/ O

utput

UV

OV

Vpc_en

Vpc

Vvc

Vvs_amb

Vre_amb

VIF_OC

Vpr_min

OV

VIF_IL

Vpr_max

18 V

1 V

Vtm_amb

9Start up with

minimum < dVIN/dt < 1.2V/ms

10Output short

circuit

11Output Power

limit Protection

12Current limit

event

13Input UV

TOFF

TSC

TSCR+TOFF

<TBLNK

(Output Short faultconditions satisfied)

TBLNK

(Output Short faulttimer expired)

OT

Vsc_vpr


Rev. 1.2

07 / 2012 of 22



7.0 APPLICATIONS CHARACTERISTICS The following figures present typical performance at TC = 25ºC, unless otherwise noted. See associated figures for general trend data.

No Load Power Dissipation vs. LineModule Enabled - Nominal VOUT

0

1

2

3

4

5

6

38 40 42 44 46 48 50 52 54

Input Voltage [V]

Po

wer

Dis

sip

atio

n [

W]

-40 ºC 25 ºC 100 ºCTCASE:

Figure 1 - No load power dissipation vs. VIN, module enabled

Efficiency & Power DissipationVOUT = 20 V TCASE = -40 ºC

707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

2

4

6

8

10

12

14

16

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:

Figure 3 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 20 V, TCASE = -40ºC

No Load Power Dissipation vs. LineModule Disabled, PC=Low

0

0.2

0.4

0.6

0.8

1

38 40 42 44 46 48 50 52 54

Input Voltage [V]

Po

wer

Dis

sip

atio

n [

W]

-40 ºC 25 ºC 100 ºCTCASE:

Figure 2 - No load power dissipation vs. VIN, module disabled


707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

2

4

6

8

10

12

14

16

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:



Rev. 1.2

07 / 2012 of 22




707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

4

6

8

10

12

14

16

18

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:


Efficiency & Power DissipationVOUT = 48 V TCASE = 25 ºC

707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

2

4

6

8

10

12

14

16

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:

Figure 7 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 48 V, TCASE = 25ºC


707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

2

4

6

8

10

12

14

16

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:



707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

2

4

6

8

10

12

14

16

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:



707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

4

6

8

10

12

14

16

18

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:



707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

2

4

6

8

10

12

14

16

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:



Rev. 1.2

07 / 2012 of 22




707274767880828486889092949698

0 1 2 3 4 5 6 7 8 9

Load Current [A]

Eff

icie

ncy

[%

]

4

6

8

10

12

14

16

18

Po

wer

Dis

sip

atio

n

[W]

38 45 55 38 45 55VIN:


Figure 13 – Typical output voltage ripple waveform, TCASE = 30ºC, VIN = 45 V, VOUT = 48 V, IOUT = 8.33 A, no external capacitance.

Powertrain switching frequency and periodic input charge vs. input voltage - Full load

800

825

850

875

900

925

950

975

1000

1025

38 40 42 44 46 48 50 52 54 56

Input Voltage [V]

f SW

[kH

z]

0

4

8

12

16

20

24

28

32

36

To

tal

inp

ut

char

ge

per

sw

itch

ing

cyc

le [C

]

55 20 48 55 20 48VOUT

fsw

C

Figure 15 – Powertrain switching frequency and periodic input charge vs. VIN, VOUT; IOUT = 8.33 A

VPR vs. Case Temperature

VIN = 45 V; VOUT = 48 V

4.70 4.704.52

6.16 6.20 6.04

4

4.5

5

5.5

6

6.5

-40 -20 0 20 40 60 80 100Temperature [ºC]

VP

R [

V]

4.17 8.33IOUT:

Figure 12 – Typical control node voltage vs. TCASE, IOUT; VIN = 45 V, VOUT = 48 V

Powertrain switching frequency and periodic output charge vs. input voltage - Full load

800

825

850

875

900

925

950

975

1000

1025

38 40 42 44 46 48 50 52 54 56

Input Voltage [V]

f SW

[kH

z]

0

4

8

12

16

20

24

28

32

36

To

tal

ou

tpu

t ch

arg

e p

er s

wit

chin

g c

ycle

[

C]

55 20 48 55 20 48VOUT

fsw

C

Figure 14 – Powertrain switching frequency and periodic output charge vs. VIN, VOUT; IOUT = 8.33 A

DC Safe Operating Area

0.00

2.08

4.17

6.25

8.33

10.42

5 10 15 20 25 30 35 40 45 50 55 60

Output Voltage [V]

Ou

tpu

t C

urr

ent

[A]

0

80

160

240

320

400

Ou

tpu

t P

ow

er

[W]

Current Power

Figure 16 – DC Output Safe Operating Area


Rev. 1.2

07 / 2012 of 22



DC modulator gain and powertrain equivalent output resistance vs. output current - VOUT = 55V

-4

-2

0

2

4

6

8

10

0 1 2 3 4 5 6 7 8 9

Output Current [A]

GP

R [

dB

]

0

50

100

150

200

250

r eq

_ou

t [

]38 45 55 38 45 55VIN:

Gpr

req_out

Figure 17 – Powertrain characteristics vs. IOUT;

Resistive load, VOUT = 55 V, various VIN


-2

0

2

4

6

8

10

12

0 1 2 3 4 5 6 7 8 9

Output Current [A]

GP

R [

dB

]

0

10

20

30

40

50

60

70

80

90

r eq

_ou

t [

]

38 45 55 38 45 55VIN:

Gpr

req_out



Output Power vs. VPR

VIN = 45V, VOUT = 48V, TC=25ºC

0

40

80

120

160

200

240

280

320

360

400

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

PR Voltage [V]

Ou

tpu

t P

ow

er

[W]

Typical min Nominal Typical max

Figure 21 – Output Power vs. VPR; VIN = 45 V, VOUT = 48 V, TCASE = 25ºC


2

4

6

8

10

12

14

0 1 2 3 4 5 6 7 8 9

Output Current [A]

GP

R [

dB

]

0

2

4

6

8

10

12

14

16

18

20

r eq

_ou

t [

]

38 45 55 38 45 55VIN:

Gpr

req_out



Effective internal input (CIN_INT) and output

(COUT_INT) capacitance vs. applied voltage

0

1

2

3

4

5

6

7

8

9

0 5 10 15 20 25 30 35 40 45 50 55Voltage [V]

Inp

ut

Cap

acit

ance

[μ

F]

0

1

2

3

4

5

6

7

8

9

Ou

tpu

t C

ap

aci

tan

ce

[μF

]

Cin Cout

Figure 20 – Effective internal input and output capacitance vs. voltage – ceramic type

Powertrain equivalent input resistancevs. output current - VOUT = 55V

0

2

4

6

8

10

12

14

16

0 1 2 3 4 5 6 7 8 9

Output Current [A]

r eq

_in

[ ]

38 45 55VIN:

Figure 22 – Magnitude of powertrain dynamic input impedance vs. VIN, IOUT; VOUT = 55 V


Rev. 1.2

07 / 2012 of 22




0

10

20

30

40

50

60

70

80

90

0 1 2 3 4 5 6 7 8 9

Output Current [A]

r eq

_in

[ ]

38 45 55VIN:



0

2

4

6

8

10

12

14

16

18

20

0 1 2 3 4 5 6 7 8 9

Output Current [A]

r eq

_in

[ ]

38 45 55VIN:


8.0 GENERAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).


Rev. 1.2

07 / 2012 of 22



9.0 PRODUCT OUTLINE DRAWING AND RECOMMENDED PCB FOOTPRINT


Rev. 1.2

07 / 2012 of 22



10.0 PRODUCT DETAILS AND DESIGN GUIDELINES 10.1 Control pins description and characteristics Control node (PR) is the input to the control node which determines the powertrain timing and ultimately the module output power (Figure 21). An internal 0.5mA current sink is always active. The bi-directional buffer between PR and the control node has two states. In normal operation, PR will be above the 0.79V switching threshold, and will drive the control node through the buffer. An internal 7.4V clamp determines the maximum output power that can be requested of the modulator. When PR falls below 0.79 V, the converter will stop switching. An internal circuit clamps the modulator input control node to 0.79 V, and a buffer will source up to 2.5 mA out of the pin at that clamp level. For this reason, the output impedance of the amplifier driving PR must be taken into account. A rail-to-rail operational amplifier with low output impedance is always recommended. The powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). Both the modulator gain and the equivalent output resistance vary as a function of line, load and output voltage, as shown in Figures 17, 18 and 19. As the load increases, the powertrain pole moves to higher frequency. As a result, the closed loop crossover frequency will be the

highest at full load and lowest at minimum load. Figure 25 shows a reference AC small-signal model. Current feedback (IF) is the input for the module output overcurrent protection and current limit features (see functional block diagram in section 4.0). A voltage proportional to the powertrain output current must be applied to IF in order for overcurrent protection to operate properly. If the IF voltage exceeds the IF pin’s overcurrent protection threshold, the powertrain will stop switching. If the IF voltage falls below the overcurrent protection threshold within TBLANK time, then the powertrain will immediately resumes switching. Otherwise a fault is latched. The current limit threshold for the IF pin is set lower than the protection threshold. When the IF pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amplifier which overrides the modulator input maximum level. This causes the powertrain to maintain a constant output current. The bandwidth of this current limit integrator is significantly slower than that of the PR control node input. Therefore this current limit can not be used in lieu of properly compensating the (external) PR control loop to avoid exceeding maximum current or power ratings for the device. If the IF pin is not driven, it must be resistively terminated to SG. A 1k resistor to SG is recommended in this case.

Figure 25 – PRM48BF480T400A00 AC small signal model


Rev. 1.2

07 / 2012 of 22



VTM Control (VC) pin supplies an initial VCC voltage to downstream VTMs, enabling them and synchronizing their startup with the PRM. The VCC voltage is a pulse, typically 10ms duration at 14V. If VC is not loaded by a VTM, it must be terminated with a 1kresistor to –VOut. Primary Control (PC) is both an input and an output. It can provide the following features: • Delayed start: upon application of voltage (>UVLO) to the module power input and after TOFF, the PC pin will source a constant 90μA current. • Output disable: PC may be pulled down externally in order to disable the module. Pull down resistance should be less than 300 Ω to SG. • Fault detection flag: The PC 5 V voltage source is internally turned off when a fault condition is latched. Note that aside from the Short Circuit fault condition, PC does not have significant current sinking capability. Therefore in the case of an array of PRMs with interconnected PC pins, PC does not in general reflect the fault state of all PRMs. The common PC line will not disable neighboring modules when a fault is detected except for a latched Output Short Circuit fault. Conversely any unit in the array latching a Short Circuit fault will disable the array for TSCR. Temperature Monitor (TM) pin outputs a voltage proportional to the absolute temperature of the converter analog control IC. It can be used to accomplish the following functions: • Monitor the control IC temperature: The gain and setpoint of TM are such that the temperature, in Kelvin, of the PRM controller IC is equal to the voltage on the TM pin scaled by 100. (i.e. 3.0 V = 300 K = 27ºC). • Closed loop thermal management at the system level (e.g. variable speed fans or coolant flow) • Fault detection flag: The TM voltage source is turned off as soon as a fault is detected. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of TM. Reference Enable (RE) pin outputs a regulated 3.3V, 8mA voltage source. It is enabled only after successful startup of the PRM powertrain (see chapters 5.0 and 6.0.) RE is intended to power the output current transducer and also the voltage reference for the control loop. Powering the reference generator with RE helps provide a controlled startup, since the output voltage of the system is able to track the reference level as it comes up. Voltage Source (VS) pin outputs a gated (e.g. mirrors PC status), non-isolated, regulated 9V, 5mA voltage source. It can be used to power external control circuitry; it always leads RE.

Signal Ground (SG) pin provides a Kelvin connection to the PRM’s internal signal ground. It should be used as the reference for PR, TM, IF, and should return all PC, VS and RE pin currents. In array configurations with common ground control circuits, a series resistor (~1) is recommended in order to decouple power and signal current returns. 10.2 Control circuit requirements and design procedure The PRM48BF480T400A00 is an intelligent powertrain module designed to fully exploit external output voltage feedback and current sensing sub-circuits. These two external circuits are illustrated in Figure 26, which shows an example of the PRM in a standalone application with local voltage feedback and high side current sensing. In general, these circuits include a precision voltage reference, an operational amplifier which provides closed loop feedback compensation, and a high side current sense circuit which includes a shunt and current sense IC. The following design procedures refer to the circuit shown in Figure 26. 10.2.1 Setting the output voltage level The output voltage setpoint is a function of the voltage reference and the output voltage sense ratio. With reference to Fig. 26, R1 and R2 form the output voltage sensing divider which provides the scaled output voltage to the negative input of the error amplifier; a dedicated reference IC provides the reference voltage to the positive input of the error amplifier. Under normal operation, the error amplifier will keep the voltages at the inverting and non-inverting inputs equal, and therefore the output voltage is defined by:

2

21

R

RRVV refOUT

Note that the component R1 will also factor into the compensation as described in a later section. It is important to apply proper slew rate to the reference voltage rise when the control loop is initially enabled. The recommended range for reference rise time is 1 ms to 9 ms. The lower rise time limit will ensure optimized modulator timing performance during startup, and to allow the current limit feature (through IF pin) to fully protect the device during power-up. The upper rise time limit is needed to guarantee a sufficient factorized bus voltage is provided to any downstream VTM input before the end of the VC pulse.


Rev. 1.2

07 / 2012 of 22



10.2.2 Setting the output current limit and overcurrent protection level The current limit and overcurrent protection set points are linked, and scale together against the current sense shunt, and the gain of the current sense amplifier. The output of the current sense IC provides the IF voltage which has VIF_IL and VIF_OC thresholds for the two functions respectively. The set points are therefore defined by:

CSS

ILIFIL GR

VI

_

and

CSS

OCIFOC GR

VI

_

where GCS is the gain of the current sense amplifier.

10.2.3 Control loop compensation requirements In order to properly compensate the control loop, all components which contribute to the closed loop frequency response should be identified and understood. Figure 25 shows the AC small signal model for the module. Modulator DC gain GPR and powertrain equivalent resistance rEQ_OUT are shown. These modeling parameters will support a design cut-off frequency up to 50kHz. Standard Bode analysis should be used for calculating the error amplifier compensation and analyzing the closed loop stability. The recommended stability criteria are as follows: 1) Phase Margin > 45º : for the closed loop response, the phase should be greater than 45º where the gain crosses 0dB. 2) Gain Margin > 10dB : The closed loop gain should be lower than -10dB where the phase crosses 0º. 3) Gain Slope = -20dB/decade : The closed loop gain should have a slope of -20dB/decade at the crossover frequency. The compensation characteristics must be selected to meet these stability criteria. Refer to Figure 27 for a local sense, voltage-mode control example based on the configuration in Figure 26. In this example, it is assumed that the maximum crossover frequency (FCMAX) has been selected to occur between B and C. Type-2 compensation (Curve IJKL) is sufficient in this case. The following data must be gathered in order to proceed:

Modulator Gain GPR: See Figures 17, 18, 19 Powertrain equivalent resistance rEQ: See Figures

17, 18, 19

Internal output capacitance: see Figure 20 External output capacitance value

In the case of ceramic capacitors, the ESR can be considered low enough to push the associated zero well above the frequency of interest. Applications with high ESR capacitor may require a different type of compensation, or cascade control. The system poles and zeros of the closed loop can then be defined as follows:

Powertrain pole, assuming the external capacitor ESR can be neglected:

LOADOUTEQ

LOADOUTEQC Rr

RrR

EXTOUT

_

_

_

Main pole frequency:

EXTOUTINTOUTLOADOUTEQ

LOADOUTEQP

CRr

Rr__

_

_ Cπ2

1F

Compensation Mid-Band Gain:

1

3MB R

Rlog20G [1]

Compensation Zero:

131Z CRπ2

1F

[2]

Compensation Pole:

21

2132

π2

1F

CCCCRP

and for FP2>>FZ1 (C1 + C2 ≈ C1):

232 2

1F

CRP

[3]


Rev. 1.2

07 / 2012 of 22



10.2.4 Midband Gain Design (R1,R3): With reference to Figure 27: curve ABC is the:

minimum output voltage in the application maximum input voltage expected in the application maximum load

PRM open loop response, and is where the maximum crossover frequency occurs. In order for the maximum crossover frequency to occur at the design choice FCMAX, the compensation gain must be equal and opposite of the powertrain gain at this frequency. For stability purposes, the compensation should be in the Mid-band (J-K) at the crossover. Using Equation [1], the mid-band gain can be selected appropriately.

10.2.5 Compensation Zero Design (C1): With reference to Figure 27: curve EFG is the:

maximum output voltage in the application minimum input voltage expected in the application minimum load in the application

PRM open loop response, and is where the minimum crossover frequency FCMIN occurs. Based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore FCMIN will occur where EFG is equal and opposite of GMB. C1 can be selected using Equation [2] so that FZ1 occurs prior to FCMIN.

Figure 26 – Control circuit example

PRMTM Regulator


Rev. 1.2

07 / 2012 of 22



Open Loop Gain vs. Frequency

-40

-20

0

20

40

60

80

Frequency, Log scale(y-intercept is application specific)

Ga

in (

dB

)

PRM Open Loop Max Load

A B

E F

I

J KL

Compensation Gain

Application's op-amp G·BW

C

G

FCMAXFCMIN

PRM Open Loop Min Load

Figure 27 – Reference asymptotic Bode plot for the considered system

10.2.6 High Frequency Pole Design (C2): Using Equation [3], C2 should be selected so that FP2 is at least one decade above FCMAX and prior to the gain bandwidth product of the operational amplifier (10MHz for this example). For applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. 10.2.7 Verifying Stability: The preferred method for verifying stability is to use a network analyzer, measuring the closed loop response across various lines and load conditions. In the absence of a network analyzer, a load step transient response can be used in order to estimate stability. Figure 28 illustrates an example of a load step response. Equation [4] can be used to predict the phase margin

based on the ratio of the “kick” to “droop” (as defined in Fig. 28).

Figure 28 – load step response example and “droop” vs. “kick” definition


Rev. 1.2

07 / 2012 of 22



22

2

ln

ln100

d

k

dk

m [4]

10.3 Burst Mode Operation: At light loads, the PRM will operate in a burst mode due to minimum timing constraints. An example burst operation waveform is illustrated in Figure 29. For very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. In this case the external error amplifier will periodically drive PR below the switching threshold in order to maintain regulation. Switching will cease momentarily until the error amplifier once again drives PR voltage above the threshold.

Figure 29 – light load burst mode of operation

Note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variable. The variability depends on many factors including input voltage, output voltages, load impedance, and external error amplifier output impedance. In burst mode, the gain of the PR input to the plant which is modeled in the previous sections is time varying. Therefore the small signal analysis can not be directly applied to burst mode operation. 10.4 Input and Output filter design Figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the PRM at full load under various input and output voltages conditions.

Figure 20 provides the effective internal capacitance of the module. A conservative estimate of input and output peak-peak voltage ripple at nominal line and trim is provided by equation [5]:

EXTINT

SW

FLTOT

CC

f

IQ

V

4.0

[5]

QTOT is the total input (Fig. 15) or output (Fig. 14) charge per switching cycle at full load, while CINT is the module internal effective capacitance at the considered voltage (Fig. 20) and CEXT is the external effective capacitance at the considered voltage. 10.5 Input filter stability The PRM can provide very high dynamic transients. It is therefore very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. For this purpose, the converter dynamic

input impedance magnitude INEQr _ is provided in Figures

22, 23, 24. It is recommended to provide adequate design margin with respect to the stability conditions illustrated in 10.5.1 and 10.5.2 . 10.5.1 Inductive source and local, external input decoupling capacitance with negligible ESR (i.e.: ceramic type) The voltage source impedance can be modeled as a series RlineLline circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified:

INEQEXTININTIN

lineline

rCC

LR

___ )( [6]

INEQline rR _ [7]

It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance, [7]. However, Rline cannot be made arbitrarily low otherwise equation [6] is violated and the system will show instability, due to under-damped RLC input network.


Rev. 1.2

07 / 2012 of 22



10.5.2 Inductive source and local, external input decoupling capacitance with significant RCIN_EXT ESR (i.e.: electrolytic type) In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor Lline. Notice that, the high performance ceramic capacitors CIN_INT within the PRM should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be

EXTINCINEQ Rr__ [8]

INEQCEXTIN

line rRC

L

EXTIN

__ _

[9]

Equation [9] shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT) – the system will be under-damped and may even become destabilized. Again, an octave of design margin in satisfying [8] should be considered the minimum. 10.6 Arrays Up to ten PRMs of the same type may be placed in parallel to expand the power capacity of the system. The following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings.

–IN pins of all PRMs must be connected together. Both inductance and resistance from the common power source to each PRM should be minimized, and matched.

Input voltage to all PRMs must be the same. Independent fuses for each PRM are recommended.

PC pins must be connected together for synchronization and proper fault response.

Reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules’ RE pins have reached their operational voltage levels.

There must be one single external voltage control loop. The control loop must drive each PR pin relative to each modules’ SG pin, and the local PR voltage must be the same across all modules.

Each PRM must have its own local current shunt and current sense circuitry to drive it’s IF pin.

The number of PRMs required to achieve a given array capacity must consider all sources of mismatch to avoid overstress of any PRM in the array. Imbalances in sharing are not only due to

current sharing accuracy specifications, but also temperature differences among PRMs, Vin variations, and error terms in the buffering of the error amplifier output to the PR pins.

Control loop compensation procedures above will hold for an array, in general, although many parameters must be scaled against the number of PRMs in the system.

Please contact Vicor Applications for assistance. 10.7 Input Fuse Recommendations A fuse should be incorporated at the input to each PRM, in series with the +IN pin. A 15A or smaller input fuse (Littelfuse® NANO2® 451/453 Series, or equivalent) is required to safety agency conditions of acceptability. Always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. 10.8 Layout considerations Application Note AN:005 details board layout using V•I Chip components. Additional consideration must be given to the external control circuit components. The current sense shunt signal voltage is highly sensitive to noise. As such, current sensing circuitry should be located close to the shunt to minimize the length of the sense signals. A Kelvined connection at the shunt is recommended for best results. The control signal from a remote voltage sense circuit to the PRM should be shielded. Avoid routing this, or other control signals directly underneath the PRM, if possible. Components that tie directly to the PRM should be located close to their respective pins. It is also critical that all control components be referenced to SG, and that SG not be tied to any other ground in the system, including –IN or –OUT of the PRM.


Rev. 1.2

07 / 2012 of 22



Warranty

Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages. Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Intellectual Property Notice Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965.

Vicor Corporation 25 Frontage Road

Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715

email

Customer Service: [email protected] Technical Support: [email protected]


prm™ regulator - vicor corporationcdn.vicorpower.com/documents/datasheets/prm48b_4… · ·...

Documents