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Problem 1 Tuesday, December 01, 2009 9:09 PM hw2Spring2011 Page 1

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Page 1: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Problem 1Tuesday, December 01, 2009

9:09 PM

hw2Spring2011 Page 1

Page 2: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Use Matlab to obtain the step response of the closed-loop system. Comment on the step response characteristics

(d)

Problem 1 continued

hw2Spring2011 Page 2

Page 3: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

(b) Let the controller K(s)=1 for this part of the question. Analytically evaluate the steady-state error due to a Step input and compare it with the Steady state error obtained using Matlab. What is the type of the System?

Problem 2Tuesday, December 01, 2009

9:15 PM

hw2Spring2011 Page 3

Page 4: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Part cTuesday, December 01, 2009

9:21 PM

hw2Spring2011 Page 4

Page 5: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Part cTuesday, December 01, 2009

9:23 PM

hw2Spring2011 Page 5

Page 6: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Problem 3 (Lead controller)Tuesday, December 01, 2009

9:24 PM

hw2Spring2011 Page 6

Page 7: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Consider the following feedback interconnection

Where

Design a Lag Controller such so that the Phase margin is 45 degrees and the kv=20.

Problem 4 (Lag Controller)Tuesday, December 01, 2009

9:27 PM

hw2Spring2011 Page 7

Page 8: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Problem 5Friday, November 20, 2009

6:12 PM

hw2Spring2011 Page 8

Page 9: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Problem 5 ContinuedFriday, November 20, 2009

6:14 PM

hw2Spring2011 Page 9

Page 10: Problem 1 - Electrical and Computer Engineering · and that the phase margin obtained by the PD design step is not affected. (b) Plot bode plot of Gl PI which is same as K G. Iterate

Problem 6

hw2Spring2011 Page 10

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