processor architectures and program mapping 5kk10 tu/e 2006 henk corporaal jef van meerbergen bart...
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![Page 1: Processor Architectures and Program Mapping 5kk10 TU/e 2006 Henk Corporaal Jef van Meerbergen Bart Mesman](https://reader030.vdocument.in/reader030/viewer/2022032704/56649d535503460f94a2fc03/html5/thumbnails/1.jpg)
Processor Architectures and Program Mapping
5kk10TU/e
2006
Henk Corporaal
Jef van Meerbergen
Bart Mesman
![Page 2: Processor Architectures and Program Mapping 5kk10 TU/e 2006 Henk Corporaal Jef van Meerbergen Bart Mesman](https://reader030.vdocument.in/reader030/viewer/2022032704/56649d535503460f94a2fc03/html5/thumbnails/2.jpg)
04/18/23 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman
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Embedded Systems Courses• We go through all the design steps of a complete multi-
processor embedded system – (containing hardware and software)
• Discuss many design trade-offs
• 4 connected courses:– Designing Embedded Systems on Silicon: 5kk00
– Processor Architectures and Program Mapping: 5kk10
– Multiprocessors: 5kk20
– Design of an Embedded System: 5kk53 (lab course)
![Page 3: Processor Architectures and Program Mapping 5kk10 TU/e 2006 Henk Corporaal Jef van Meerbergen Bart Mesman](https://reader030.vdocument.in/reader030/viewer/2022032704/56649d535503460f94a2fc03/html5/thumbnails/3.jpg)
04/18/23 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman
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Processor Architectures and Program Mapping
Objectives:
• Study the processing components of future multi-processor platforms, ranging from– highly flexible processors, to– highly computational-efficient processors
• Learn how to map applications to these components
• Learn how to exploit the (data) memory hierarchy
![Page 4: Processor Architectures and Program Mapping 5kk10 TU/e 2006 Henk Corporaal Jef van Meerbergen Bart Mesman](https://reader030.vdocument.in/reader030/viewer/2022032704/56649d535503460f94a2fc03/html5/thumbnails/4.jpg)
04/18/23 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman
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flexibility
efficiency
DSP
Programmable CPU
Programmable DSP
Application specific instruction set
processor (ASIP)
Applicationspecific processor
Processor design spectrum
![Page 5: Processor Architectures and Program Mapping 5kk10 TU/e 2006 Henk Corporaal Jef van Meerbergen Bart Mesman](https://reader030.vdocument.in/reader030/viewer/2022032704/56649d535503460f94a2fc03/html5/thumbnails/5.jpg)
04/18/23 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman
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low medium high
high
medium
low
flexibility
efficiency
ASIC
GP procFPGA
DSP
ASIP
Processor design spectrum
![Page 6: Processor Architectures and Program Mapping 5kk10 TU/e 2006 Henk Corporaal Jef van Meerbergen Bart Mesman](https://reader030.vdocument.in/reader030/viewer/2022032704/56649d535503460f94a2fc03/html5/thumbnails/6.jpg)
04/18/23 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman
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i386SXi486DX P568040
microsparc
Supersparc
601604
Ultrasparc P6
604e21164a
Turbosparc 604e
21364
7400
3DTV
Queryby
humming
106
105
104
103
102
101
100
2 1 0.5 0.25 0.13 0.07
Computational efficiency [MOPS/W]
Feature size [m]
[Roza]
Intrinsic computational efficiency
ICE of silicon
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Schedule forProcessor Architectures and Program Mapping
• Lect 1, Nov 30: Bart Mesman• Programmable CPU cores + hands-on 1
• Lect 2, Dec 7: Bart Mesman• Programmable DSP cores
• Lect 3, Dec 14: Henk Corporaal• ILP Architectures
• Lect 4, Dec 21: Henk Corporaal• VLIW compilers
![Page 8: Processor Architectures and Program Mapping 5kk10 TU/e 2006 Henk Corporaal Jef van Meerbergen Bart Mesman](https://reader030.vdocument.in/reader030/viewer/2022032704/56649d535503460f94a2fc03/html5/thumbnails/8.jpg)
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Schedule forProcessor Architectures and Program Mapping
• Lect 5, Jan 11: Bart Mesman• ASIPs + hands-on 3
• Lect 6, Feb 8: Bart Mesman• SIMD + NoC
• Lect 7, Feb 15: Jef van Meerbergen• Real processors and Platforms
• Lect 8, Feb 22: Jef van Meerbergen / Guest• WSN and system level design aspects / trade-offs
• Lect 9,10, Mar 1,8: Henk Corporaal• Data management (DTSE) + hands-on 3
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Topic 1: Programmable CPU cores• Exploiting PLP = pipeline parallelism
= clock frequency• Identify bottlenecks in CPU architectures for media
applications (performance and power)• Good for application development and prototyping• Different criteria for stand-alone vs. embedded CPUs
• Introduction of the applications• Hands-on
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Topic 2: DSP cores
• Evolution from CPU to DSP architectures from a DSP application point of view: exploit ILP
• Compilation is complicated as a result of DSP architectural features
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Topic 3: ASIPs
• Synthesis approach: design your own processor!!
• Tuning the instruction-set and architecture by adding application-specific computational units, registers, and busses
• Computational efficiency while maintaining flexibility
• Compiler should be flexible!: retargetable compilation
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Topic 4: VLIW processing
• Exploiting ILP = Instruction/Operation level parallelism
• Architectures
• Code generation
• Limits of VLIW
• Disadvantage: code size
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Topic 5: SIMD processing
• Exploiting Data level parallelism
• Advantage: code size
• Architectures
• Code generation
• Communication issues
• RC-SIMD and D-SIMD architectures
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Topic 6: Real processors and Platforms
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Topic 7: WSN and system level design aspects / trade-offs
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Topic 8 details: Data management• How to effectively exploit a data memory hierarchy for
low energy and high performance• Methodology:
– Rewrite your program such that
– data locality is exploited
– find interesting 'copy candidates'
– assign 'copy candidates' to local memories
– schedule accesses to memories
– exploit data life-time to overlap data structures in memory
– use loop transformations
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Hands-on• We consider the mapping of 3 applications:
– 16-tap FIR filter (MIPS)– TTA– YUV2RGB conversion (DTSE)
Map application to
• 1. Programmable RISC core
• 2. VLIW
• 3. Data memory hierarchy
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Hands-on 1: RISC core
• Programmable RISC cores– MIPS assembly code– use of SPIM simulator
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Hands-on 2: VLIW
• TTA– Application not yet decided
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Hands-on 3: Use of Memory Hierarchy
• Data management– Code transformations– Exploiting the memory hierarchy for low power
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Exam
• Oral exam
– Course theory 40%, – Hands-on 60%
• MIPS assembly hands-on (only for exam admission)
• TTA
• DTSE hands-on
• Material: all slides, Jef’s homepage->education->5p520 (embedded multimedia systems)
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Other
• Website (under construction):
www.ics.ele.tue.nl/~heco/courses/pam
• Location: EH 2.19
• Time: Thursday 13.30 – 16.30 hour