productive debug and analysis of software on armv8 … · productive debug and analysis of software...
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Rob Kaye Technical Specialist, ARM
Productive Debug and Analysis of Software on ARMv8 Systems Using Virtual Prototypes
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Virtual Prototypes and the
Software Development Challenge
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Software Costs Increasing
Primary Design Costs By Process Node
The cost of developing and
qualifying software increases
rapidly with higher complexity
IC designs
High-performance SoCs
include multiple processor
cores and 100s of IP blocks
Source: IBS 2013
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Core, Subsystem
or SoC
Standardized interface to
ARM, 3rd party and open
source debuggers
Comprehensive, extensible
trace of prototype and
software
Runtime control, checking,
reporting
Visualisation, file system,
networking,
keyboard/mouse
Aligned with deliverables
from ARM, Linaro
Integration with 3rd party
models, EDA solutions
Assembling a Virtual Prototype Key Components for a Complete Solution
Compatible
Software
Stack
SystemC
Interface
Scripting
Debug
Interface
Virtual I/O
Trace
Interface
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Benefits of Virtual Prototypes
Time-to-Market Parallel development of hardware and software
Early access: models available long before silicon / board ARMv7-A Virtualisation Model: April 2010 (Board released Jan. 2012)
big.LITTLE Model to Lead Partners: April 2011(Board released July 2012)
ARMv8: Architecture Model: 2011, Cortex-A57, Cortex-A53: 2012
Juno VP: 2012 (Silicon: 2014)
Aids in understanding complex IP Executable PV models of System IP (CCI, CCN, GIC, SMMU) speeds the learning process
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Total Project Duration “Traditional”
Software
Development
HW/SW
Co-Design
Software
Development
Total Project Duration with VP
Virtual Prototype
Virtual Prototypes Shorten the Project Duration Parallelising Hardware and Software Development
Time Saved
Total Project Duration “Traditional”
ASIC
Design
ASIC
Production
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Benefits of Virtual Prototypes
Time-to-Market Parallel development of hardware and software
Early access: models available long before silicon / board ARMv7-A Virtualisation Model: April 2010 (Board released Jan. 2012)
big.LITTLE Model to Lead Partners: April 2011. (Board released July 2012)
ARMv8: Architecture Model: 2011, Cortex-A57, Cortex-A53: 2012
Juno VP: 2012 (Silicon: 2014)
Aids in understanding complex IP Executable PV models of System IP (CCI, CCN, GIC, SMMU) speeds the learning process
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Speeding-up Development with Virtual Prototyping ARMv8 Test Chip Bring-Up Timeline
Development on virtual prototype before silicon Development
on hardware
2 years 10 days
Full software stack
and tools validated
on hardware
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Aids in understanding complex IP Executable PV models of System IP (CCI, CCN, GIC, SMMU) speeds the learning process (debug, trace,
checkers)
Ease of distribution, support and maintenance No hardware to store, ship or setup
Profile code and find bugs faster Extensive debug and trace capabilities: more flexible than hardware
Virtual prototypes enable deterministic debug
Iterative Development Virtual prototypes inherently more adaptable
Start development on base prototypes, add incremental models as they come on line
High performance for software developers Good for software development – boot an OS in 10s of seconds
Benefits of Fast Models and Virtual Prototypes Other consideration when choosing a development methodology
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Debug and Trace & Analysis
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Fast Execute real world workloads efficiently
Flexible Integration with ARM and 3rd party solutions
Enables the broadest spectrum of use cases
Fidelity Accurate, complete modeling of
ARMv8 and ARMv7 cores and System IP
Productive Debug and Analysis of Software Virtual Prototypes Provide the Ideal Solution
Checkpointing
Debug, Analysis and Trace
Rapid Peripheral Validation
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Debug, Trace and Platform Integration
Automated generation of debug (CADI)
and trace (MTI) interfaces DS-5 and 3rd party debugger support
SystemC TLM 2.0 interfaces to ESL tools AMBA-PV extensions to TLM 2.0 up to AMBA 5
Virtual
Prototype
Cortex-A57
Fast Model
Cortex-A53
Fast Model
CCI/CCN Fast Model
Peripheral
model
GIC
Fast Model
SMMU
Fast Model
Custom
IP model
Custom
IP model
Custom
IP model
Debug and Simulation Control (CADI)
Model Trace Interface (MTI)
SystemC TLM 2.0 Interface (AMBA-PV)
SystemC TLM 2.0 Interface (AMBA-PV)
Custom
IP model
Peripheral
model
DS-5 Debug and Trace
Streamline Visualisation
Trace and Debug
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Application Code Model Code
Debugging the Virtual Prototype and the Code Running on it
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“JTAG” like debug interface to the virtual prototype
Architecturally Independent
Gives access to Memory, registers, breakpoints, run-time control, disassembly
Supported by ARM and ecosystem debug solutions Interface to GDB
CADI Component Architecture Debug Interface
Core, Subsystem
or SoC
Virtual I/O
Compatible
Software
Stack
SystemC
Interface
Scripting
Trace
Interface
Debug
Interface
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Application debug on the VP same as on final
hardware No modifications required for using the models
Connection between debugger and target via
peripheral component E.g. Ethernet, Serial
Application Debug
GDB Frontend
Fixed Virtual Prototype
Cortex-A57
Fast Model
Cortex-A53
Fast Model
CCI/CCN Fast Model
Peripheral
model
GIC
Fast Model
SMMU
Fast Model
Ethernet
Model Ethernet
Linux
GDB Server
Application
Software Stack on Model Core, Subsystem
or SoC
Virtual I/O
Compatible
Software
Stack
SystemC
Interface
Scripting
Trace
Interface
Debug
Interface
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Key advantages for a VP versus hardware are: You can hack it to add your own debug
Control and interaction is simple and comprehensive
Instrumentation (also known as printf() debugging) is a
simple but effective way of finding out what your code is doing Several options supported
Interfaces to Python scripting
CADI access to model internals
Other Debug Options Instrumentation and Scripting
Fixed Virtual Prototype
Cortex-A57
Fast Model
Cortex-A53
Fast Model
CCI/CCN Fast Model
Peripheral
model
GIC
Fast Model
SMMU
Fast Model
Peripheral
Model CADI
resources
{
REGISTER{type(uint), bitwidth(32)} ctrl_reg;
REGISTER{type(uint), bitwidth(32)} irq_reg;
REGISTER{type(uint), bitwidth(32)} a_reg;
REGISTER{type(uint), bitwidth(32)} b_reg;
REGISTER{type(uint), bitwidth(32)} result_reg;
}
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Leverages popular Python scripting/programming language
Supports increasing use of Virtual Prototypes in scripted/batched environments
Interactive and programmatic usage
PyCADI is self describing: No prior knowledge about the target is required
PyCADI enables: Connection to targets
Memory access
Register access
Breakpoints
Run-control
Model Scripting Interface: PyCADI High Level Python Interface Built on Top of CADI
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Used to create Python scripts for common debugger tasks Run/Stop/Step execution
Read/Write to registers and memory
Place breakpoints
Scripting automated verification Start the simulation and load application code
Enable tracing and generate trace logs
Post process trace logs to compare with “Golden Reference”
Example PyCADI Applications How are we using it? How do partners use it?
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User configurable
Programmable use-case awareness
Real-Time feedback on software
fulfilment or failure to fulfil criteria of
use-case PyCADI interrogates model and compares
results with expected configuration
Checkers can be supplied with IP
Automatic peripheral discovery
Stateful analysis
Example Use of PyCADI Use Case Validity Rapid validation of correct device programming, simplifies bring up of complex peripherals
? ? ?
!
RGB/BGR?
16Bpp 565/555?
UPBASE? PPL? LPP?
Clocks?
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Plugin
Trace in hardware is via CoreSight
Trace in ARM Virtual Prototypes is via Model Trace Interface (MTI)
Model Trace Interface (MTI) is a provided interface
on the Fast Model Plug-ins connected to the MTI at simulation start-up
Wide range of events can be traced Memory and cache accesses, branches, registers accesses exceptions/interrupts
Extensible, comprehensive and not subject to hardware restrictions
Trace in Virtual Prototypes Model Trace Interface (MTI)
Fixed Virtual Prototype
Cortex-A57
Fast Model
Cortex-A53
Fast Model
CCI/CCN Fast Model
Peripheral
model
GIC
Fast Model
SMMU
Fast Model
Peripheral
Model
MT
I
Plugin Plugin
Analysis, Viewers,
Charting
DS-5 Debug and Trace
Streamline Visualisation
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Trace source generates a stream of trace events. Accompanied with a set of data fields
One of two possible actions triggered
by a trace event: Increment a counter
Call a callback
Callback carries subset of the data fields
Callbacks and counters can be registered
and unregistered during run-time of
the simulation.
MTI Operation: General
Example: Run State Transition
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Bare metal trace of ARMv7-A and ARMv8-A cores
Symbolic debug
Source stepping
Instruction stepping
Disassembly
Instruction and Event Aware
Virtual Prototype Debug and Trace with ARM DS-5 Productive software development pre-silicon shortens time-to-market
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ARM DS-5 Streamline compatible data generation from Fast Models
Tracing and visualisation of core performance parameters
OS aware
Thread aware
Custom / User Defined Trace Counters
Software Performance Tuning with Fast Models and Streamline Identify and correct software performance hotspots pre-silicon
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Prototype Integration,
Hardware/Software Debug
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Virtual Prototypes used during SoC development Hardware/Software Co-Verification
Software Driven Verification
Analysis
EDA environments support SystemC Cadence, Carbon Design Systems, Mentor Graphics, Synopsys
Rich environment for development and debug
Models from many sources and mixed levels of abstraction (PV/CA, PV/RTL) “Host” simulator schedules the Fast Models providing a degree of timing control
SystemC TLM 2.0 Timing Annotation enables passing of timing information
Concurrent Hardware and Software Bring-Up Extending the Virtual Prototype for a broad range of uses cases
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Virtual
Prototype
Cortex-A57
Fast Model
Cortex-A53
Fast Model
CCI/CCN Fast Model
Peripheral
model
GIC
Fast Model
SMMU
Fast Model
Custom
IP model
Custom
IP model
Custom
IP model
Debug and Simulation Control (CADI)
Model Trace Interface (MTI)
SystemC TLM 2.0 Interface (AMBA-PV)
SystemC TLM 2.0 Interface (AMBA-PV)
Custom
IP model
Peripheral
model
Concurrent Hardware and Software Debug
Standardized TLM 2.0 bridges for
AMBA
Enables broadest range of use
cases
Standardized Interfaces to
solutions from: Synopsys (Virtualizer)
Cadence (VSP)
Carbon (SoC Designer)
Mix and match models at
different levels of abstraction
Concurrent debug of hardware
and software
AMBA TLM
AMBA TLM
© 2014 Synopsys, Inc. All rights reserved. 27
Leverage and Extend Your Software Debugger
Joint DS-5/VP Explorer software debugging & tracing of a VDK for ARM big.LITTLE
Variables Call stack
Disassembly
OS Kernel
Eclipse SW Debugger
Registers
VDK
Performance
Processes
Power
Registers
© 2014 Synopsys, Inc. All rights reserved. 28
Debugging a Kernel Error
29 © 2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Unified Hardware and Software Debugging
CPU Models
SystemC
process debug
Multi-Core SW Debug View HW Debug View
Virtual System
Prototype Embedded
Software
Waveform,
Watchpoint
System
Memory
CPU &
TLM2 Model
registers
SystemC
HW Model
Stepwise exec.
BreakPoint
SW Debug
+
HW model info.
SystemC Aware Debug
+
TLM2.0 Debug
TLM2.0 Breakpoint TLM2.0 Memory Checker TLM2.0 Performance Analysis TLM 2.0 Transaction Viewer SystemC and TLM 2.0 Profiling
Carbon Design Systems Confidential The Trusted Path to Accuracy
• Driver developers can debug/validate driver code against an accurate system
• Cycle accuracy without having to spend time booting Linux in CA model
• Each driver developer can independently debug their own driver code
Swap & Play
SoC Designer™ Plus virtual Prototype running with 100% accuracy
SoC Designer™ Plus virtual prototype running at 200+ MIPS
OS Boot Boot
Loader UART Driver
CP1
CP2
CP3
LCD Driver
Mali Driver
Boot Linux/Android in seconds and create check points for Firmware/Driver engineers
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Typical Virtual Prototype Flow
Start with example Fast Model project or FVP Sufficient for OS boot and initial software development
Develop Virtual Prototype features to support software programmers Incrementally build out Prototype capabilities
Easy deployment as new features completed
Export Fast Model subsystem to SystemC to extend Prototype and integrate with commercial EDA/ESL tools
Majority of software features and integration completed ahead of silicon Fast Prototype execution – software teams efficient
Advanced debug and visibility capabilities
Final optimisation and tuning against silicon
Power/performance tuning often the final stages of the project
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Fast, Accurate Programmer’s View Models for ARM IP Enables software development prior to silicon availability
Accelerates time-to-market, improves software quality
Suitable for driver, firmware, OS and application development
Export to Accellera SystemC and TLM 2.0 Integration with Synopsys, Cadence, Mentor Graphics
and Carbon Virtual Prototype Solutions
Integration with proprietary TLM simulators
Debug, Trace and Simulation Control Debug with DS-5 and ecosystem solutions
Scripting control with PyCADI
Comprehensive, extensible trace interface (MTI)
ARM Fast Models
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Robert Kaye
Technical Specialist, ARM
Development Solutions Group
Mobile: +44 7766 201275
Email: [email protected]