prof lei he ucla [email protected] ee 201c modeling of vlsi circuits and systems

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Prof Lei He UCLA [email protected] EE 201C Modeling of VLSI Circuits and Systems

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Page 1: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

Prof Lei He

UCLA

[email protected]

EE 201C Modeling of VLSI Circuits and Systems

EE 201C Modeling of VLSI Circuits and Systems

Page 2: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Chapter 5 Signal and Power IntegrityChapter 5 Signal and Power Integrity

On-chip signal integrityRC and RLC coupling noise

Power integrity

Static noise: IR dropDynamic noise: L di/dt noise

Chapter 6: Beyond die noiseIn-package decap insertionLow frequency P/G resonanceNoise for High-speed signaling

Page 3: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Reading on Signal IntegrityReading on Signal Integrity

RC couplingJ. Cong, Z. Pan and P. V. Srinivas, "Improved Crosstalk

Modeling for Noise Constrained Interconnect Optimization", ASPDAC, 2001.

RLC couplingJun Chen and Lei He, "Worst-Case Crosstalk Noise for

Non-Switching Victims in High-speed Buses", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 8, Aug. 2005.

To be covered by student presentation on May 14

Page 4: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Reading on Power IntegrityReading on Power Integrity

Static noise: IR drop S. Tan and R. Shi, “Optimization of VLSI Power/Ground (P/G)

Networks Via Sequence of Linear Programmings”, DAC’09

Dynamic noise: L di/dt noise Yiyu Shi, Jinjun Xiong, Chunchen Liu and Lei He, "Efficient

Decoupling Capacitance Budgeting Considering Current Correlation Including Process Variation", ICCAD, San Jose, CA, Nov. 2007.

Supplementary reading: H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Power Grid

Analysis Using Random Walks,” IEEE Trans. on CAD, 2005. Yiyu Shi, Wei Yao, Jinjun Xiong, and Lei He, "Incremental and

On-demand Random Walk for Iterative Power Distribution Network Analysis", ASPDAC 2009

Page 5: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

DAC 2009 Best Paper AwardSlides provided by X.D. Tan

Xiang-Dong Tan* and C.-J. Richard Shi

Optimization of VLSI Power/Ground (P/G) Networks Via Sequence of Linear

Programmings

Optimization of VLSI Power/Ground (P/G) Networks Via Sequence of Linear

Programmings

Page 6: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Outline of PresentationOutline of Presentation

Introduction and motivation

Review of existing algorithms

Relaxed P/G optimization procedure

New P/G optimization algorithm

Experimental results

Summary and future work

Page 7: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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IntroductionIntroduction

...

...

Pad

IR drops:

Voltage difference between power supply pads and individual cell instances.

Electro-migration:

Metal ion mass transport along the grain boundaries when a metallic interconnect is stressed at high current density. Mean Time to Failure (MTF) (Black’s equation):MTF A w l J E kTa ( , ) exp( / )2

Page 8: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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IntroductionIntroduction

A real industrial chip

#cell instances: 0.5M

#P/G resistors: 0.6M

Page 9: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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IntroductionIntroduction

Unrestricted IR drops and current densities in power / ground (P/G) network will cause malfunction and reliability problems in deep sub-micron IC chips. Increased cell delays (timing problem) increased resistance and even opens of P/G wires

Most of P/G designs are done manually.An aggressive design will cause more design iterations and

thus lead to increased design costs. Over conservative P/G network design wastes a lot of

important chip areas.

Page 10: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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MotivationMotivation

Two steps in P/G network design:P/G network construction (P/G routing).Determination of wire segment widths.

Determination of wire segment widths is hard to solve. The problem of determining wire segment widths in a P/G

network subject to reliability constraints is a constrained non-linear optimization problem.

Existing methods are not very efficient.based on the constrained nonlinear programming, can not handle large industrial P/G networks containing

millions of wire segments.

Page 11: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Outline of PresentationOutline of Presentation

Introduction and motivation

Review of existing algorithms

Relaxed P/G optimization procedure

New P/G optimization algorithm

Experimental results

Summary and future work

Page 12: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Algorithm ReviewAlgorithm Review

Assumption:Currents (average or maximum) of each individual cell

instance are known a priori before the optimization. computed by using power models of cells in a design

Existing optimization methods differ in the selection of variables.

Ohm’s Law

RV V

I

l

wii i

i

i

i

1 2 wi

li

Vi1 Vi2I i

Page 13: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Problem FormulationProblem Formulation

Min-area objective function: (Problem P)

IR drop constraints:

Electro-migration constraints:

Minimum width constraints:

f l wI l

V Vi ii B

i i

i ii B

( , )w V, I

2

1 2

V V V Vi i min maxor

| | | |I w V V li i i i i 1 2

wl I

V Vwi

i i

i i

1 2

min

Page 14: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Algorithm ReviewAlgorithm Review

Resistance values and branch currents are variables (Chowdhury and Breuer’87)

Both objective function and IR drop constraints are nonlinear

Solution: augmented Lagrangian method

Resistance values are variables (Dutta and Marek-Sadowska’89)

All the constraints are nonlinear Solution: feasible direction method

Nodal voltage and branch current are variables (Chowdhury’89)

Only objective function is nonlinear Solution: linear programming & conjugate gradient

Topology construction (Mitsuhashi and Kuh’92)

Page 15: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Outline of PresentationOutline of Presentation

Introduction and motivation

Review of existing algorithms

Relaxed P/G optimization procedure

New P/G optimization algorithm

Experimental results

Summary and future work

Page 16: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Relaxed P/G Optimization AlgorithmRelaxed P/G Optimization Algorithm

Relaxation: current directions are fixed. Nodal voltages and branch currents can be selected as

variables and be optimized separately.

Two optimization steps to solve P (Chowdhury’89) Solve for nodal voltages under fixed branch currents

(problem P1) Solve for branch current under fixed nodal voltages

(problem P2)

Advantage: All the constraints become linear and P2 is a linear

programming problem. P1 is a convex programming problem.

Page 17: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Problem P1Problem P1

Nonlinear Optimization Problem (P1)Objective function:

Subject to

fV V

i

i ii Bi( ) ,V

1 2

Iili2

V

Vi

i

V

Vmin

max

V Vi i1 2

I

l

wi

i

min

V Vi i1 2 0

I i

IR drop: Electro-migration: Minimum width:

| |V Vi i1 2 l i

Page 18: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Problem P2Problem P2

Linear Optimization Problem (P2)Objective function:

Subject to

f I ii

i B

( ) ,I

li2

V Vi1 i2

Minimum width: KCL law:

l

V Vw

i1 i2min

i iI

s Ii i

i B j ( )

0

Page 19: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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ObservationsObservations

Solution to P1: First transform P1 into a unconstrained nonlinear

optimization problem by adding a penalty function to the objective function.

Conjugate gradient method was used to solve the unconstrained nonlinear problem.

Disadvantage:Very slow convergence (almost linear)Conjugate gradient directions may deteriorate

Page 20: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Outline of PresentationOutline of Presentation

Introduction and motivation

Review of existing algorithms

Relaxed P/G optimization procedure

New P/G optimization algorithm

Experimental results

Summary and future work

Page 21: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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New Optimization AlgorithmNew Optimization Algorithm

Basic idea ---- linearize the nonlinear objective function in P1. Define

Linearized objective function:

v sign I V Vi i i i ( )( )1 2 0

fvi

ii B

( )| |

v

g ff

v vvi

ii B

i

ii Bi( ) ( )

( )( )

| | | |v v

v

vv v

0

00

0 02

2

Page 22: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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New Optimization AlgorithmNew Optimization Algorithm

The g(v) makes sense only if

Each product term, h(x) = c/x, in f(x) is a monotonic decreasing function.

g g f f( ) ( ) ( ) ( )v v v v0 0

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14-50

0

50

100

x

1/x and its first order Taylor's expansion at 0.04

h(x) = 1/x

H(x) = 1/x0 -1/(x0^2)*(x-x0)

Page 23: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Two Optimization ScenariosTwo Optimization Scenarios

(1) All the branch voltage drops increase.

(2) Only some branch voltage drops increase while others decrease or stay unchanged.

Combine two scenarios, we have

f f g g( ) ( ) ( ) ( )v v v v0 0 and

We always have

v v vi i i0 02 0 1 ( ) ,

v vi i0

g g f f( ) ( ) ( ) ( )v v v v0 0

Page 24: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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New Optimization Problem P3New Optimization Problem P3

Minimize Linearized objective function

Subject to

g VV V V V

V Vi

i ii B

i

i ii i

i B

( )( )

( )

2

10

20

10

20 1 2

V

Vi

i

V

Vmin

max

V Vi i1 2

I

l

wi

i

min

IR drop: Electro-migration: Minimum width:

| |V Vi i1 2 l i

Extra constraint:

sign I V V sign I V Vi i i i i i( )( ) ( )( )10

20

1 2

Page 25: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Sequence of Linear ProgrammingsSequence of Linear Programmings

New P/G Optimization Algorithm

1. Obtain an initial solution for a given P/G network

2. Build all the constraints for Problem P3

3. Solve P3 by sequence of linear programmings and record the result as

4. Build all the constraints based on of step (3) for the problem P2

5. Solve P2 by a linear programming and record the result as

6. Stop if improvement over previous result is small. Otherwise, goto step (2)

V , Ik k

V k 1

Ik 1

V k 1

Page 26: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Theoretical ResultTheoretical Result

Theorem: There exists a so that step (3) always converges to the global minimum in the convex problem space of P1.

xmin

x0x1

x2

x3

x4

Page 27: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Practical ConsiderationsPractical Considerations

Selection of At the beginning, solution space in P3 should be as

large as possible, so should be small. It should be close to 1 in later course of sequence of

linear programmings.

Numerical Stability Power networks are converted ground networks to

improve the numerical stability. Voltage drop in a ground network has to be

represented by by a power network with 5V supply voltage.

Power networks can be easily converted into ground networks.

2 5 10 5.

4 999975.

Page 28: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Outline of PresentationOutline of Presentation

Introduction and motivation

Review of existing algorithms

Relaxed P/G optimization procedure

New optimization algorithm

Experimental results

Summary and future work

Page 29: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Experimental ResultsExperimental Results

Sequence of linear programming and Conjugate gradient method were performed on 4 oversized p/g networks on SUN Untra-I with 169 MHz.

Ckt #node #bch New Algorithm Conjugate Gradient SP#it time rd% #it time rd%

p4x4 17 23 4 0.43 95.1 21 78.7 94.2 183.0p20x20 402 439 3 12.6 91.8 255 36147.1 90.8 2868.8p3x500 1502 1505 2 37.6 47.8 67 2135.4 26.8 >56.8g300x10 3002 3599 2 609.9 93.7 137 15192.1 78.4 >25.0

p100X100 10002 10199 4 1325.6 80.7 117 41716.8 48.9 >31.5

Page 30: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Comparison in CPU timeComparison in CPU time

p4x4 p20x20 p3x500 p300x10 p100x100

01

00

00

20

00

03

00

00

40

00

05

00

00

p4x4 p20x20 p3x500 p300x10 p100x100

CPU time bynew algorithm

CPU time byCG

Page 31: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Comparison in PerformanceComparison in Performance

p4x4 p20x20 3x500 g300x10 p100x1000

10

20

30

40

50

60

70

80

p4x4 p20x20 3x500 g300x10 p100x100

reduced to (%)by newalgorithm

reduced to (%)by CG

Page 32: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Experimental ResultsExperimental Results

1 2 3 4 5 61

1.005

1.01

1.015

1.02

1.025

1.03

# iteration

f(x)

/f_m

in(x

)scaled cost vs #iterations for new algorithm

The cost reduction versus the number of iterations (p4x4)

Page 33: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Experimental ResultsExperimental Results

0.4 0.6 0.8 13

3.5

4

4.5

5

5.5

6

6.5

7

xi

# o

f lin

ea

r p

rog

ram

min

gs

# of linear programmings vs xi

0.4 0.6 0.8 1424

426

428

430

432

434

436

438

440

442

xi

co

st

cost vs xi

Effect of on the performance of the new algorithm ( )xi

Page 34: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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Outline of PresentationOutline of Presentation

Introduction and motivation

Review of existing algorithms

Relaxed P/G optimization procedure

New optimization algorithm

Experimental results

Summary and future work

Page 35: Prof Lei He UCLA LHE@ee.ucla.edu EE 201C Modeling of VLSI Circuits and Systems

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SummarySummary

A new method based sequence of linear programmings was proposed to determine the widths of P/G network segments subject to reliability constraints.

We showed theoretically that new method is capable of finding solution as good as that by the best-known method.

Experimental results demonstrated that new method is orders-of-magnitude faster than the best-known method with constantly better solution quality.