prof.manoj kavedia ( 9860174297 ) ([email protected])...

Prof.Manoj Kavedia ( 9860174297 ) ([email protected])

` Combinational LogicChapter-3(Hours : 16 Marks:32 )( 12069 –Principle of Digital Technology)Combinational Logic Circuits3.1 Introduction to combinational logic circuit.3.2 Standard representation of Canonical forms (SOP & POS, Minterm, Maxterm) - Conversion between SOP & POS,Numericals based on above topic, Don’t care conditions.3.3 K – map reduction techniques and realization (only for SOP – 2, 3, 4 variables), Realization using K – map techniques of Half adder, full adder, Half subtractor, full subtractor, gray to binary, binary to gray converter, BCD to 7 – segmentdecoder using K-map.3.4 Multiplexer - Necessity of multiplexer, Types of multiplexers 2:1, 4:1, 8:1, 16:1 with realization, Multiplexer Tree, Study of MUX ICs 74150, 74151, 74152, 74153,74157, Applications of multiplexer.3.5 Demultiplexer - Necessity and Principle of Demultiplexer,Types and realization of De Mux 1:2, 1:4, 1:8, 1:16, Demux Tree, Application of Demux as decoder, Study of ICs 74138, 74139, 74154, 74155.

Combinational Logic CircuitCombination Logic circuits are made up from basic logic AND,

OR or NOT gates that are "combined" or connected together to produce more complicated switching circuits.

As combination logic circuits are made up from individual logic gates they can also be considered as "decision making circuits" and combinational logic is about combining logic gates together to process two or more signals in order to produce at least one output signal according to the logical function of each logic gate. Common combinational circuits made up from individual logic gates include Multiplexers, Decoders and De-multiplexers, Full and Half Adders etc.

Classification of Combinational LogicOne of the most common uses of combination logic is in

Multiplexer and De-multiplexer type circuits. Here, multiple inputs or outputs are connected to a common signal line and logic gates are used to decode an address to select a single data input or output switch. A multiplexer consist of two separate components, a logic decoder and some solid state switches, but before we can discuss multiplexers, decoders and de-multiplexers in more detail we first need to understand how these devices use these "solid state switches" in their design.

3

1

http://www.electronics-tutorials.ws/logic/logic_2.html

http://www.electronics-tutorials.ws/combination/comb_3.html

http://www.electronics-tutorials.ws/combination/comb_2.html




Standard Representation For Logical FunctionQ1.What is Variable and list the standard from of the Boolean FunctionAns.A Variable in complemented or uncomplemented form is known as Literal. Thus Boolean functions or equation are expressed in terms of literal. The values assumed by literal are in binary form. Any Boolean function can be expressed in two standard or canonical forms

1) Sum of product (SOP)2) Product of sum (POS)

If each term in SOP and POS form contain all the literal (variables) then these are known as standard SOP or standard POS form.

Q2.What SOP and How SOP Equations are represented?Ans.Standard SOP form

Each individual term in standard SOP form is called as minterm.

Y = PQR + PQR + PQR + PQR + PQR

This contain all the independent variable in SOP form which is obtained by first ANDing and then ORing them i.e. minterm or each term. Hence above equation has 5 minterm's PQR,PQR,PQR,PQR,PQR.

The possible number of minterm is equal to 2 to the power of number of variable i.e. if 3 variables are present in equation then there are 23 = 8 minterm's. Minterm with normal complemented variables is taken as ‘0’ and uncomplemented is taken as ‘1’.

2


3


Fig. Shows the truth able for 3 variables Boolean expressions.A B A Decimal equivalent Minterm(mi) Notation0 0 0 0 CBA m00 0 1 1 CBA m10 1 0 2 CBA m20 1 1 3 CBA m31 0 0 4 CBA m41 0 1 5 CBA m51 1 0 6 CBA m61 1 1 7 CBA m7

Using these notation we can write equation asY = m7 +m6+m5+m4+m3+m2+m1+m0

Y = m Σ (0,1,2,3,4,5,6,7)

Hence it is easy to used notation instead of minterm. The symbol Σ represent ORing of minterm.

Q3. Write truth table and equation in SOP form for following minterm.Y = m(1,3,6,7)

Ans : Minterm are M1,M2,M3,M4,M5,M6,M7. And equation has 3 variables. Hence the truth table is M table for minterm available in function write 1.

A B C Minterm Notations Y0 0 0 ABC M0 00 0 1 ABC M1 10 1 0 ABC M2 00 1 1 ABC M3 11 0 0 ABC M4 01 0 1 ABC M5 01 1 0 ABC M6 11 1 1 ABC M7 1

∴Y = ABC +ABC+ABC+ABC.

In general each row of truth table has functional value 1 described by minterm. The minterm is product of literal. The complement variable has value logic 0 and uncomplemented variable has value logic 1. Combining all the products term (minterm) constructed for the variable having value=1 i.e. minterm value = 1 by Boolean OR operation results in minterm canonical form.

4


Q4.What POS and How POS Equations are represented?Ans.Product of Sum( POS )

Product of sum method is also called as maxterm canonical form. Consider the equation

Y = (A+B+C)(A+B+C)(A+B+C)In this approach independent variables are ORing is followed by ANDing

of individual term. Each individual is called as maxterm. Number of maxterm depends on number of literal or variables i.e. if equation has three variables then there will be 23 = 8 maxterm. Each maxterm is represented by M i where subscript i is decimal equivalent of natural binary number. The maxterm with complemented variable is taken as ‘1’ and uncomplemented variable is taken as ‘0’.

Table shows possible maxterm for 3 variables equation.A B C Decimal equivalent Maxterm

MiNotation

0 0 0 0 M0 A+B+C0 0 1 1 M1 A+B+C0 1 0 2 M2 A+B+C0 1 1 3 M3 A+B+C1 0 0 4 M4 A+B+C1 0 1 5 M5 A+B+C1 1 0 6 M6 A+B+C1 1 1 7 M7 A+B+C

Using this notation above equation can be written asY= M2.M3.M4

= πM( i=2,3,6)= πM(2,3,6)

Where π is represented ANDing of maxtermY = (A+B+C)(A+B+C)(A+B+C)

Q5. Write truth table and equation in POS form for following minterm.Y = ( A+B+C)(A+B+C)(A+B+C)

Y = πM(2,3,6)

A B C Decimal equivalent

Maxterm Mi

Notation Y

0 0 0 0 M0 A+B+C 10 0 1 1 M1 A+B+C 10 1 0 2 M2 A+B+C 00 1 1 3 M3 A+B+C 0

5


1 0 0 4 M4 A+B+C 11 0 1 5 M5 A+B+C 11 1 0 6 M6 A+B+C 01 1 1 7 M7 A+B+C 0

In general each row of truth table represent that has functional (i.e. output) of logical 0. It is described by maxterm. Maxterm is sum of all the term. In maxterm representation complemented variable has value ‘1’ and uncomplemented variable has value ‘0’. Combining all the sum term(maxterm) constructed for variable having value logic 0 by Boolean AND operation results in maxterm canonical form.

Q6. Write truth table and equation in SOP form for following minterm.Y= πM(2,3,6,7)

Solution:A B C Decimal

equivalentMaxterm Mi Notation Y

0 0 0 0 M0 A+B+C 10 0 1 1 M1 A+B+C 10 1 0 2 M2 A+B+C 00 1 1 3 M3 A+B+C 01 0 0 4 M4 A+B+C 11 0 1 5 M5 A+B+C 11 1 0 6 M6 A+B+C 01 1 1 7 M7 A+B+C 0

Substitute 0 for all values represented in equation and then AND all maxterm from truth table

Y= (A+B+C) (A+B+C) (A+B+C) (A+B+C)

Q7.Describe Conversion of SOP to standard SOP formAns.The SOP form can be converted to standard SOP form by ANDing the term in the expression with term form by ORing the variable and its complement which are not present in that term.

Y= AB+AB+BCIn first term C is missing , AND it with(C+C)In second term B is missing, AND it with(B+B)In third term A missing, AND it with (A+A)

Y = AB(C+C)+AC(B+B)+BC(A+A) = ABC+ABC+ABC+ABC+ABC+ABC Y = ABC+ABC+ABC+ABC+ABC

Hence above equation is standard SOP equation.

Q8.Describe the step Conversion of standard SOP to POS

6


Ans.The Boolean expression in standard SOP form can be converted to standard POS as follows:1) Complement the Boolean expression in standard SOP form which will

contain missing minterm.2) Complement the individual missing minterm to get maxterm and by using

demorgan law change OR(sum) to AND (product).

Q9.Describe the Conversion of POS to standard POSAns.The POS form can be converted to standard POS form by ORing the terms in the expression with terms formed by ANDing the variable and its complement which are not present in that term.

Y = (A+B)(A+C)(B+C) to standard POS form.1st term A+B, C is missing, OR with it C.C2nd term A+C, B is missing, OR it with B.B3rd term B+C, A is missing, Or it with A.A

Y = (A+B+C.C)(A+C+B.B)(B+C+A.A) = (A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C)

Y = (A+B+C)(A+B+C)(A+B+C)(A+B+C) Hence above equation is in standard POS form.

Q10. Convert Y = ABC+ABC+ABC+ABC+ABC in standard SOP form to standard POS form.

Terms in the minterm are m1, m3, m4 , m5 , m7

1) Step1:Missing minterm are M0,M2,M6.Y = Σ(m0,m2,m6)Y = Σ(m0,m2,m6)

2) Step2: Complement equation using DMT.Y = π(M0,M2,M6)Y = (A+B+C)(A+B+C)(A+B+C)

Q11.Describe the Conversion of standard POS to Standard SOP formThe Boolean expression in standard POS form can be converted to

standard SOP form by following, following procedure1) Complement the Boolean expression in standard POS form which will

contain missing maxterm.2) Complement the individual missing maxterm to get the minterm and by

using demorgan(DMT) law change AND(product) to OR(sum).

Q12. Convert the Boolean expression SPOS to SSOPY= (A+B+C) (A+B+C) (A+B+C) = (M0,M3,M4)

Solution

7


1) Step1: Missing maxterm are M1,M2,M5,M6,M7. Y = πM1,M2,M5,M6,M7.

2) Step2 : Complement expression by DMT.Y = πM1.M2.M5.M6.M7 = ABC+ ABC+ ABC+ ABC+ ABC

Q13.List the different Boolean expression simplification techniqueAns.The SSOP or SPOS equation that has more than just a few products are difficult to reduce by algebraic method.

Karnaugh map or K-map method is used for simplification of Boolean expression. It is graphical method of representation. But if number of variables are more than 4 or exceeds 4 than it is difficult to solve using K-map than other following techniques are used.

1) Variable entered mapping2) Quine MC cluskey method

Hence to solve any Boolean expression there are four methods out of Which two are listed above and other two are

1) Algebraic method2) K-map method.

Q14.What is Karnaugh or K-map ?Describe Ans. The Karnaugh map, like Boolean algebra, is a simplification tool applicable to digital logic. Maurice Karnaugh, a telecommunications engineer, developed the Karnaugh map at Bell Labs in 1953. Karnaugh map or K-map method is used for simplification of Boolean expression. It is graphical method of representation

k-map for two, three and four variable is shown in fig. In an n-variable K-map there are 2n cells. Each cell corresponds to one of the combination of n-variables. In k-map one cell represent one minterm or maxterm. In k-map the variables and all possible values of the variable are indicated to identify cell. GRAY code is used for identification of cell.

Sample Two , Three and Four Variable KMaps 0 1

0021132 variable k-map (n=2) F(AB)

00 01 11 10

00264113753 variable k-map (n=3) F(ABC)

00 01 11 1000041280115139113715111012614104-Variable K-Map

(n=4)

8


Q15.Describe Two Variable K Maps ?Ans.2-variable k-map: Table shows truth table for 2 variable equationIn 2 variable A & B has four combination corresponds to 4-minterm (or maxterm) and needs four location in k-map. These four locations corresponds to 4 rows of truth table.

A ‘1’ is placed in those boxes where minterm are included (Y=1) and 0 is included where the minterm are absent or excluded (Y=0). Hence for above truth table the k-map is

Q16.Describe Three Variable K Maps ?Ans.3 variable k-map : Truth table for three variable k-map is as shown. For three variable equation k-map will have 8 cells as shown(23 = 8). A ‘1’ is placed in those boxes where minterm are included (Y=1) and 0 is included where the minterm are absent or excluded (Y=0). Hence for above truth table the k-map is

K Map For 3 Variable 00 01 11 10

0 ABC ABC ABC ABC1 ABC ABC ABC ABC

Truth TableA B C Y0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 11 1 0 01 1 1 1

In this case also enter 1 for minterm's whose Y=1 and 0 for the maxterm's

00 01 10 11

0 0 1 0 11 1 0 1 1

Truth TableA B Y0 0 00 1 11 0 01 1 1

Minterms

K- Map Entry 0 1

0 AB AB1 AB AB

0 1

0 0 11 0 1

9


Q17.Describe Three Variable K Maps ?Ans. 4 variable k-map : Table shows truth table for 4-variable Boolean expression. For 4 variable equation k-Map has 16 cells i.e. 24 = 16A ‘1’ is placed in those boxes where minterm are included (Y=1) and 0 is included where the minterm are absent or excluded (Y=0). Hence for above truth table the k-map is

Q18.Describe the terms Minterm and MaxtermAns.MintermA product in as SSOP is called as Minterm.A minterm is a Boolean expression resulting in 1 for the output of a single cell, and 0s for all other cells in a Karnaugh map, or truth table. If a minterm has a single 1 and the remaining cells as 0s, it would appear to cover a minimum area of 1s.

Truth Table ABCDY00001000110010000110010010101101100011101000110011101011011011001110111110111110

K-Map for 4-Variable is as shown 00 01 11 10

00ABCDABCDABCDABCD01ABCDABCDABCDABCD11ABCDABCDABCDABC

D10ABCDABCDABCDABCD

K Map 00 01 11 10

001111011111110000100011

10


The example above left shows the minterm ABC, a single product term, as a single 1 in a map that is otherwise 0s. Another minterm A'BC' is shown above right. The point to noted is that the address of the cell corresponds directly to the minterm being mapped. That is, the cell 111 corresponds to the minterm ABC above left. Above right we see that the minterm A'BC' corresponds directly to the cell 010. A Boolean expression or map may have multiple minterms.

MaxtermA product in as SPOS is called as Maxterm.A maxterm is a Boolean expression resulting in a 0 for the output of a single cell expression, and 1s for all other cells in the Karnaugh map, or truth table. The illustration above left shows the maxterm (A+B+C), a single sum term, as a single 0 in a map that is otherwise 1s. If a maxterm has a single 0 and the remaining cells as 1s, it would appear to cover a maximum area of 1s.

The maxterm is a 0, not a 1 in the Karnaugh map. A maxterm is a sum term, (A+B+C) in our example, not a product term.

Therefore (A+B+C) is mapped into the cell 000. For the equation Out=(A+B+C)=0, all three variables (A, B, C) must individually be equal to 0. Only (0+0+0)=0 will equal 0. Thus we place our sole 0 for minterm (A+B+C) in cell A,B,C=000 in the K-map, where the inputs are all0 . This is the only case which will give us a 0 for our maxterm. All other cells contain 1s because any input values other than ((0,0,0) for (A+B+C) yields 1s upon evaluation.

Q19.List the Procedure for placing a minterm in a K-mapAns. Following are the steps to Place Minterm in KMAP

• identify the minterm (product term) term to be mapped. • Write the corresponding binary numeric value. • Use binary value as an address to place a 1 in the K-map • Repeat steps for other minterms (P-terms within a Sum-Of-Products).

11


Q20.List the Procedure for placing a maxterm in a K-mapAns. Following are the steps to Place Maxterm in KMAP

• Identify the Sum term to be mapped. • Write corresponding binary numeric value. • Form the complement • Use the complement as an address to place a 0 in the K-map • Repeat for other maxterms (Sum terms within Product-of-Sums expression).

Q21.List the procedure for writing the Sum-Of-Products reduced Boolean equation from a K-map: Ans : The procedure for writing the Sum-Of-Products reduced Boolean equation from a K-map:

• Form largest groups of 1s possible covering all minterms. Groups must be a power of 2.

• Write binary numeric value for groups. • Convert binary value to a product term. • Repeat steps for other groups. Each group yields a p-terms within a Sum-Of-

Products.

Q22.List the the procedure for writing the Product-Of-Sums Boolean reduction for a K-map: Ans.The procedure for writing the Product-Of-Sums Boolean reduction for a K-map:

• Form largest groups of 0s possible, covering all maxterms. Groups must be a power of 2.

• Write binary numeric value for group. • Complement binary numeric value for group. • Convert complement value to a sum-term. • Repeat steps for other groups. Each group yields a sum-term within a Product-Of-

Sums result.

Q23.Describe the terms PAIR, QUAD and OCTECTS related to KMAPSAns.Simplification of logical function with k-map is based on the principle of combining terms in adjacent cells. Two cells are said to be adjacent if they differ in only one variable. Also left two cells and right two cells are adjacent

Similarly simplification of logical function is achieved by grouping adjacent 1’s or 0’s in group of 2i where i= 0,1,2,3 i.e. up to the number of variables.

PAIR : Grouping two adjacent ones: If there are two adjacent ones in k-map these can be grouped together and the resulting term will have one literal less than original two terms (minterm) i.e. Pairs.

12


QUAD : Grouping adjacent 4 one’s:

A quad is group of four 1’s that are1) Horizontally or vertically adjacent.2) 1’s may be end to end.3) 1’s in form of a square.In quad group two variable and their complement are eliminated.

00 01 11 100111110000 Y = C

00 01 11 10000000011111110000100000 Y= CD

00 01 11 1000010001010011010

0100100 Y = AB

00 01 11 100110011100 Y =

00 01 11 10000000010110110110100000 Y=

00 01 11 1000011001011011000

0100000 Y =

00 01 11 100101011010

Y= AB+AB

00 01 11 100110010000 Y=AC

00 01 11 100000010110

Y = BC

00 01 11 1000110001001111010010010

0Other possibilities

00 01 11 1000010001011111000010011

1Other possibilities

13


OCTECT: Grouping of adjacent 8 one’s: Other than pair there is one more group of adjacent 1’s i.e. the octet. This is a group of 8- 1’s as shown in fig. An oct4et group eliminates three variables and its complement.

Overlapping Groups: When there are pairs, quads, octet in a k-map. There is possibility that these group overlap i.e. it is possible to combine a particular 1 in k-map in more than one way.

Q24.Describe the term ROLLING , Redundant Group, Corner related to KMAP

Ans. Rolling the map :Rolling of map is also possible as shown in fig. In k-map rolling is done so that the left side touches the right side. If you see carefully it is two pair forming quad.

Other possibilities

00 01 11 1000 0 0 0 001 1 1 1 111 1 1 1 110 0 0 0 0

Y=

00 01 11 1000 0 0 0 001 1 1 1 111 1 1 1 110 0 0 0 0

Y=

00 01 11 1000 1 1 1 101 1 1 1 111 1 1 1 110 1 1 0 0

Y=

00 01 11 100 1 1 1 11 0 1 0 0

Y =

00 01 11 1000 0 0 0 001 1 1 1 111 1 1 1 110 0 0 0 0

Y=

00 01 11 1000 1 1 0 101 1 1 1 111 1 1 1 110 1 1 0 0

Y=

00 01 11 100 1 0 0 11 1 0 0 1

Y=

00 01 11 1000 1 0 0 101 0 0 0 011 0 0 0 010 1 0 0 1

Y=

00 01 11 1000 0 1 1 001 1 0 0 111 1 0 0 110 0 1 1 0

Y=

00 01 11 1000 1 1 1 101 0 0 0 011 0 0 0 010 1 1 1 0

Y=

00 01 11 100 1 0 0 11 0 0 0 0

Y=

00 01 11 1000 1 0 0 101 1 0 0 111 0 0 0 010 0 1 0 0

Y=

00 01 11 1000 0 0 1 001 1 0 0 111 0 0 0 010 1 0 1 1

Y=

00 01 11 1000 1 0 0 101 1 0 0 111 1 0 0 110 1 0 0 1

Y=14


Eliminate redundant groupAfter you finished encircling groups, eliminate any redundant group.

This is a group whose 1’s are already grouped. In fig. All pairs are grouped, then if you form quad, already all 1’s of quad

are grouped in pair. Therefore quad is redundant it should be eliminated.

Corner

Fold up the corners of the map below like it is a napkin to make the four cells physically adjacent.

The four cells above are a group of four because they all have the Boolean variables B' and D' in common. In other words, B=0 for the four cells, and D=0 for the four cells. The other variables (A, B) are 0 in some cases, 1 in other cases with respect to the four corner cells. Thus, these variables (A, B) are not involved with this group of four. This single group comes out of the map as one product term for the simplified result: Out=B'C'

Q25. Find grouping for following k-map?

00 01 11 10

00 0 0 1 001 1 1 1 0

11 0 1 1 110 0 1 0 0

00 01 11 10

00 0 0 1 001 1 1 1 1

11 0 1 1 110 0 1 0 0

00 01 11 1000 0 0 0 001 0 0 1 011 1 1 1 110 0 1 1 1

15


Q26.List the Rules for simplification of k-mapsAns.Rules for Simplification of KMAP2 variables k-maps1) Any two in adjacent is one then k-map may be k-map combined to represent

single variable.2) Any single 1 on map represent the AND function (product) of two variables.3) The total expression corresponding to 1’s of map the ORed function(sum) of

various variable term which covers all 1’s in the map

3 variable k-maps1) A group of 4-adjacent 1’s can be combined to represent a single variable.2) A group of 2-adjacent 1’s can be combined to represent 2 variable.3) Any single 1 on map represent three variable.4 variable k-map1) Grouping of 8-1’s represent a single variable term.2) Group of 4- 1’s represent two variables term.3) Group of 2-1’s represent 3 variable term.4) Individual 1’s represent 4-variable terms.

Notes1) Top row is considered to be adjacent to bottom row.2) Extreme left hand row is adjacent to the extreme right hand row.3) Always try to overlap group of possible i.e. try to make largest group.4) Sometimes take care that all the 1’s should not overlap.

Q27.Simplify the FollowingAns.

16


Circuit Diagram for the Solution obtained

Q28. Simplify the following Boolean expression:

1) f(A,B,C) = πm(0,2,4,6,7)Solution:

2. f(A,B,C,D) = πm(0,1,5,7,8,9,12,13,15)Solution:

A B C Y0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 11 0 1 01 1 0 11 1 1 1

AB 00 01 11 1000 1 1 1 101 0 0 1 0

Y =

A B C D Y0 0 0 0 10 0 0 1 10 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 10 1 1 0 00 1 1 1 11 0 0 0 11 0 0 1 11 0 1 0 01 0 1 1 01 1 0 0 11 1 0 1 11 1 1 0 01 1 1 1 1

00 01 11 1000 1 1 1 101 1 1 1 111 0 1 1 010 0 0 0 0

Y=

17


2. f(A,B,C,D) = πm(0,1,2,4,5,8,9,10)Implementation using NAND and OR gate after simplification.Solution:

Q29. Simplify1) f(A,B,C,D) = πm(1,3,4,5,6,7,8,9,13,15) Implement using NOR gateSolution:

AB 00 01 11 1000 1 0 1 001 0 0 0 011 0 0 0 110 1 0 1 1

f=2) f(A,B,C,D) = πM(4,5,6,7,8,12)Solution:

AB 00 01 11 1000 1 0 0 001 1 0 1 111 1 0 1 110 1 0 1 1

Example Based on KMAPS

Realizations Using KMAP – Arithmetic Circuits

A B C D Y A B C D Y0 0 0 0 1 1 0 0 0 10 0 0 1 1 1 0 0 1 10 0 1 0 1 1 0 1 0 10 0 1 1 0 1 0 1 1 00 1 0 0 1 1 1 0 0 00 1 0 1 1 1 1 0 1 00 1 1 0 0 1 1 1 0 00 1 1 1 0 1 1 1 1 0

00 01 11 1000 1 1 0 101 1 1 0 111 0 0 0 010 1 0 0 1

Y=

18


Q30.Design Half Adder ? Draw Circuit Using Basic GatesAns. A combinational logic which performs two bit addition is called as HALF ADDER. Rules for addition are

1) 0 + 0 = 02) 0 +1 =13) 1 + 0 =14) 1 + 1 =1

Block Diagram Truth Table

19


Sum Carry

KMAPSolving KMAP For Sum and Carry

Sum= AB + AB = A + B

Carry = AB

Hence half adder adds two bit at a time. The half adder can be constructed using a AND gate and XOR gate. The output of EX-OR gate gives the sum and the output of And gate gives the carry. The circuit of half adder is as shown we can analyze this circuit for four inputs condition and result are tabulated into truth table as shown.

Realization Half Adder using gates

Half Adder Using Basic GatesHalf Adder

Circuit

20


Q31.Draw Half Adder Circuit using NAND GateAns.

Half Adder Using NAND Gate

Q32. Design FULL Adder ? Draw it circuit diagram suing Basic GatesAns. A combinational logic circuit that performs arithmetic sum of three input bit is called as Full adder. Full adder has three input A, B, Cin where Cin is carry from previous stage and TWO outputs sum(s) and carry (Co) where Co is output carry for next stage. Fig. Shows truth table and block diagram of full adder.


21


KMAPS For Sum and Carry Expression for SumSum

Carry

Expression For Carry

When adding two binary numbers (bits) we may get a carry from one column to the next. To add binary number electronically we need a circuit that can handle 3 bits at a time. This can be done by using a connecting two half adders and an OR gate as shown.

For instance suppose A=1, B=1 and C=1first half adder gives a carry of 1 and a sum of 0.

The second half adder gives a carry of 0and sum of 1. This results in final output of carry = 1 and sum=1.

Implementation Using Gates Circuits of Full Adder

22


Q33.Draw Circuit Diagram of Full adder Using two Half AddersAns.

Block Diagram of Full Adder using Half Adder

Circuit Diagram of Full Adder using Half Adder

Q34. Design Half Subtractor ? Draw Circuit Using Basic GatesAns. A Combinational logic circuit for the subtraction of two bit is known as half Subtractor. This combinational logic circuit subtracts two bits and produce their difference and borrow. Fig. Shows truth table and block diagram of half Subtractor.

23


(b) Truth TableKMAPS for Half SubtractorDifference Borrow

Equation for difference Equation for borrow

Diff = AB+AB Borrow = AB

Form truth table it is clear that the difference output is zero whenever input A & B are same and difference output is 1 whenever A and B are different. Hence we can use EX-OR gate to produce difference output.

The borrow is one only when A=0 and B=1 we can get the borrow output by ANDing A and B. Fig. Shows circuit diagram for half subtractor

Disadvantages of half Subtractor is that it does not take into account borrow from previous stage.

H.S

Difference (D)(D)

Borrow(B)(D)

H.S.

24


Realization of Half Subtractor

Basic Gates Circuit Diagram

Q35.Draw Half Subtractor using Half Subtractor

Ans.

Fig.Half Subtractor using NAND GateQ36.Design FULL Adder ? Draw its circuit diagram using basic GatesAns. A combinational logic circuit that performs subtraction between two bit number and taking into account the borrow by lower significant stage.

The three inputs are A, B, Bin where Bin is borrow by lower stage and two outputs D and Bout. Bout is last stage borrow. Fig. Shows truth table and block of full subtraction.

25


Block Diagram

Truth Table

KMAPS for Difference and Borrow

Difference Equation for Difference

F.S.Difference(D)

Borrow(B)

Bin

26


Borrow Equation for Borrow

Equation for borrowBo = ABBin + ABBin + ABBin + ABBin

Bo= ABin +BA + BBin

Equation for difference

Diff = ABBin + ABBin + ABBin + ABBin

Diff = A ⊕ B ⊕ Bin

A full Subtractor is a circuit that performs the subtraction between two bits taking into accounts that a 1 has been borrowed for the subtraction of previous column.

The full Subtractor circuit can be constructed using 2 half Subtractor and a OR gate as shown below. This circuit has 3 inputs and 2 outputs. Input A & B represent the bit to be subtracted and Bin represents borrow required for the subtraction of lower column.

Realization Using Gates

27


Q37.Draw logical Circuit diagram of FULL adder using Half AdderAns.

Code ConvertorQ38.Design Binary to Gray Code Convertor?Ans.Fig.Shows truth table for Binary to gray code converter

Truth table

28


Kmaps For G3 output For G2 Output

For G1 output For G0 output

Boolean Expressions areG3 = B3G2 = B3B2 + B3B2G1 = B2B1 + B2B1G0 = B1B0 + B1B0

Implementation of Binary to gray code converter

29


Q39.Design Gray to Binary Code Convertor?Ans.Input is G3G2G1G0 as 4 bit Gray input and B3B2B1B0 as Output.FigShows truth table of 4 Bit Gray to Binary code converter

KMAPS– Gray to Binary Code Converter

Kmap for B3 Expression for B3

B3 = G3


30



Kmap for B0

31


Expression for B0

There fore the Expression areB3 = G3B2 = G2 + G3B1 = G1 + G2 + G3B0 = G0 + G1 + G2 + G3

Realization Using Gates

32


Q40.Design Binary to BCD Code Convertor?Ans. In this design B3B2B1B0 are the input and D4D3D2D1D0 are the output Fig shows the truth table for the same

Kmaps for Binary to BD code converterKmap and Expression for D4 Kmap and Expression for D3

33


Kmap and Expression for D2 Kmap and Expression for D1

Kmap for D0

Realization of Binary to BCD converter

34


Q41.Design BCD to Excess-3 Code Convertor?Ans.Input for BCD to excess-3 are D3D2D1D0 and output is E3E2E1E0.Fig Shows the truth table for BCD to Excess-3 Code Converter

Kmaps and Boolean Expression for BCD to Excess-3 Code Converter

KMap and Expression for E3 Kmap and Expression for E2

KMap and Expression for E1 Kmap and Expression for E0

35


Realization of BCD to Excess-3 Code Converter

Multiplexers

Q42.Define Multiplexer Ans.Multiplexer ( Data Selector)

Multiplex means many into one. A multiplexer is a logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output. The selection of the desired data input depends on the control inputs. The data input selected is controlled by the set of the select inputs. Basically it acts as digitally controlled multiposition switch.

Hence we can say that a multiplexer (MUX) is a digital switch which connects data from one of “N” sources to the output. A number of select inputs determine which data source is connected to the output. Total number input for N select are 2N.ie if a Mux has 2 select Lines then 22 = 4 data input are there for the mux.

36


Block Diagram

Q43.State the Necessity of Using MultiplexerAns. Multiplexer is used in the electronic systems, where the digital data is available on more than one lines, to route this data over a single line.Hence we require a circuit which select one of the many inputs at a time. Such circuit should have many inputs, One output and some select inputs.Multiplexer improves the reliability of the digital system because it reduces the number of external wired connections.

Q44.Draw 4:1 Mux ? and Describe its operationAns.Fig Shows Block Diagram of 4:1 Mux .

1. It has 4 input D3D2D1D0 , 2. Two select lines(S1S0) and 3. One data out put Line Y

S2 S1 Y0 0 Do0 1 D11 0 D21 1 D3

Truth Table

Do

D1

D2

D3

Y

S1 S2

Do

D1

D2

D3

Y

S1 S2

37


Expression for 4:1Mux Y = SoS1Do + SoS1D1 + SoS1D2 + SoS1D3

38


Fig. 4:1 Multiplexer

Operation :When data is applied to data input depending upon select signal data is

switched to output Y1.When S1=0 ,S0=0 data on Y output is from data line D0 ie Y = D02.When S1=0 ,S0=1 data on Y output is from data line D1 ie Y = D13.When S1=1 ,S0=0 data on Y output is from data line D2 ie Y = D24.When S1=1 ,S0=1 data on Y output is from data line D3 ie Y = D3

Q45.Draw the Logical circuit diagram of 8:1 Mux with Control Signal?Describe its operation.Ans. Fig Shows Block Diagram of 8:1 Mux.

1. It has 8 input D7--D0 2. Three select lines(S3S1S0) and 3. One data out put Line Y4. E is the Strobe or Select or Control line.

39


Block Diagram Truth TableOperation

1. When the Strobe Signal or Control signal is made Low(0) , the multiplexer get disabled and output becomes logic 0 (Y = 0) even if data is connected to any input.

2. For Enabling the MUX the control or Strobe input is to be made High.3. When data is applied to data input depending upon select signal data is

switched to output Y4. When S2 =0 ,S1=0 ,S0=0 data on Y output is from data line D0 ie Y = D05. When S2 =0, S1=0 ,S0=1 data on Y output is from data line D1 ie Y = D16. Similarly When S2=1 S1=1 ,S0=1 data on Y output is from data line D7

ie Y = D7

Expression for 8:1 Mux

Y = E.(S2S1S0.D0 + S2S1S0.D1 + S2S1S0.D2 + S2S1S0.D3 + S2S1S0.D4 + S2S1S0.D5 + S2S1S0.D6 + S2S1S0.D7 )

Logical Circuit Diagram of 8:1 Mux

40


Q.DraQ46.Draw Block Diagram , Logical Diagram of 16:1 MUx, Also write its Boolean expressionAns. Fig Shows Block Diagram of 16:1 Mux.

1. It has 16 input D15--D0 2. Three select lines(S4S3S1S0) and 3. One data out put Line Y4. E is the Strobe or Select or Control

line.

Block Diagram

Truth table

Operation1. When the Strobe Signal or Control signal is made Low(0) , the

multiplexer get disabled and output becomes logic 0 (Y = 0) even if data is connected to any input.

2. For Enabling the MUX the control or Strobe input is to be made High.3. When data is applied to data input depending upon select signal data is

switched to output Y4. When S3=0, S2 =0 ,S1=0 ,S0=0 data on Y output is from data line D0 ie

Y = D05. When S3=0 ,S2 =0, S1=0 ,S0=1 data on Y output is from data line D1 ie

Y = D16. When S3=1 ,S2 =0, S1=0 ,S0=0 data on Y output is from data line D8 ie

Y = D8

41


7. Similarly When S3=1,S2=1 S1=1 ,S0=1 data on Y output is from data line D15 ie Y = D15

Boolean Expression for 16: 1 MuxY = E.(S3S2S1S0.D0 + S3S2S1S0.D1 + S3S2S1S0.D2 + S3S2S1S0.D3 +

S3S2S1S0.D4 + S3S2S1S0.D5 + S3S2S1S0.D6 + S3S2S1S0.D7 + S3S2S1S0.D8 + S3S2S1S0.D9 + S3S2S1S0.D10 + S3S2S1S0.D11 + S3S2S1S0.D12 + S3S2S1S0.D13 + S3S2S1S0.D14 + S3S2S1S0.D15 )

Logical Circuit Diagram of 16:1 Mux

42


Q47.List IC for Multiplexer Ans

Sr.No IC. No Description Output1 74157 Quad 2:1 Mux Same as Input2 74158 Quad 2:1 Mux Inverted Output3 74153 Dual 4:1 Mux Same as Input4 74352 Dual 4:1 Mux Inverted as Input5 74151 8:1 Mux Complementary Outputs6 74150 16:1 Mux Inverted Outputs

Q48.Draw the Pin diagram of IC 74153 and DescribeAns. IC 74153 is a Dual 4:1 MUX.

1. It has two four line inputs I0A,I1A,I2A,I3A and I0B,I1B,I2B,I3B2. There are two outputs ZA & ZB. 3. Two strobes EA & EB for section 0 and section 1 respectively 4. Two Select lines S1 & S0 are common for both the sections. 5. To enable the particular section the strobe input of that section must be

held active low.

Pin diagram

Truth Table

74153

43


Internal Logical Diagram

Q49.Draw the Pin diagram of IC 74150 and DescribeAns. IC 74150 is a 16:1 MUX.

1. It has 16 data inputs E0-E15 and four select lines A,B,C,D. 2. The output “W” of this circuit is the inversion of the data input selected. 3. An input line Dn. is selected corresponding to decimal number N

representing D,C,B,A.4. G is the strobe signal which is to be maintained LOW

Pin diagram

44


Truth Table

Logical Symbol

Q50.Draw the Pin diagram of IC 74151 and DescribeAns.IC 74151A - 8:1 Mux

1. It has 8 data input D7 to D02. Three (3) select inputs C,B,A 3. Two (2) outputs Y & W ( Complementary outputs)4. To enable the MUX the strobe must be held active low.

Pin DiagramLogical

DiagramTruth Table

45


Q51.What is Multiplexer Tree? State its NecessityAns.Maximum input mux IC available is 16 input to 1 output i.e. 16:1 Mux is available. Some time it is required to have multiplexer more than 16 input for example 32:1 or 64:1 or 256:1. This requirement is meet by forming a tree like connection of 16:1 mux or 8:1 or 4:1 mux i.e. available. This is achieved with help of enable/strobe (G) input of mux. Following example shows some of such examples.

Q52. Design of mux tree 32:1 mux using 16:1 Ans.Truth Table of 32:1 Mux

Truth table:

MUX 1 selected

S4 S3 S2 S1 S0 Y0 0 0 0 0 D00 0 0 0 1 D10 0 0 1 0 D20 0 0 1 1 D3--- --- --- --- --- --0 1 1 1 1 D15

MUX 2 selected

1 0 0 0 0 D161 0 0 0 1 D171 0 0 1 0 D19--- --- --- --- --- --1 1 1 1 1 D31

Fig.32:1 Mux Tree Using 16:1

46


For S4 = 0 Lower multiplexer is enable which transfer any of 16 input to output Y depends on DCBA select input. At this time S4 for MUX2 is high it is inactive ( S4 = 1 ).

When S4 = 1 or made high upper mux or mux1 is inactive disabled whereas lower operates(D2) operates as 16:1 mux and transfer any of 16 inputs to one output Y depending on select input.

Output of both mux are ORed to get 1 output hence 32:1 mux can be implemented.

Q53.Design 16:1 Mux using 8:1 MuxAns.

MUX 1 selected

S3 S2 S1 S0 Y0 0 0 0 D00 0 0 1 D10 0 1 0 D20 0 1 1 D3--- --- --- --- --0 1 1 1 D7

MUX 2 selected

1 0 0 0 D81 0 0 1 D91 0 1 0 D10--- --- --- --- --1 1 1 1 D15

47


Fig. Mux 16:1 using 8:1For S3 = 0 right multiplexer is enable which transfer any of 8 input to

output Y1 depends on DCBA select input. At this time S3 for MUX2 is high it is inactive ( S3 = 1 ).

When S3 = 1 or made right mux or mux1 is inactive disabled whereas left operates(M2) operates as 8:1 mux and transfer any of 8 inputs to one output Y2 depending on select input.

Output of both mux are ORed to get 1 output hence 16:1 mux can be implemented.

Q54. Design 16:1 Mux Tree using 4:1 MuxAns. Truth table 16:1 Mux

S3 S2 S1 S0

Select MUX D0 input

0 0 0 0--- --- -- -- D1 1st 4 output0 0 1 1

Select MUX D1 input

0 1 0 0--- --- -- -- D2 2nd 4 output0 1 1 1

Select MUX D2 input

1 0 0 0--- --- -- -- D2 3rd 4 output1 0 1 1

Select MUX D3 input

1 1 0 0--- --- -- -- D3 4th 4 output1 1 1 1

48


When S3S2S1S0 is 0000 then Do input of the First Mux is selected since S3S2S1S0=0000 and Since S3S2=00 the Do input of the MUX5 is select to transfer at the outputSimilarly when S3S2 =01 then D1 input of the MUX D5 is selected for the output

when S3S2=10 then D2input of the MUX D5 is selected for the output when S3S2=11 then D3 input of the MUX D5 is selected for the output

But for all S3S2 input the range for the S2S1= 00 - to – 11. Therefore 16 input of the input multiplexer are transferred to the output through 4 input of the output multiplexer(MUX5)

Q55. Design 8:1 Mux Tree using 4:1 MuxAns. The cascading of two 4:1 multiplexer results in 8 : 1 multiplexer as shown in Fig.

1. There are in all eight data inputs (D7 through D0),2. The select lines S1 and S0 of both 4:1 multiplexers are connected in

parallel whereas a third select input s2 is used for enabling one multiplexer at a time.

3. S2 is connected directly to the enable (E) terminal of MUX-1 whereas S2 is connected to the enable terminal of MUX-2.

8:1 Mux Tree using 4:1 MuxTruth Table

Q56. Implementation of Boolean Expression Using Multiplexer 1. F(d,c,b,a) = Σm(2,4,5,7,10,14)2. F(c,b,a) = Σm(0,2,4,6)

Ans.General step for Implementation 1. Depending on the function see the variable required i.e. in above

equation there are 4 variables

49


2. In truth table write 1’s for all minterm the equation 3. Connect all the input whose output are 1’s to logic High i.e. +5v supply4. Remaining input are connected to logic 0 i.e. grounded.5. Then verify the truth table.

Equation 1 : F(d,c,b,a) = Σm(2,4,5,7,10,14) Truth Table for the above equation Circuit diagram : Mux needed is of 4 select inputs

D C B A Y O/P0 0 0 0 D0 00 0 0 1 D1 00 0 1 0 D2 10 0 1 1 D3 00 1 0 0 D4 10 1 0 1 D5 10 1 1 0 D6 00 1 1 1 D7 11 0 0 0 D8 01 0 0 1 D9 01 0 1 0 D10 11 0 1 1 D11 01 1 0 0 D12 01 1 0 1 D13 01 1 1 0 D14 11 1 1 1 D15 0

( refer Diagram on Page A /Ch3)Equation 2 : F(c,b,a) = Σm(0,2,4,6) Truth Table

Circuit diagram : Mux needed is of Three select inputD C A Y O/P0 0 0 D0 10 0 1 D1 00 1 0 D2 10 1 1 D3 01 0 0 D4 11 0 1 D5 01 1 0 D6 11 1 1 D7 0

( refer Diagram on Page A /Ch3)Fig: Mux diagram for Boolean expression

50


Q57.State Advantages and application of the MultiplexerAns. Following are the Advantages of Multiplexer

1. Simplification of the logic expression is not required2. It minimize the IC package count 3. Logic design is simplified

For using mux as a logic element , either the truth table or one of the standard form of the logic expression must be available. The design procedure is given below

1. Identify the decimal number corresponding to each minterm in the expression

2. The input lines corresponding to these numbers are to be connected to logic “1”

3. All other input lines are connected to logic “0”4. The inputs are applied to the select input

Application of Multiplexer1. Data Routing 2. Logic Function generator3. Control Sequencer4. Parallel-to-serial convertor5. Boolean Expression Implementation6. Used in ADC /DAC 7. In designing of Combinational Logic Circuits8. Used in data logger and Dataacquition System

1.Data routing: Multiplexers can be used to route data from one of several sources to one destination.2.Logic function generator: It can also be used to implement logic functions in sum-of-products form directly from a truth table without the need for simplification. The logic variables are used as the select inputs and each data input is connected permanently HIGH or LOW. 3.Control sequencer: A multiplexer can also be used as a part of control sequencer.4.Parallel-to-serial converter: Digital systems that process data in parallel form take very less time. In order to transmit the information over long distances, the parallel arrangement is undesirable as it requires a large number of transmission lines.5.Boolean Expression Implementation : Multiplexer can be used for implementation of Boolean Expression since it reduces hardware and number of connection which makes debugging easy.

51


6.Used in ADC/DAC : For increasing number of input and Outpuy. Example is ADC0808 , 0809Therefore data in parallel form is converted to serial for using multiplexers.

DemultiplexerQ59.What is Demultiplexer?Explain 1:4 Demultiplexer?Ans.Demultiplexer ( Data Distributor ) : Demux

Demultiplexer is exactly reverse to that of MUX. Demultiplexer means “1” into many. A demultiplexer is a logic circuit with one input and many outputs. It accepts a single input and distributes it over several output depending upon the control inputs.

It performs Function opposite to Multiplexer. Types of Demultiplexer are 1. 1 line - to - 4 line (1:4 ) Demultiplexer2. 1 line - to - 8 line (1:8 ) Demultiplexer3. 1 line - to - 16 line (1:16 ) Demultiplexer

Block Diagram

Truth Table Operation

1. Din is connected to Y0 when S1S0=00, 2. Din is Connected to Y1 when S1S0=01, 3. Din is connected to Y2 when S1S0=10, 4. Din is Connected to Y3 when S1S0=11

Boolean Expression Logical Diagram

Y0 = S1S0DinY1 = S1S0DinY2 = S1S0DinY3 = S1S0Din

52


Q60.Draw and Explain 1:8 DEMux ?Ans.Fig Shows the Block diagram and Truth table of 1:8 demux

1. It has One data input Din2. One Strobe Signal for Enabling the DEMUX , it should be High for

normal operation3. Three Select Signals S2S1S0 for Selecting the output to get connected

with input


53


Logical expression Logical Diagram

Y7 = E.S2S1S0.DinY6 = E.S2S1S0.DinY5 = E.S2S1S0.DinY4 = E.S2S1S0.DinY3 = E.S2S1S0.DinY2 = E.S2S1S0.DinY1 = E.S2S1S0.Din Y0 = E.S2S1S0.Din

Operation : When E = 0 , all the AND gate has there one input as Logic “O” make all output of the AND gate as LOW. Hence DEMUX is disabledFor Normal Operation E =1.Operation is as follows

1. Din is connected to Y0 when S3S1S0=000, 2. Din is Connected to Y1 when S3S1S0=001, 3. Din is connected to Y2 when S3S1S0=010, 4. Din is Connected to Y3 when S3S1S0=011 5. Din is Connected to Y4 when S3S1S0=100 6. Din is Connected to Y5 when S3S1S0=101 7. Din is Connected to Y6 when S3S1S0=110 8. Din is Connected to Y7 when S3S1S0=111

Q61.Draw and Explain 1:16 DEMux ?Ans. Fig Shows the Block diagram and Truth table of 1:8 demux

1. It has One data input Din2. One Strobe Signal for Enabling the DEMUX , it should be High for

normal operation3. Four Select Signals S3S2S1S0 for Selecting the output to get

connected with input

54


Truth Table:

Truth Table

55


Logical Expressions Logical Diagram

56


Yo = ABCDDIn

Y1 = ABCDDIn

Y2 = ABCDDIn

Y3 = ABCDDIn

Y4 = ABCDDIn

Y5 = ABCDDIn

Y6 = ABCDDIn

Y7 = ABCDDIn

Y8 = ABCDDIn

Y9 = ABCDDIn

Y10 = ABCDDIn

Y11 = ABCDDIn

Y12 = ABCDDIn

Y13 = ABCDDIn

Y14 = ABCDDIn

Y15 = ABCDDIn

Q62.List Some IC of DemultiplexerAns.Demultiplexer IC's

57


Ic No Description Output74138 1:8 Demux

(3 line to 8 line Decoder)Inverted Output

74139 Dual 1:4 Demux(2 line to 4 line Decoder)

Inverted Output

74155 Dual 1:4 Demux( Dual 2:4 Line Decoder )

1Y - Inverted Inputs2Y - Same as Input

74156Dual 1:4 Demux( Dual 2:4 Line Decoder )

Open Collector1Y - Inverted Inputs2Y - Same as Input

74154 1:16 Demux(4 Line to 16 Line Decoder)

same as InputOpen Collector

741591:16 Demux(4 line to 16 Line Decoder)

Same as Input

58


Q63.Describe the demultiplexer IC 74155 ie 1:4 DemuxAns.

Truth Table

59


Q64.Describe IC 74154 1:16 demuxAns. The pin configuration of this IC is as shown in Fig.

1.A, B, C, D are the four input lines, G1 and G2 are the active low strobe lines.

2.Q0-Q15 are the 16-active low output3.This is a TTL IC hence needs a unipolar power supply of + 5 Volts.4.These ICs can be used as 1: 16 demultiplexer. To do so, one of the

strobe inputs (G1 or G2) is used as data input (Din line and the input lines A, B, C, D act as select lines. The other strobe input should be connected to logic low level.

5.If G1 or G2 or both are high then all the outputs will be high (inactive).6.74LS154 are ideally suitable for implementing high performance

memory decoders.7.All the inputs are buffered and input clamping diodes are provided.

60


Truth Table

61


Logical Diagram

Q65.Describe what is Demultiplexer Tree and state its necessityAns. Since 1:16 is maximum available demux (4:16)/decoder to meet the larger input needs there should be provision for expansion. This is made possible by using enable input terminal.Hence when such demux are cascaded they are called as Demux Tree. IT is Needed for Expansion of Demux for higher number of output then the commercial available.

Q66.Design 1:8 demux using 1:4 demuxAns.Fig.Shows truth table of 1:8 using 1:4 Demux. Two 1:4 demux are needed.

62


Design 1. The select lines S1 and S0 of the two 1: 4 deniultiplexers are connected

in parallel with each other and S2 is used for selecting one of the two 1:4 demultiplexers.

2. S2 is connected directly to Enable (E) input of Demux — 2 whereas inverted S2 is connected to the enable input of Demux — 1.

Logical Diagram of 1:4 using 1:8Demux

63


Q67.Design 1:32 demux using 1:8 demuxAns.Fig.Shows Truth table of 1:32 using 1:8 Demux.It requires total 5 select Line out of which three(S2S1S0) of 1:8 are used to select the output of individual demux and two select(S4S3) line of input demux is used to select the Demux ie any one out of four as shown in truth table

Truth tableDemux Tree

Q68.Compare Mux and DemuxAns.

SrNo Parameter MUX DEMUX1 Logic Circuit Combinational Logic Combinational Logic2 Data Input Many ie N Input One Input3 Output One output Many output ie N4 Select Input M select Lines M Select Lines5. Relation Between

Select Input and Output

N=2M N=2M

6. Operation Many into 1 ie DataSelector

One into Many ie Data Distributor

7 Application 1. Boolean Expression implementatio

1. Boolean Expression implementation

64


n.One Equtaion per MUX

2. In time division multiplexing at the sending end.

.Many Equaton can be implemented using one DEMUX and Some gates.

2. In time division multiplexing at the receiving end

Q69.Implement Following Boolean Expression using DEMUX1. F1 = Σm(0,1,3,5,6)2. F2 = Σm(0,1,2,4,6)3. F3 = Σm(1,2,3,6)

Ans.When Boolean expression are to be implemented using demux additional logic gates are need and also more than Boolean expression can be implemented using single Demux.

General steps :1. Since output are not more then 7 we can use 1:8 demux.2. Take the minterm output from the input of the OR gate so that output will

come for the minterm specified in the equation.3. Hence to implement above three equation three OR gates are needed.4. Fig shows the circuit diagram.

// Logical Diagram are needed (Refer page B / Ch3)

EncoderQ70.What is Encoders ? Describe its OperationAns.The opposite of the decoding process is called Encoding and is performed by a combinational logic circuit called an Encoder. In other words Encoders is a logic circuit that provide appropriate code (Binary or BCD etc) as the output for each input signal applied. The process is reverse of decoding. When more then one input are applied at a time , internal hardware will check this condition and the highest priority input will be taken into account and converted in format at the output.It has N Input and M output.

65


Q71.List Different types of EncodersAns. Types of encoders

1. Priority encoders.2. Decimal to BCD encoder.3. Octal to binary encoder,4. Hexadecimal to binary encoder.

Q72.What is Priority Encoder ?Describe it OperationAns.Fig.Shows Block Diagram of 4:2 Priority Encoder

Operation1. What will happen if all input are made simultaneously High.Here

priority comes into picture that output will be corresponding to highest priority input.

2. Priorities are given to the input lines. If two or more input lines are “1” at the same time, then the input line with highest priority will be considered.

3. The block diagram of a priority encoder is shown in Fig and its truth table is shown in Fig.

4. There are four inputs D0 through D3 and two outputs Y1 and Y0 Out of the four inputs D3 has the highest priority and D0 has the lowest priority.

5. That means if D3=1 then Y1 Y0 = 11 irrespective of the other inputs. Similarly if D3 = 0 and D2= 1 then Y1Y0 = 10 irrespective of the other inputs.

6. Complete operation can be Understood from truth table.

Q73.Describe the operation of 8:3 encoder 74148Ans.

Figure shows 8:3 encoder which has 8 active low input and 3 output lines .When input line 0 goes low , output is 000.When input line 5 goes low , output is 101.However this encoder is Unable to provide appropriate code if two or more input lines are activated simultaneously. The encoder which resolves this problem of simultaneous input is called as priority encoder. Figure shows logic symbol of 74LS148 ,8:3 priority encoder.

76543210

A0

A1

A2

8:366


67


Q74.Describe the operation of decimal to BCD EncoderAns.Decimal to BCD encoders

Decimal BCDA B C D

0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 1

(Refer Page C hapter3)Fig : Decimal to BCD Encoder Fig : Truth Table

Figure shows a decimal to BCD encoder when push button 3 is pressed the C & D OR gates have high inputs therefore output ABCD=0011. Similarly when push button 9 is pressed A & D OR gates will have high inputs therefore we get ABCD=1001.

IC 74147 is a decimal to BCD encoder and is also called priority encoder.

Input Output Enable

E1

0 1 2 3 4 6 7 A2

A1

A0

Eo GS

H X X X X X X X H H H H HL H H H H H H H H H H H LL X X X X X X L L L L H HL X X X X X L H L L H L HL X X X X L H H L H L L HL X X X L H H H L H H L HL X X L H H H H H L L L HL X L H H H H H H L H L HL L H H H H H H H H L L HL L H H H H H H H H H L H

76543210

A0

A1

G

VccGnd

A2

Eo

E1

74LS148

68


Q75.Describe IC 74147 Priority Encoder Ans.Fig. Shows IC 74147 Decimal to BCD Encoder.It is also called as 10:4 Encoder.

Functional DiagramPin Diagram

Truth Table

Operation1. A9 to A1 are the inputs with A1 having the lowest priority and A9

having the highest priority.2. From truth table we conclude that all nine inputs are ACTIVE LOW

representing decimal digit from 1 to 9. In response to input, chip produces inverted BCD code corresponding to highest numbered ACTIVE INPUT.

69


3. When all inputs are held high, output D C B A 1 111 i.e. DCBA (0000) (0)10. Thus a decimal 0 is represented.

4. The truth table also shows the normal BCD output which is actually the inversion of the output of IC

5. As A9, is the highest priority input, if A9 = 0 then the remaining input lines are treated as don’t care and the inverted BCD output is produced as DCBA = 0110. The Same logic is applicable to the other inputs.

Q76.Describe IC 74148 Octal to Binary EncoderAns.Figure shows octal to Binary Encoder Truth table and Pin diagram

Pin Diagram Pin Description

Truth TableDescription

1. I7 to I0 are the eight active low inputs.

70


2. A2 to A0, are the three active low outputs.3. El is the active low enable input terminal. If El is at logic 1 then it

will force all the output to become high i.e. inactive, This feature can be used to allow some time for the new input data to settle down.

4. GS is the group signal output. It is used for indication that one of the inputs is low i.e. active.

5. If all the inputs are inactive (high) the enable output (EO) goes to logic 0.

DecoderQ77.What is Decoder?Describe with block diagram.Ans. A decoder is digital logic circuit that convert N-bit binary input code in to M lines . Here each output lines will be activated for only one of the possible combination. It is combinational Logic Circuit. Decoder is identical to a demultiplexer without any data input. It performs operations which are exactly opposite to those of an encoder.For N input of the decoder there will be M = 2N

output. Fig.Shows Block Diagram of 2:4 Decoder. It has 2 input A,B and Four output D0,D1,D2,D3.

Fig shows the generalized block diagram.

Boolean Expression Logical Diagram

DO = ABD1 = ABD2 = ABD3 = AB

71


Q78.List different ways a decoder can be referredAns.Decoder can be referred in several other waysExample 3:8 decoder it accepts three lines and gives output eight lines.

1. it is also called as 1 of the 8 decoder2. it may also be called as Binary to octal decoder3. if it is 4:8 decoder then it is called as binary to

hexadecimal decoder.

Q79.Describe the 3:8 decoder with its logical DiagramAns.Fig. Shows truth table and Logical diagram of the 3:8 Decoder

Truth Table

Block DiagramDesign :3:8 decoder has

1. 3 input CBA2. 8 output D7 to D0

72


Logical Diagram

Q80.Describe IC 74138 3:8 decoderAns.

Pin Diagram Truth TableDescription

1. The pin configuration of the 3:8 decoder IC 74138 is shown in Fig2. A2 A1 A0 are the three the three input lines. To this we apply the 3-bit

binary data to these inputs.3. Oo-O7 are the 8-output active low lines(output is Low).4. There are three enable inputs out of which E1, E2 are the active low

enable inputs whereas E3, is an active high enable input.5. For Normal operation or for IC to selected for Operation E1=E2 =0 (LOW)

and E3 = 1 (High)6. It can be used as demux by making either E1 or E2 or E3 as Data input.

If E1 and E2 are made as data input then it will be active Low and If E3 is made as data input then it is Active High.

73


7. Truth table as shown in Fig.

Q81.Describe IC 74139 Dual 1:4 decoderAns.Fig Shows Pin diagram and Functional Diagram of 74139. It has

1. Two Enable Signal 1En and 2EN2. 4 Input signal , Two for each section. (1A,1B and 2A,2B)3. 8 active LOW output Four for each section.(1YO,1Y1,1Y2,1Y3 and

2YO,2Y1,2Y2,2Y3)

Pin DiagramFunctional Diagram

74


Truth Table

Q82. Implement the Following Boolean Expression using DecoderF1(A,B,C) =∑(0,4,7) +D(2,3)F2(A,B,C) = ∑(1,5,6)F3(A,B,C) = ∑(0,2,4,6)

Ans.

75


Q83.How Demux can be used as DecoderAns.

Q84.What is 7 Segment display ? List its type with diagramAns.

76


Q85.Describe the Operation of BCD to 7 Segment DecoderAns.

For Common Anode Seven Segment Display1. The display used is common anode type.2. The decoder accepts a four bit BCD and converts it to a seven

bit code suitable for the seven segment display (a to g) and drives the display.

3. For segment to glow the corresponding decoder output goes low, and sinks current (for common anode display).

4. A current limiting resistance is connected in series with each segment.

For Common Cathode Seven Segment Display1. Fig. shows the circuit arrangement to drive a common

cathode display using a BCD to seven segment decoder / driver.

2. The outputs of this decoder are active high. Therefore whenever a segment is to be turned on. The corresponding output of the decoder goes high.

77


1. The decoder has to source the current in this case the common anode point is connected to Vcc ie positive supply voltage.

2. A Current limiting resistor is externally connected in series with each segment

3. The cathode of segment to be turned on are connected to ground. For example for displaying 7 the cathode of each segment a,b,c should be connected to ground.

Q86.List IC used as Decoder/Drive for Driving 7 segment DisplaysAns.Following are the IC used for BCD to Decimal conversion

Q87.Describe the BCD to Decimal Decoder IC 7445Ans.IC 7445 (BCD to Decimal decoder)

These BCD-to-decimal decoders/drivers consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of BCD input logic ensures that all outputs remain OFF for all invalid (10–15) binary

78


input conditions. These decoders feature high-performance, NPN output transistors designed for use as indicator/relay drivers, or as open-collector logic-circuit drivers. The high-breakdown output transistors are compatible for interfacing with most MOS integrated circuits.

Features1. Full decoding of input logic2. 80 mA sink-current capability3. All outputs are off for invalid BCD input conditions

Fig.Shows BCD -to- Decimal decoder/Driver

Fig.Truth Table

79


It is also called 4:10 decoder and is similar 4:16 decoder but with only 10 output lines. Since BCD numbers are from 0000 to 1001. When ABCD=0001 the Y1 AND gate has all its input high producing a high output.

Similarly when ABCD=1001 the Y9 AND gate will produce high output. IC 7445 is a BCD to DECIMAL decoder here all the outputs are active low. For forbidden numbers all the output goes high. Depending upon the ABCD inputs representing the decimal number corresponding output will go low.Q88.List IC which are used to convert BCD to 7 segment and Driver 7 segment displayAns.BCD to 7 segment Decoder and Driver ICs.

Q89.Describe the IC 7447 BCD-7Segment Decoder/Driver used to interface common Anode 7 Segment DisplayAns. Features of 7447

1. Open collector output drive the indicator directly2. Lamp test Provision3. Leading and Trailing zero Suppression

The output are active low therefore these IC is used for common Anode type of displays.

80


The functions of other pin in the IC are as below:♦ LT: This is called lamp test terminal and is used for segment testing. If it is

connected to logic 0 level. All segments of display connected to the decoder will be ON. For normal decoding operation this terminal must be connected to logic 1 level.

♦ RBI: For normal decoding operation this is connected to logic 1 level. If it is connected to logic 0 level, the segment outputs will generate the data for normal 7 segment decoding for all BCD inputs except 0 whenever the BCD inputs corresponds to 0 the seven segment display switches OFF. This is used for zero blanking in multi digit displays.

♦ BI: If it is connected to logic 0 level the display is switched OFF irrespective of BCD inputs. This is used for conserving the power in multiplexed displays.

♦ RBO: This output is used for cascading purpose and is connected to RBI terminal of the succeeding stage.

Truth Table

Q90.What is ALU ? Describe ALU IC 74181?Ans. A very popular and widely used combinational circuit is ALU which is capable of performing arithmetic as well as logical operations. This is the heart of any micro processor. Figure shows the block diagram of 74181 ALU.

81


Fig : Arithmetic and Logic UnitDescription of ALU - 74181

The block diagram of 74LS181 ALU is as shown. This circuit can be used for both positive as well as negative logic. The functions of various input and output control lines are as follows:

Inputs: a) A0-A3 and B0-B3 are four bit binary data inputs. b) Cn-carry input. This is active low i.e. if carry input is to be given it should be

at logic 0.Outputsa) F0-F3 are 4 bit binary data output.b) Cn+4 is Carry output-For the addition operation a logic 0 on this line indicates

a carry output. For the subtraction operation it indicates sign of output logic 0 on this line indicates positive result and logic 1 indicates a negative result in 2's complement form.

c) A=B is Equality output. Logic 1 on this line indicates A=B. It is used for comparator operation.

d) G - Carry generate output.e) P - Carry propagate output.

These outputs are used when a number 74181 circuits are used in cascade. The 74181 can be cascaded by connecting the carry-out of a stage to the

carry-in of the succeeding stage.

Control Lines

82


a) Select line: It has four function select lines, S3,S2,S1,S0, so to select any one of the operations.

b) Mode Control -M : If M=0 Arithmetic operations are performed & if M=1 logical operations are performed.

Fig.Show Truth table of ALU

Q91.What is Digital Comparator ? Describe Digital Comparator IC 7485?Ans.Comparator is a circuit which compares two inputs. Figure shows a digital comparator which compares two 1 bit digital signals.

83


1. Whenever A >B then output marked A>B will be 1 while other outputs are zero. 2. Whenever A=B (0 or 1) then output marked A=B will be one 3. Whenever A<B then output marked A<B will be one while other outputs are

zero. 4. IC 7485 is a 4 bit digital comparator. 5. A and B are 4 bit binary inputs while A>B,A=B and A<B are its outputs. 6. This IC is provided cascading facility with another digital comparator.

Fig.Functional Diagram of IC 7485

84


Truth table

85


Q92.Draw 5 bit comparator using IC 7485

Ans.Fig. Shows 5 bit comparator

Q93.what is Parity ? Describe even and Odd parityAns. In mathematics, parity refers to the evenness or oddness of an

integer, which for a binary number is determined only by the least significant bit. In telecommunications and computing, parity refers to the evenness or oddness of the number of bits with value one within a given set of bits, and is thus determined by the value of all the bits. It can be calculated via an XOR sum of the bits, yielding 0 for even parity and 1 for odd parity. This property of being dependent upon all the bits and changing value if any one bit changes allows for its use in error detection schemes. In quantum mechanics, parity corresponds to the behavior of the wave function under reflection.

In computers, parity (from the Latin paritas: equal or equivalent) refers to a technique of checking whether data has been lost or written over when it's moved from one place in storage to another or when transmitted between computers

Start Data Data Data Data Data Data Data Data Parity Stop0 1 2 3 4 5 6 7 8 9 10

A parity bit is a bit that is added to ensure that the number of bits with the value one in a set of bits is even or odd. Parity bits are used as the simplest form of error detecting code.

The parity bit, unlike the start and stop bits, is an optional parameter, used in serial communications to determine if the data character being transmitted is correctly received by the remote device.

86


There are two variants of parity bits 1. even parity bit and 2. odd parity bit.

When using even parity, the parity bit is set to 1 if the number of ones in a given set of bits (not including the parity bit) is odd, making the entire set of bits (including the parity bit) even. When using odd parity, the parity bit is set to 1 if the number of ones in a given set of bits (not including the parity bit) is even, making the entire set of bits (including the parity bit) odd. In other words, an even parity bit will be set to "1" if the number of 1's + 1 is even, and an odd parity bit will be set to "1" if the number of 1's +1 is odd

Q94.Describe the IC 74180 parity GeneratorAns.Fig Shows functional and Pin diagram of IC 74180

Functional Diagram Pin DiagramFiguregives the block diagram of 74180 in which there are

1. Eight parity inputs A through H and 2. Two cascading inputs. 3. There are two outputs ∑EVEN and ∑ODD. Its function table is given in

Table

Q95.Design 9 bit ODD parity generator using 7485

87


Ans.Fig. Shows truth table for 9 bit parity generator and Checker

88


Description1. Since the odd parity checker is to be drawn, we have to use the

∑odd output of 74180.2. Since 9 bit input is to be applied, we should apply 8 of the 9 bits to

the input A - H. 3. Whereas the 9 bit is applied to the ODD input as shown in Fig. 4. Output ∑odd will be high if the parity of the 9 bit input is odd.5. The function table of 74180 explains the operation of this circuit

89

prof.manoj kavedia ( 9860174297 ) ([email protected])...

Documents