program structure and syllabus

PROGRAM STRUCTURE

AND SYLLABUS

For

M. Tech TWO YEARS DEGREE PROGRAM

(Applicable for the batches admitted from 2017-18)

ADITYA ENGINEERING COLLEGE An Autonomous Institution

Approved by AICTE, Affiliated to JNTUK & Accredited by NBA, NAAC with 'A' Grade

Recognized by UGC under the sections 2(f) and 12(B) of UGC act 1956

Aditya Nagar, ADB Road, SURAMPALEM - 533 437

VLSI DESIGN

AR17 M.Tech (VLSI Design)

Aditya Engineering College (A) 1

VISION & MISSION OF THE COLLEGE

VISION

To induce higher planes of learning by imparting technical education with,

- International standards

- Applied research

- Creative ability

- Value based instruction and to emerge as a premier institute.

MISSION

Achieving academic excellence by providing globally acceptable technical education

by forecasting technology through

- Innovative research & development

- Industry institute interaction

- Empowered manpower

VISION & MISSION OF THE DEPARTMENT

VISION

To empower the Electronics and Communication Engineering students with

technological capability, professional commitment and social responsibility.

MISSION

M1: Providing quality education through dedication to duty, best of breed

laboratory facilities, collaborative ventures with the industries and

effective teaching-learning process.

M2: Pursuing research and promoting new technologies in order to serve the

needs of the society, industry, government and scientific community.

M3: Equipping the students with strong foundations to enable them for

continuing education. ****



PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

Graduates of the Program will

PEO 1

Acquire competency in areas of VLSI including IC Fabrication, Design,

Testing, Verification and prototype development focusing on

applications.

PEO 2

Design, implement, analyze and interpretation of VLSI projects using

CAD& EDA tools: Cadence, P-Spice, Vivado, MATLAB, Mentor

Graphics, microwind, DSCH

PEO 3 Integrate multiple sub-systems to develop System On Chip, optimize its

performance and excel in industry sectors related to VLSI domain.

PROGRAM OUTCOMES (POs)

After successful completion of the program, the graduates will be able to

PO 1

Scholarship of Knowledge: Acquire in-depth knowledge of specific

discipline or professional area, including wider and global perspective,

with an ability to discriminate, evaluate, analyze and synthesize

existing and new knowledge, and integration of the same for

enhancement of knowledge.

PO 2

Critical Thinking: Analyze complex engineering problems critically,

apply independent judgment for synthesizing information to make

intellectual and/or creative advances for conducting research in a wider

theoretical, practical and policy context.

PO 3

Problem Solving: Think laterally and originally, conceptualize and

solve engineering problems, evaluate a wide range of potential

solutions for those problems and arrive at feasible, optimal solutions

after considering public health and safety, cultural, societal and

environmental factors in the core areas of expertise.

PO 4

Research Skill: Extract information pertinent to unfamiliar problems

through literature survey and experiments, apply appropriate research

methodologies, techniques and tools, design, conduct experiments,

analyze and interpret data, demonstrate higher order skill and view

things in a broader perspective, contribute individually/in group(s) to

the development of scientific/technological knowledge in one or more

domains of engineering.

PO 5

Usage of modern tools: Create, select, learn and apply appropriate

techniques, resources, and modern engineering and IT tools, including

prediction and modeling, to complex engineering activities with an

understanding of the limitations.

PO 6 Collaborative and Multidisciplinary work: Possess knowledge and

understanding of group dynamics, recognize opportunities and



contribute positively to collaborative-multidisciplinary scientific

research, demonstrate a capacity for self-management and teamwork,

decision-making based on open-mindedness, objectivity and rational

analysis in order to achieve common goals and further the learning of

themselves as well as others.

PO 7

Project Management and Finance: Demonstrate knowledge and

understanding of engineering and management principles and apply the

same to one’s own work, as a member and leader in a team, manage

projects efficiently in respective disciplines and multidisciplinary

environments after considerisation of economical and financial factors.

PO 8

Communication: Communicate with the engineering community, and

with society at large, regarding complex engineering activities

confidently and effectively, such as, being able to comprehend and

write effective reports and design documentation by adhering to

appropriate standards, make effective presentations, and give and

receive clear instructions.

PO 9

Life-long Learning: Recognize the need for, and have the preparation

and ability to engage in life-long learning independently, with a high

level of enthusiasm and commitment to improve knowledge and

competence continuously.

PO 10

Ethical Practices and Social Responsibility: Acquire professional

and intellectual integrity, professional code of conduct, ethics of

research and scholarship, consideration of the impact of research

outcomes on professional practices and an understanding of

responsibility to contribute to the community for sustainable

development of society.

PO 11

Independent and Reflective Learning: Observe and examine

critically the outcomes of one’s actions and make corrective measures

subsequently, and learn from mistakes without depending on external

feedback.



PROGRAM SPECIFIC OUTCOMES

After successful completion of the program, the graduates will be able to

PSO1

(K3)

Acquire competency in areas of VLSI including IC Fabrication, Design,

Testing, Verification and prototype development focusing on

applications.

PSO2

(K4)

Design, implement, analyze and interpretation of VLSI projects using

CAD& EDA tools: Cadence-Spice, Xilinx ISE, MATLAB, Mentor

graphics, microwind,DSCH

PSO3

(K6)

Integrate multiple sub-systems to develop System On Chip, optimize its

performance and excel in industry sectors related to VLSI domain.

Mission of the department – PEOs mapping

PEO’s Statements M1 M2 M3

PEO 1:

Identify and apply appropriate Electronic Design

Automation (EDA) to solve real world problems in

VLSI domain to create innovative products and

systems.

3 2 3

PEO 2:

Develop managerial skill and apply appropriate

approaches in the domain of VLSI design incorporating

safety, sustainability and become a successful

professional or an Entrepreneur in the domain.

3 3 3

PEO 3:

Pursue career in research in VLSI designdomain through

self-learning and self-directed on cutting edge

technologies

3 2 3

Note:.

Bloom’s Taxonomy

Knowledge Level

Knowledge Level

Representation

Remember K1

Understand K2

Apply K3

Analyse K4

Evaluate K5

Create K6

Mapping / Correlation levels

1: Slight (Low)

2 : Moderate (Medium)

3 : Substantial (High)



PROGRAMME STRUCTURE I SEMESTER

Course

Code Name of the Course

Periods /Week Credits

(C) Lecture (L) Practice (P)

172EM1T01 Digital System Design 4 --- 3

172VD1T01 VLSI Technology & Design 4 --- 3

172VD1T02 CMOS Analog IC Design 4 --- 3

172VD1T03 CMOS Digital IC Design 4 --- 3

Elective – I

172EM1E01 Cyber Security

4 --- 3 172VD1E01 Digital Design using HDL

172CO1E02 Advanced Operating Systems

172EM1E03 Soft Computing Techniques

Elective – II

172VD1E02 CPLD / FPGA Architectures & Applications

4 --- 3 172VD1E03 Hardware Software Co - Design

172EM1E07 Advanced Computer Architecture

172VD1L01 Front End VLSI Design - Lab --- 3 2

TOTAL 20

II SEMESTER

Course




172VD2T04 CMOS Mixed Signal Circuit Design 4 --- 3

172VD2T05 Embedded System Design 4 --- 3

172VD2T06 Low Power VLSI Design 4 --- 3

172VD2T07 Design For Testability 4 --- 3

Elective – III

172VD2E04 CAD for VLSI

4 --- 3 172EM2T06 DSP Processors & Architectures

172VD2E05 VLSI Signal Processing

Elective – IV

172EM2E08 System on Chip Design

4 --- 3 172VD2E06 Optimization Techniques in VLSI Design

172VD2E07 Semi Conductor Memory Design and Testing

172VD2L02 Back End VLSI Design - Lab --- 3 2

TOTAL 20



III SEMESTER

Course




172VD3C01 Comprehensive Viva-Voce --- --- 2

172VD3R01 Seminar – I --- --- 2

--- Project Work Part – I --- --- 16

TOTAL 20

IV SEMESTER

Course




172VD4R02 Seminar - II --- --- 2

172VD4P01 Project Work Part - II --- --- 18

TOTAL 20



DIGITAL SYSTEM DESIGN

Course Objectives:

COB 1: To make the students to aware of different algorithms for minimizing the

complexity of

digital system design.

COB 2: To demonstrate the students about PLA design aspects, IISc &

COMPACT algorithms with suitable examples.

COB 3: To impart the knowledge on SM charts, design aspects of ROM,PAL and

digital circuit design approach using CPLDs ,FPGAs and ASICS.

COB 4: To impart the knowledge about Fault Modeling, Test Patten generation

and different methods for fault diagnosis of Combinational circuits.

COB 5: To impart the knowledge about fault diagnosis methods of Sequential

circuits.

Course Outcomes:

At the end of the Course, Student will be able to:

CO 1: Examine CAMP Algorithms for minimizing the complexity of digital

system design.

CO 2: Simplify digital circuits using PLA minimization algorithm (IISc

algorithm) and PLA folding algorithm

CO 3: construct digital circuits using CPLDs, FPGAs and ASICs

CO 4: Analyze the functionality of combinational circuits using different fault

diagnosis & test methods.

CO 5: Analyze the testing aspects and fault diagnosis methods of sequential

circuits.

Mapping of Course Outcomes with Program Outcomes

CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K4) 2 3 2 - - - - - - - -

CO 2(K4) - 3 - - - - - - - - -

CO 3(K3) 1 2 1 3 3 - - - - - -

CO 4(K4) 2 3 2 - - - - - - - -

CO 5(K4) 2 3 2 - - - - - - - -

Mapping of Course Outcomes with Program Specific Outcomes

CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K4) - 2 1

CO 2(K4) - - 1

CO 3(K3) 1 1 -

CO 4(K4) 2 2 -

CO 5(K4) 2 2 -

I Semester L P C

Course Code: 172EM1T01 4 0 3



UNIT-I

Minimization Procedures and CAMP Algorithm:

Review on minimization of switching functions using tabular methods, k-map, QM

algorithm, CAMP-I algorithm, Phase-I: Determination of Adjacencies, DA, CSC,

SSMs and EPCs,, CAMPI algorithm, Phase-II: Passport checking, Determination of

SPC, CAMP-II algorithm: Determination of solution cube, Cube based operations,

determination of selected cubes are wholly within the given switching function or not,

Introduction to cube based algorithms.

UNIT-II

PLA Design, Minimization and Folding Algorithms:

Introduction to PLDs, basic configurations and advantages of PLDs, PLA-

Introduction, Block diagram of PLA, size of PLA, PLA design aspects, PLA

minimization algorithm(IISc algorithm), PLA folding algorithm(COMPACT

algorithm)-Illustration of algorithms with suitable examples.

UNIT-III

Design of Large Scale Digital Systems:

Algorithmic state machine charts-Introduction, Derivation of SM Charts, Realization

of SM Chart, control implementation, control UNIT design, data processor design,

ROM design, PAL design aspects, digital system design approaches using CPLDs,

FPGAs and ASICs.

UNIT-IV

Fault Diagnosis in Combinational Circuits:

Faults classes and models, fault diagnosis and testing, fault detection test, test

generation, testing process, obtaining a minimal complete test set, circuit under test

methods- Path sensitization method, Boolean difference method, properties of Boolean

differences, Kohavi algorithm, faults in PLAs, PLA test generation, DFT schemes,

built in self-test. Fault tolerance techniques

UNIT-V

Fault Diagnosis in Sequential Circuits:

Fault detection and location in sequential circuits, circuit test approach, initial state

identification, Hamming experiments, synchronizing experiments, machine

identification, distinguishing experiment, adaptive distinguishing experiments.

Text Books:

1. Logic Design Theory, N. N. Biswas, PHI

2. Switching and Finite Automata Theory, Z. Kohavi , TMH, 2nd Edition, 2001.

Reference Books:

1. Fundamentals of Logic Design, Charles H. Roth, Cengage Learning,5thEdition.

2. Digital Systems Testing and Testable Design, MironAbramovici, Melvin A.

3. Digital Logic Applications and Design, John M Yarbrough, Thomson

Learning, 2001.



Web Links:

1. https://www.scribd.com/document/1935815/NR-311901-Digital-Systems-

Design

2. https://www.slideshare.net/yayavaram/pla-minimization-testing

3. https://www.elsevier.com/.../digital-systems-design...fpgas...cplds/.../978-0-

7506-8397...

4. www.donnamaie.com/Advanced.../Advance%20Logic%20Chap%2012-

typed.pdf

*****

https://www.scribd.com/document/1935815/NR-311901-Digital-Systems-Design

https://www.scribd.com/document/1935815/NR-311901-Digital-Systems-Design

https://www.slideshare.net/yayavaram/pla-minimization-testing

https://www.elsevier.com/.../digital-systems-design...fpgas...cplds/.../978-0-7506-8397

https://www.elsevier.com/.../digital-systems-design...fpgas...cplds/.../978-0-7506-8397

http://www.donnamaie.com/Advanced.../Advance%20Logic%20Chap%2012-typed.pdf

http://www.donnamaie.com/Advanced.../Advance%20Logic%20Chap%2012-typed.pdf



VLSI Technology and Design

Course Objectives:

COB 1: To enable the students to know the fundamentals of VLSI technologies.

COB 2: To impart the knowledge on basic properties of MOS devices based on

different circuit parameters.

COB 3: To enable the students to learn the concepts of subsystem design

processes, subsystem design and layouts of VLSI circuits.

COB 4: To train the students with necessary electronic design automation concepts

for VLSI design and design issues.

COB 5: To make students to familiar with different floor planning methods for

designing low power VLSI architectures.

Course Outcomes:


CO 1: Summarize the fundamental concepts of VLSI technology including both

fabrication process and basic design elements.

CO 2: Analyze the various VLSI design technologies and design issues.

CO 3: Analyze the electrical properties, basic circuit concepts and scaling of the

MOS devices.

CO 4: Develop a subsystem design process for VLSI circuits.

CO 5: Choose various floor planning methods for architecture design.

CO 6: Identify various design methodologies for chip design.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K2) 1 - - - - - - - 3 - -

CO 2(K4) - 3 2 - 2 - - - 2 - 3

CO 3(K4) 2 - - 2 - - - - - - 3

CO 4(K3) 1 2 - 3 - - - - - - -

CO 5(K5) - - - 3 2 - - 3 2 - 1

CO 6(K3) - - - - 3 2 1 - 2 - -

I Semester L P C

Course Code: 172VD1T01 4 0 3




CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K2) 2 1 1

CO 2(K4) 3 3 1

CO 3(K4) 2 3 1

CO 4(K3) 2 2 3

CO 5(K5) 2 3 2

CO 6(K3) 3 2 1

UNIT-I:

VLSI Technology:

Fundamentals and applications, IC production process, MOS Technology and

fabrication process of pMOS, nMOS, CMOS and BiCMOS technologies, comparison

of different processes.

Building Blocks of a VLSI circuit: Computer architecture, memory architectures,

communication interfaces, mixed signal interfaces.

UNIT-II:

VLSI Design:

Electronic design automation concept ,ASIC and FPGA design flows, SOC design

,design technologies,Combinational design techniques, sequential design techniques,

state machine logic design techniques.

VLSI Design Issues:

Design process, design for testability, technology options, power calculations, package

selection, clock mechanisms, mixed signal design.Design rules and process

parameters, layout techniques and process parameters.

UNIT-III:

Basic electrical properties of MOS and BiCMOS circuits:

MOS and BiCMOS circuit design processes, Basic circuit concepts, scaling of MOS

circuits-qualitative and quantitative analysis with proper illustrations and necessary

derivations of expressions.

UNIT-IV:

Subsystem Design and Layout:

Some architectural issues switch logic, gate logic, examples of structured design

(combinational logic), some clocked sequential circuits, other system considerations.

Subsystem Design Processes: Some general considerations and an illustration of

design processes, design of an ALU subsystem.

UNIT-V:

Floor Planning:

Introduction, Floor planning methods, off-chip connections.

Architecture Design: Introduction, Register-Transfer design, high-level synthesis,

architectures for low power, architecture testing.

Chip Design: Introduction and design methodologies.



Text Books:

1. Essentials of VLSI Circuits and Systems, K. Eshraghian, Douglas A. Pucknell,

SholehEshraghian, PHI Publications, 2005.

2. Modern VLSI Design,Wayne Wolf, Pearson Education, 3rd Edition, 1997.

3. VLSI Design, Dr.K.V.K.K.Prasad, KattulaShyamala, Kogent Learning Solutions

Inc, 2012

Reference Books:

1. VLSI Design Technologies for Analog and Digital Circuits, Randall L.Geiger,

Phillip E.Allen, Noel R.Strader, TMH Publications, 2010.

2. Introduction to VLSI Systems: A Logic, Circuit and System Perspective, Ming,

BO Lin, CRC Press, 2011.

3. Principals of CMOS VLSI Design, N.H.E Weste, K. Eshraghian, Addison

Wesley,2nd Edition.

Web Links:

1. www.mmumullana.org/downloads/files/n54744b1ab8147.pdf

2. https://www.tutorialspoint.com/vlsi_design/vlsi_design_digital_system.html

3. https://www.ikbooks.com/home/samplechapter?filename=26_Sample_Chapter.

pdf

4. www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch02.pdf

5. vlsibyjim.blogspot.com/2015/03/floorplanning.html

****

www.mmumullana.org/downloads/files/n54744b1ab8147.pdf

https://www.tutorialspoint.com/vlsi_design/vlsi_design_digital_system.html



CMOS Analog IC Design

Course Objectives:

COB 1: To enable the students to learn about evolution of CMOS integrated

circuits.

COB 2: To make the students familiar with advanced current mirrors and their

behavior at high frequency and low frequencies.

COB 3: To make the students familiar with design of OP-AMPs, comparators in

CMOS.

COB 4: To familiarize the students with the various Amplifiers & OP-amps.

COB 5: To train the students to face the challenges in CMOS technology.

Course Outcomes:


CO 1: Demonstrate the small signal and large signal models of CMOS transistors

in different frequencies.

CO 2: Analyze the characteristics of different CMOS circuits.

CO 3: Develop the two stage CMOS operational amplifiers.

CO 4: Analyze different comparators and their performance parameters.

CO 5: Develop the basic circuits based on the knowledge acquired in the course.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1 (K2 ) 1 1 - 2 - - - 3 - - -

CO2 (K4 ) 1 3 2 2 - - 1 - - - -

CO3 (K3) 1 2 - 3 - - - 3 - - -

CO4 (K4 ) 2 3 2 - - - - - - - -

CO5 (K3) 1 2 1 - 3 - - 3 3 - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K2 ) 2 1 -

CO2 (K4 ) 3 3 1

CO3 (K3) 3 3 1

CO4 (K4 ) 3 3 3

CO5 (K3) 3 2 -

I Semester L P C




UNIT-I

MOS Devices and Modeling:

The MOS Transistor, Passive Components- Capacitor & Resistor, Integrated circuit

Layout, CMOS Device Modeling - Simple MOS Large-Signal Model, Other Model

Parameters, Small-Signal Model for the MOS Transistor, Computer Simulation

Models, Sub-threshold MOS Model.

UNIT-II

Analog CMOS Sub-Circuits:

MOS Switch, MOS Diode, MOS Active Resistor, Current Sinks and Sources, Current

Mirrors-Current mirror with Beta Helper, Degeneration, Cascode current Mirror and

Wilson Current Mirror, Current and Voltage References, Band gap Reference.

UNIT-III

CMOS Amplifiers:

Inverters, Differential Amplifiers, Cascode Amplifiers, Current Amplifiers, Output

Amplifiers, High Gain Amplifiers Architectures.

UNIT-IV

CMOS Operational Amplifiers:

Design of CMOS Op Amps, Compensation of Op Amps, Design of Two-Stage Op

Amps, Power- Supply Rejection Ratio of Two-Stage Op Amps, Cascode Op Amps,

Measurement Techniques of OP Amp.

UNIT-V

Comparators:

Characterization of Comparator, Two-Stage, Open-Loop Comparators, Other Open-

Loop Comparators, Improving the Performance of Open-Loop Comparators, Discrete-

Time Comparators.

Text Books:

1. CMOS Analog Circuit Design, Philip E. Allen and Douglas R. Holberg,

Oxford University Press, International 2ndEdition, 2010.

2. Analysis and Design of Analog Integrated Circuits, Paul R. Gray, Paul J. Hurst,

S. Lewis and R. G. Meyer, Wiley India, 5thEdition, 2010.

Reference Books:

1. Analog Integrated Circuit Design, David A.Johns, Ken Martin, Wiley Student

Edition, 2016.

2. Design of Analog CMOS Integrated Circuits, BehzadRazavi, TMH Edition.

3. CMOS: Circuit Design, Layout and Simulation, Baker, Li and Boyce, PHI.

Web Links:

1. http://www.aicdesign.org/OnLineLectures.html

2. http://nptel.ac.in/courses/117106030/

3. www.mentor.com

4. www.cadence.com ****.

http://www.aicdesign.org/OnLineLectures.html

http://www.cadence.com/



CMOS DIGITAL IC DESIGN

Course Objectives:

COB 1: To enable the students to learn about static and dynamic characteristics of

MOS Inverters.

COB 2: To familiarize the students with the design of combinational logic gates in

CMOS.

COB 3: To enable the students to understand sequential logic gates design in

CMOS.

COB 4: To train the students for designing basic Arithmetic building blocks.

COB 5: To make the students to understand the concept of semiconductor

memories.

Course Outcomes:


CO 1: Explain the functionality of MOS inverters

CO 2: Analyze various combinational circuits designs in CMOS

CO 3: Analyze sequential logic gates designs in CMOS

CO 4: Explain the functionality of different arithmetic building blocks

CO 5: Analyze different semiconductor memories


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K2) - 1 - - 2 - - - - - -

CO 2(K4) 2 3 2 - 3 3 - 3 - - -

CO 3(K4) 2 3 2 - 3 3 - 3 - - -

CO 4(K2) - 1 - - - 1 - - - - -

CO 5(K4) 2 3 2 - - - - 3 - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K2) 2 1 - CO 2(K4) 3 3 - CO 3(K4) 3 3 - CO 4(K2) 2 1 - CO 5(K4) 3 3 1

I Semester L P C




UNIT-I

MOS Design:

Pseudo NMOS Logic: Inverter, Inverter threshold voltage, Output high voltage,

Output Low voltage, Gain at gate threshold voltage, Transient response, Rise time,

Fall time, Pseudo NMOS logic gates, Transistor equivalency, CMOS Inverter logic.

UNIT-II

Combinational MOS Logic Circuits:

MOS logic circuits with NMOS loads, Primitive CMOS logic gates – NOR & NAND

gate, Complex Logic circuits design – Realizing Boolean expressions using NMOS

gates and CMOS gates , AOI and OIA gates, CMOS full adder, CMOS transmission

gates, Designing with Transmission gates.

UNIT-III

Sequential MOS Logic Circuits:

Behavior of bistable elements, SR Latch, Clocked latch and flip flop circuits, CMOS

D latch and edge triggered flip-flop.

UNIT-IV Dynamic Logic Circuits:

Basic principle, Voltage Bootstrapping, Synchronous dynamic pass transistor circuits,

Dynamic CMOS transmission gate logic, High performance Dynamic CMOS circuits.

UNIT-V

Semiconductor Memories:

Types, RAM array organization, DRAM – Types, Operation, Leakage currents in

DRAM cell and refresh operation, SRAM operation Leakage currents in SRAM cells,

Flash Memory- NOR flash and NAND flash.

Text Books:

1. CMOS Digital Integrated Circuits Analysis and Design ,Sung-Mo Kang, Yusuf

Leblebici, TMH, 3rd Ed., 2011.

2. Digital Integrated Circuits, Jan M Rabaey, Pearson Education,2nd Edition,

2003.

Reference Books:

1. Introduction to VLSI Systems: A Logic, Circuit and System Perspective,

Ming-BO Lin, CRC Press, 2011.

2. Digital Integrated Circuits – A Design Perspective, Jan M. Rabaey, Anantha

Chandrakasan, Borivoje Nikolic, PHI, 2nd Ed.

3. Digital Integrated Circuit Design , Ken Martin, Oxford University Press, 2011.



Web Links:

1. https://subodhtripathi.files.wordpress.com/2012/01/0072460539cmos1.pdf

2. highered.mheducation.com/sites/0072460539/index.html

3. https://www.scribd.com/doc/102546275/CMOS-Digital-Integrated-Circuits-

Sung-Mo-Kang-Leblebici

4. https://infoscience.epfl.ch › Infoscience

5. https://www.slideshare.net/.../105926921-

cmosdigitalintegratedcircuitssolutionmanual.

*****.

https://subodhtripathi.files.wordpress.com/2012/01/0072460539cmos1.pdf



CYBER SECURITY

(Elective-I)

Course Objectives:

COB 1: To make the students to understand the Network Security.

COB 2: To enable the students to understand network-troubleshooting concepts.

COB 3: To make the students to understand about risk management processes and

practices.

COB 4: To demonstrate the students about the threats and risks within context of

the cyber security architecture.

COB 5: To make the students familiar with the security tools and hardening

techniques.

Course Outcomes:


CO 1: Discover the various security attacks and security services

CO 2: Develop a model for Internetwork security

CO 3: Analyze threats and risks within context of the cyber security architecture

CO 4: Utilize cryptography algorithms, digital signatures, digital Certificates and

Key Management

CO 5: Interpret the IP Security and its implementation of architecture, SSL, TLS

CO6: Make use of the intrusion detection system and Firewall


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K4) 2 3 2 3 3 3 - - 3 3 3

CO 2(K3) 1 2 1 3 3 2 - 3 3 3 2

CO 3(K4) - 3 2 - - 3 - - 3 3 3

CO 4(K3) 1 - 2 3 3 3 - - 3 - 2

CO 5(K5) 3 3 3 3 3 3 - 3 3 3 3

CO 6(K3) 1 2 1 3 3 2 - - 3 3 2


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K4) 3 - -

CO 2(K3) - 2 -

CO 3(K4) 3 - -

CO 4(K3) 3 - -

CO 5(K5) 3 - 2

CO 6(K3) 3 - -

I Semester L P C

Course Code:172EM1E01 4 0 3



UNIT-I

Introduction:

Security Attacks (Interruption, Interception, Modification and Fabrication), Security

Services (Confidentiality, Authentication, Integrity, Non-repudiation, access Control

and Availability) and Mechanisms, A model for Internetwork security, Internet

Standards and RFCs, Buffer overflow & format string vulnerabilities, TCP session

hijacking, ARP attacks, route table modification, UDP hijacking, and man-in-the-

middle attacks.

UNIT-II

Conventional Encryption:

Conventional Encryption Principles, Conventional encryption algorithms, cipher block

modes of operation, location of encryption devices, key distribution Approaches of

Message Authentication, Secure Hash Functions and HMAC

UNIT-III

Number Theory:

Prime and Relatively Prime Numbers, Modular Arithmetic, Fermat’s and Euler’s

Theorems, The Chinese Remainder theorem, Discrete logarithms Public key: Public

key cryptography principles, public key cryptography algorithms, digital signatures,

digital Certificates, Certificate Authority and key management Kerberos, X.509

Directory Authentication Service

UNIT-IV

IP Security:

IP Security Overview, IP Security Architecture, Authentication Header, Encapsulating

Security Payload, Combining Security Associations and Key Management Transport

Level Security: Web Security Requirements, Secure Socket Layer (SSL) and

Transport Layer Security (TLS), Secure Electronic Transaction (SET)

Email Privacy: Pretty Good Privacy (PGP) and S/MIME.

UNIT-V

Intrusion Detection:

Intruders, Intrusion Detection systems, Password Management. Malicious Software:

Viruses and related threats & Countermeasures. Fire walls: Firewall Design principles,

Trusted Systems.

Text Books:

1. Network Security & Cryptography: Principles and Practices, William Stallings,

PEA, 6th edition.

2. Hack Proofing your Network, Russell, Kaminsky, Forest Puppy, Wiley

Dreamtech.



Reference Books:

1. Network Security & Cryptography, Bernard Menezes, Cengage, 2010.

2. Network Security: The Complete Reference, Mark Rhodes-Ousley, Roberta

Bragg, Keith Strassberg.

Web Links:

1. http://www.sis.pitt.edu/jjoshi/IS2935/Fall04/

2. http://wiki.cas.mcmaster.ca/index.php/Conventional_Encryption_Algorithms

3. https://technet.microsoft.com/en-us/library/cc961976.aspx

4. https://technet.microsoft.com/en-us/library/cc179879.aspx

*****

https://www.amazon.com/s/ref=dp_byline_sr_book_1?ie=UTF8&text=Mark+Rhodes-Ousley&search-alias=books&field-author=Mark+Rhodes-Ousley&sort=relevancerank

https://www.amazon.com/Roberta-Bragg/e/B001ILFKWS/ref=dp_byline_cont_book_2

https://www.amazon.com/Roberta-Bragg/e/B001ILFKWS/ref=dp_byline_cont_book_2

https://www.amazon.com/s/ref=dp_byline_sr_book_3?ie=UTF8&text=Keith+Strassberg&search-alias=books&field-author=Keith+Strassberg&sort=relevancerank

http://www.sis.pitt.edu/jjoshi/IS2935/Fall04/



DIGITAL DESIGN USING HDL

(Elective-I)

Course Objectives:

COB 1: To impart the knowledge ondesign of digital circuits using HDLwith

example digital circuits.

COB 2: To enable the students to design combinational and sequential logic

circuits using VHDL language.

COB 3: To impart the knowledge of Verilog language to design digital circuit in

behavioral, dataflow and structural model

COB 4: To enable the students to synthesize the digital and sequential circuits and

analyze them.

COB 5: To demonstrate the functionality of digital circuits using various fault

models.

Course Outcomes:


CO 1: Interpret the HDL design styles, data types to implement the basic digital

circuits.

CO 2: Analyze the basic logic circuits in Xilinx tool.

CO 3: Apply the HDL knowledge to implement combinational and sequential

digital circuits.

CO 4: Make use of the Xilinx tool Knowledge to synthesis the combinational and

sequential circuits.

CO 5: Test for the functionality of digital circuit by using various fault models


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1 (K3) - 1 - - 2 - - 3 - - -

CO2 (K6) - - 2 - 3 3 - - 3 - -

CO3 (K2) - 2 - - 3 - - - 3 - -

CO4 (K3) - 2 - - 3 2 - - - - -

CO5 (K4) - - - 3 3 - - - - - 3


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K3) 2 1 -

CO2 (K6) 3 3 1

CO3 (K2) 3 2 -

CO4 (K 3) 3 2 -

CO5 (K4) - 3 1

I Semester L P C

Course Code: 172VD1E01 4 0 3



UNIT-I

Digital Logic Design using VHDL:

Introduction, designing with VHDL, design entry methods, logic synthesis, entities,

architecture,packages and configurations, types of models: dataflow, behavioural,

structural, signals vs. Variables, generics, data types, concurrent vs. sequential

statements, loops and program controls.

Digital Logic Design using Verilog HDL:

Introduction, Verilog Data types and Operators, Binary data manipulation,

Combinational and Sequential logic design, Structural Models of Combinational

Logic, Logic Simulation, Design Verification and Test Methodology, Propagation

Delay, Truth Table models using Verilog.

UNIT-II

Combinational Logic Circuit Design using VHDL:

Combinational circuits building blocks: Multiplexers, Decoders, Encoders, Code

converters, Arithmetic comparison circuits, VHDL for combinational circuits, Adders-

Half Adder, Full Adder, Ripple-Carry Adder, Carry Look-Ahead Adder, Subtraction,

Multiplication.

Sequential Logic Circuit Design using VHDL:

Flip-flops, registers & counters, synchronous sequential circuits: Basic design steps,

Mealy State model, Design of FSM using CAD tools, Serial Adder Example, State

Minimization, Design of Counter using sequential Circuit approach.

UNIT-III

Digital Logic Circuit Design Examples using Verilog HDL:

Behavioural modelling, Data types, Boolean-Equation-Based behavioural models of

combinational logics, Propagation delay and continuous assignments , latches and

level-sensitive circuits in Verilog, Cyclic behavioural models of flip-flops and latches

and Edge detection, comparison of styles for behavioural model; Behavioural model,

Multiplexers, Encoders and Decoders, Counters, Shift Registers, Register files,

Dataflow models of a linear feedback shift register, Machines with multi cycle

operations, ASM and ASMD charts for behavioural modelling, Design examples,

Keypad scanner and encoder.

UNIT-IV

Synthesis of Digital Logic Circuit Design:

Introduction to Synthesis, Synthesis of combinational logic, Synthesis of sequential

logic with latches and flip-flops, Synthesis of Explicit and Implicit State Machines,

Registers and counters.

UNIT-V

Testing of Digital Logic Circuits and CAD Tools:

Testing of logic circuits, fault model, complexity of a test set, path-sensitization,

circuits with tree structure, random tests, testing of sequential circuits, built in self-test,

printed circuit boards, computer aided design tools, synthesis, physical design.



Text Books:

1. B Bala Tripura Sundari, Design Through Verilog HDL, T.R. Padmanabhan,

Wiley, 2009.

2. Verliog Digital System Design,Zainalabdien Navabi, TMH, 2nd Edition.

Reference Books:

1. Fundamentals of Digital Logic with Verilog Design, Stephen Brown,Zvonkoc

Vranesic, TMH, 2nd Edition.

2. Advanced Digital Logic Design using Verilog, State Machines & Synthesis for

FPGA,Sunggu Lee, Cengage Learning, 2012.

3. Verilog HDL, Samir Palnitkar, Pearson Education,2nd Edition, 2009.

4. Advanced Digital Design with Verilog HDL, Michel D. Ciletti, PHI, 2009.

Web Links:

1. https://en.wikipedia.org/wiki/

2. http://www.fpga4fun.com/HDLtutorials.html

3. http://esd.cs.ucr.edu/labs/tutorial/


*****

https://en.wikipedia.org/wiki/

https://en.wikipedia.org/wiki/

http://www.fpga4fun.com/HDLtutorials.html

http://esd.cs.ucr.edu/labs/tutorial/



ADVANCED OPERATING SYSTEMS

(Elective-I)

Course Objectives:

COB 1: To make the students to know the fundamentals of Operating Systems.

COB 2: To enable the students to learn about the structure and organization of the

file system.

COB 3: To impart the knowledge on distributed operating system concepts.

COB 4: To train the students with comprehensive and up-to-date coverage of the

major developments in distributed Operating System.

COB 5: To demonstrate the students about Hardware and software features of

Communication and Distribution systems.

Course Outcomes:


CO 1: Explain the basic concept of operating systems.

CO 2: Interpret the high-level structure of the Unix and Linux kernels.

CO 3: Analyze the concepts of processes, resource control, physical and virtual

memory, scheduling, I/O and files.

CO 4: Illustrate the concept of distributed operating systems.

CO 5: Develop the Mutual exclusion, Deadlock detection and agreement

protocols.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K2) - - - - - - - - - - -

CO 2(K2) - 1 - - - - - - - - -

CO 3(K4) 2 - 2 3 3 3 - - - - -

CO 4(K2) - 1 - - - 1 - - - - -

CO 5(K3) 1 - - - 3 2 - - 3 3 -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K2) - - -

CO 2(K2) 2 - -

CO 3(K4) 3 3 -

CO 4(K2) - 1 -

CO 5(K3) 3 2 -

I Semester L P C

Course Code: 172CO1E02 4 0 3



UNIT-I

Introduction to Operating Systems:

Overview of computer system hardware, Instruction execution, I/O function,

Interrupts, Memory hierarchy, I/O Communication techniques, Operating system

objectives and functions, Evaluation of operating System.

UNIT-II

Introduction to UNIX and LINUX:

Basic Commands & Command Arguments, Standard Input, Output, Input / Output

Redirection, Filters and Editors, Shells and Operations.

UNIT-III

System Calls:

System calls and related file structures, Input / Output, Process creation & termination.

Inter Process Communication:

Introduction, File and record locking, Client – Server example, Pipes, FIFOs, Streams

& Messages, Name Spaces, Systems V IPC, Message queues, Semaphores, Shared

Memory, Sockets & TLI.

UNIT-IV

Introduction to Distributed Systems:

Goals of distributed system, Hardware and software concepts, Design issues.

Communication in Distributed Systems:

Layered protocols, ATM networks, Client - Server model, Remote procedure call and

Group communication.

UNIT-V

Synchronization in Distributed Systems:

Clock synchronization, Mutual exclusion, E-tech algorithms, Bully algorithm, Ring

algorithm, Atomic transactions.

Deadlocks:

Dead lock in distributed systems, Introduction - deadlock handling strategies in

distributed systems - issues in deadlock detection and resolution, control organizations

for distributed deadlock detection - centralized and distributed deadlock detection

Distributed dead lock prevention and distributed dead lock detection., algorithms -

hierarchical deadlock detection algorithms.

Text Books:

1. The Design of the UNIX Operating Systems, Maurice J. Bach, 1986, PHI.

2. Distributed Operating System, Andrew. S. Tanenbaum, 1994, PHI.

3. The Complete Reference LINUX, Richard Peterson, 4th Ed., McGraw Hill.



Reference Books:

1. UNIX Operating Systems: Internal and Design Principles, Stallings, 6th Ed.,

PE.

2. Modern Operating Systems, Andrew S Tanenbaum, 3rd Ed., PE.

3. Operating System Principles, Abraham Silberchatz, Peter B. Galvin, Greg

Gagne, 7th Ed, John Wiley

4. Network Programming, W.Richard Stevens, 1998, PHI.

Web Links:

1. http://mally.stanford.edu/~sr/computing/basic-unix.html

2. https://www-uxsup.csx.cam.ac.uk/pub/doc/suse/suse9.0/userguide-

9.0/ch24s04.html

3. http://www.profjayesh.com/p/hardware-software-concepts-distributed.html

*****

http://mally.stanford.edu/~sr/computing/basic-unix.html

http://mally.stanford.edu/~sr/computing/basic-unix.html

https://www-uxsup.csx.cam.ac.uk/pub/doc/suse/suse9.0/userguide-9.0/ch24s04.html

https://www-uxsup.csx.cam.ac.uk/pub/doc/suse/suse9.0/userguide-9.0/ch24s04.html

http://www.profjayesh.com/p/hardware-software-concepts-distributed.html



SOFT COMPUTING TECHNIQUES

(Elective-I)

Course Objectives:

COB 1: To enable the students to familiarize with the learning methods for neural

networks.

COB 2: To demonstrate the students about basics of genetic algorithms and their

applications in optimization and planning.

COB 3: To train the students to learn about fuzzy sets, fuzzy logic and fuzzy

inference system.

COB 4: To make the students to design and implement the soft computing based

solutions for real-world problems.

COB 5: To facilitate the knowledge about various genetic algorithms.

Course Outcomes:


CO 1: Describe the soft computing techniques and their roles in building

intelligent machines.

CO 2: Apply the Artificial Neural Networks knowledge for solving the linear

problems.

CO 3: Apply the fuzzy logic and reasoning knowledge for solving the

uncertainty in engineering problems.

CO 4: Apply genetic algorithms to combinatorial optimization problems.

CO 5: Compare solutions by various soft computing approaches for a given

problem.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K3) 3 2 2 - - - - - - - -

CO 2(K3) - 2 2 - - - - - - - -

CO 3(K3) - 2 - 2 3 - - - - - -

CO 4(K3) - 2 - 2 3 - - - - - -

CO 5(K5) - 3 3 3 3 - 3 - - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K3) 3 - -

CO 2(K3) - 2 2

CO 3(K3) - 2 2

CO 4(K3) - 2 2

CO 5(K5) - - 3

I Semester L P C

Course Code: 172EM1E03 4 0 3



UNIT-I:

Introduction:

Approaches to intelligent control, Architecture for intelligent control, Symbolic

reasoning system, Rule-based systems, the AI approach, Knowledge representation –

Expert systems.

UNIT-II:

Artificial Neural Networks:

Concept of Artificial Neural Networks and its basic mathematical model, McCulloch-

Pitts neuron model, Learning Process: - error–correction learning, Hebbian learning,

competitive learning, Boltzmann learning, the credit-assignment problem, supervised

learning, and other learning techniques. Single Neuron/Perceptron networks: -

training methodology, typical application to linearly separable problems. Feed-forward

Multilayer Perceptron, Multilayer Perceptron: - Back propagation algorithm,

virtues and limitation of BP algorithm, modifications to back-propagation, Hopfield

network, Self-organizing network and Recurrent network.

UNIT–III:

Fuzzy Logic System:

Introduction to Fuzzy systems, Membership function, basic fuzzy set operation and

approximate reasoning, Introduction to fuzzy logic modeling and control,

Fuzzification, inferencing and de-fuzzification, Fuzzy modeling and control schemes

for nonlinear systems, Self-organizing fuzzy logic control.

UNIT-IV:

Genetic Algorithm:

Basic concept of Genetic algorithm and detail algorithmic steps, Basic concepts,

Search space, working principle. Encoding: binary, Octal, Hexadecimal, permutation,

Value and Tree. Decoding, fitness function, Selection: Roulette wheel, Boltzmann,

Tournament, Rank and Steady-state. Elitism, Crossover: single-point, two-point,

multi-point, uniform, matrix and crossover rate, Mutation: mutation, mutation rate.

Ant colony optimization: Ant foraging behavior, combinatorial optimization, Routing

in communication network, traveling sales man problem.

UNIT-V:

Applications:

GA: function optimization, adaptive system identification, and Application of ANN

and Fuzzy systems to non-stationary time series prediction; pattern classification;

control; communication engineering; system identification and pattern classification.

Text Books:

1. Neural Networks - A Comprehensive Foundation, S. Haykin, Pearson

Education, India (The book is also published by Prentice Hall of India), 2000.

2. Neural Network Design, Martin T. Hagan, Howard B. Demuth, Mark H. Beale,

(ISBN: 0 9717321-0-8); Thomson, 2002.



Reference Books:

1. Swarm Intelligence: From natural to Artificial Systems, E. Bonabeau, M.

Dorigo and G. Theraulaz (Santa Fe Institute Studies in the Sciences of

Complexity Proceedings),1999

2. Fuzzy Set Theory and Its Applications, Zimmerman H.J. Kluwer Academic

Publishers,1994

Web Links:

1. https://www.tutorialspoint.com/genetic_algorithms/

2. http://freevideolectures.com/Course/2348/Intelligent-Systems-and-Control/16


4. https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-

034-artificial-intelligence-fall-2010

*****

https://www.tutorialspoint.com/genetic_algorithms/

https://www.tutorialspoint.com/genetic_algorithms/

http://freevideolectures.com/Course/2348/Intelligent-Systems-and-Control/16

http://nptel.ac.in/courses/117105084/

https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-034-artificial-intelligence-fall-2010

https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-034-artificial-intelligence-fall-2010



CPLD/FPGA ARCHITECTURES & APPLICATIONS

(Elective-II)

Course Objectives:

COB 1: To impart the knowledge on programmable logic devices and differences

among them.

COB 2: To demonstrate the FPGA Programming Technologies, programmable

logic block architectures and their inter connects.

COB 3: To make the students to familiarize with the different SRAM

programmable FPGAs and their programming technology.

COB 4: To enable the students to learn about different Anti-Fuse Programmed

FPGAs and their programming technology.

COB 5: To enable the students to develop different digital circuits with ACT

Architectures.

Course Outcomes:


CO 1: Identify different types of programmable logic devices.

CO 2: Compare the performance of different FPGAs and their programming

Technologies.

CO 3: Analyze different SRAM programmable FPGA architectures.

CO 4: Analyze different Anti-Fuse Programmed FPGA architectures.

CO 5: Develop digital circuits with ACT architectures.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K3) 1 - 1 - 3 - - - - - -

CO 2(K2) - - - 2 2 - - - - - -

CO 3(K4) 2 3 2 3 3 - - - - - -

CO 4(K4) 2 3 2 3 3 - - - - - -

CO 5(K3) 1 2 1 3 3 - - - - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K3) - - -

CO 2(K2) - - -

CO 3(K4) 2 2 -

CO 4(K4) 2 2 -

CO 5(K3) 1 1 3

I Semester L P C




UNIT-I

Introduction to Programmable Logic Devices:

Introduction, Simple Programmable Logic Devices - Read Only Memories,

Programmable Logic Arrays, Programmable Array Logic, Programmable Logic

Devices/Generic Array Logic; Complex Programmable Logic Devices – Architecture

of Xilinx Cool Runner XCR3064XL,CPLD, CPLD Implementation of a Parallel

Adder with Accumulation.

UNIT-II

Field Programmable Gate Arrays:

Organization of FPGAs, FPGA Programming Technologies, Programmable Logic

Block Architectures, Programmable Interconnects, Programmable I/O blocks in

FPGAs, Dedicated Specialized Components of FPGAs, Applications of FPGAs.

UNIT–III

Programming FPGAs:

SRAM Programmable FPGAs, Introduction, Programming Technology, Device

Architecture, The Xilinx XC2000, XC3000 and XC4000 Architectures.

UNIT-IV

ACT FPGA Architectures:

Anti-Fuse Programmed FPGAs, Introduction, Programming Technology, Device

Architecture, TheActel ACT1, ACT2 and ACT3 Architectures

UNIT-V

Applications:

Design Applications, General Design Issues, Counter Examples, A Fast Video

Controller, A Position Tracker for a Robot Manipulator, A Fast DMA Controller,

Designing Counters with ACT devices, Designing Adders and Accumulators with the

ACT Architecture.

Text Books:

1. Field Programmable Gate Array Technology, Stephen M. Trimberger, Springer

International Edition.

2. Digital Systems Design, Charles H. Roth Jr, LizyKurian John, Cengage Learning.

3. Digital Systems Design with FPGAs and CPLDs, Ian Grout, Elsevier, Newnes.

Reference Books:

1. Digital Design Using Field Programmable Gate Arrays, Pak K. Chan/Samiha

Mourad, Pearson Low Price Edition.

2. Digital Systems Design with FPGAs and CPLDs, Ian Grout, Elsevier, Newnes.

3. FPGA based System Design, Wayne Wolf, Prentice Hall Modern Semiconductor

Design Series.

4. Field Programmable Gate Arrays, John V. Oldfield, Richard C. Dorf, Wiley India.



Web Links:

1. www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/pla.html

2. www.eng.ucy.ac.cy/theocharides/Courses/ECE664/L5.pdf

3. www.soc.napier.ac.uk/~bill/pdf/ICD_C09.PDF

4. https://en.wikipedia.org/wiki/Complex_programmable_logic_device.

*****

http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/pla.html

http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/pla.html

http://www.eng.ucy.ac.cy/theocharides/Courses/ECE664/L5.pdf

http://www.soc.napier.ac.uk/~bill/pdf/ICD_C09.PDF

https://en.wikipedia.org/wiki/Complex_programmable_logic_device



HARDWARE SOFTWARE CO-DESIGN

(Elective-II)

Course Objectives:

COB 1: To demonstrate the students about issues related to hardware software co

design and synthesis.

COB 2: To enable the students to learn about various prototyping and emulation

techniques of the system.

COB 3: To make the students familiar with architectures of 8051, ADSP21060,

TMS320C60 for high performance systems and Data dominated systems.

COB 4: To demonstrate the students about the various compilation techniques and

tools for Embedded Systems.

COB 5: To Enable the students to design and synthesize the system from

specifications.

Course Outcomes:


CO 1: Analyze embedded system’s hardware and software design issues.

CO 2: Develop the applications on 8051, ADSP2106 and TMS320C60

processors

CO 3: Demonstrate modern embedded architectures and compilation

technologies.

CO 4: Interpret the Design, co design by using design verification tools.

CO 5: Build the system from system level specification languages.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1 (K4) 2 3 - 3 3 - 1 - - - -

CO2 (K3) - 2 1 - 3 - - - - - 2

CO3 (K2) - 1 - 2 2 - - 3 - - -

CO4 (K2) - - - - 2 - - - 3 - 1

CO5 (K3) - 2 1 - 3 - - - - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K4) 3 3 1

CO2 (K3) 3 2 -

CO3 (K2) 3 2 1

CO4 (K2) 2 1 -

CO5 (K3) - 2 1

I Semester L P C




UNIT-I

Co- Design Issues:

Co- Design Models, Architectures, Languages, A Generic Co-design Methodology.

Co- Synthesis Algorithms: Hardware software synthesis algorithms: hardware –

software partitioning distributed system cosynthesis.

UNIT-II

Prototyping and Emulation:

Prototyping and emulation techniques, prototyping and emulation environments,

future developments in emulation and prototyping architecture specialization

techniques, system communication infrastructure

Target Architectures:

Architecture Specialization techniques, System Communication infrastructure, Target

Architecture and Application System classes, Architecture for control dominated

systems(8051-Architectures for High performance control), Architecture for Data

dominated systems(ADSP21060, TMS320C60), Mixed Systems.

UNIT–III

Compilation Techniques and Tools for Embedded Processor Architectures:

Modern embedded architectures, embedded software development needs, compilation

technologies, practical consideration in a compiler development environment.

UNIT-IV

Design Specification and Verification:

Design, co-design, the co-design computational model, concurrency coordinating

concurrent computations, interfacing components, design verification, implementation

verification, verification tools, interface verification

UNIT-V

Languages for System – Level Specification and Design:

System – level specification, design representation for system level synthesis, system

level specification languages, Heterogeneous specifications and multi-language co-

simulation, the cosyma system and lycos system.

Text Books:

1. Hardware / Software Co- Design Principles and Practice, Jorgen Staunstrup,

Wayne Wolf, Springer,2009

2. Hardware / Software Co- Design ,Giovanni DeMicheli, Mariagiovanna Sami,

Kluwer Academic Publishers,2002



Reference Books:

1. A Practical Introduction to Hardware/Software Co-design, Patrick R. Schaumont,

Springer Publications,2010

Web Links:

1. https://embedded.eecs.berkeley.edu/Research/hsc/abstract.html

2. http://ieeexplore.ieee.org/document/6172642/

3. http://www.tik.ee.ethz.ch/education/lectures/hswcd/

4. http://ieeexplore.ieee.org/document/715400/

*****

http://ieeexplore.ieee.org/document/6172642/

http://www.tik.ee.ethz.ch/education/lectures/hswcd/



ADVANCED COMPUTER ARCHITECTURE

(Elective-II)

Course Objectives:

COB 1: To make the students to know about the instruction set architectures.

COB 2: To enable the students to understand the advanced concepts of computer

architecture.

COB 3: To demonstrate the students about the advanced concepts computer

architecture.

COB 4: To enable the students to understand multiprocessor & parallel processing

architectures.

COB 5: To demonstrate the students about performance comparisons of modern

and high-performance computers.

Course Outcomes:


CO 1: Compare the performance of different computer architectures with respect

to changing faces of computing and Technology trends.

CO 2: Examine the operation of modern CPUs including pipelining and memory

systems.

CO 3: Explain instruction level parallelism with dynamic scheduling, Static

branch prediction and VLIW approach.

CO 4: Identify the best multi processors with respect to Thread level Parallelism,

Memory architecture and Synchronization.

CO 5: Measure the Practical issues in the interconnecting networks


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1 (K4 ) 2 - 2 3 - - 1 - - - 3

CO2 (K4 ) 2 3 2 - 3 - 1 - - - -

CO3 (K2 ) - 1 - 2 2 1 - 3 - - 1

CO4 (K3 ) 1 2 - 3 - - - - - - -

CO5 (K5 ) - 3 3 - - - 2 - - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K4 ) 3 3 1

CO2 (K4 ) 3 3 1

CO3 (K2 ) 2 1 -

CO4 (K3 ) 3 2 -

CO5 (K5 ) 3 - 2

I Semester L P C




UNIT-I

Introduction:

Fundamentals of Computer Design Fundamentals of Computer design, Changing faces

of computing and task of computer designer, Technology trends, Cost price and their

trends, measuring and reporting performance, Quantitative principles of computer

design, Amdahl’slaw. Instruction set principles and examples- Introduction,

classifying instruction set- memory addressing- type and size of operands, Operations

in the instruction set.

UNIT-II

Pipelining & RISC Aarchitectures:

Pipelines Introduction, basic RISC instruction set, Simple implementation of RISC

instruction set, Classic five stage pipe lined RISC processor, Basic performance issues

in pipelining, Pipeline hazards, Reducing pipeline branch penalties.

Memory Hierarchy Design Introduction, review of ABC of cache, Cache performance,

Reducing cache miss penalty, Virtual memory.

UNIT-III

Introduction to Parallelism:

Instruction Level Parallelism (ILP)-The Hardware Approach: Instruction-Level

parallelism, Dynamic scheduling, Dynamic scheduling using Tomasulo’s approach,

Branch prediction, High performance Instruction delivery- Hardware based

speculation. ILP Software Approach Basic compiler level techniques, Static branch

prediction, VLIW approach, Exploiting ILP, Parallelism at compile time, Cross cutting

issues - Hardware verses Software.

UNIT-IV

Multi Processors:

Multi Processors and Thread Level Parallelism Multi Processors and Thread level

Parallelism- Introduction, Characteristics of application domain, Systematic shared

memory architecture, Distributed shared –Memory architecture, Synchronization.

UNIT-V

Inter Connection Networking:

Inter Connection and Networks Introduction, Interconnection network media, Practical

issues in interconnecting networks, Examples of inter connection, Cluster, Designing

of clusters. Intel Architecture Intel IA-64 ILP in embedded and mobile markets

Fallacies and pit falls



Text Books:

1. Computer Architecture: A Quantitative Approach, 3rd Edition, John L.

Hennessy, David A. Patterson - an Imprint of Elsevier.

2. Advanced Computer Architecture: Parallelism, Scalability, programmability,

Ka hwang, Tata McgrawHill

Reference Books:

1. Modern Processor Design : Fundamentals of Super Scalar Processors, John P.

Shen and Miikko H. Lipasti.

2. Computer Architecture and Parallel Processing - Kai Hwang, Faye A.Brigs.,

MC Graw Hill.

3. Advanced Computer Architecture - A Design Space Approach, DezsoSima,

Terence Fountain, Peter Kacsuk, Pearson Edition.

Web links:

1. http://www.serc.iisc.ernet.in/~viren/Courses/ACA/ACA.htm

2. https://www.iitg.ernet.in/asahu/cs523e/#LectSlides


4. https://www.intel.com/content/www/us/en/architecture-

&Technology/microarchitecture/intel-64-architecture-general.html

*****

http://www.serc.iisc.ernet.in/~viren/Courses/ACA/ACA.htm


https://www.intel.com/content/www/us/en/architecture-

https://www.intel.com/content/www/us/en/architecture-



FRONT END VLSI DESIGN - LAB

Course Objectives:

COB 1: To impart the knowledge on HDL design flow for digital system design.

COB 2: To enable the students to develop HDL code for basic modules of digital

systems.

COB 3: To make the students to simulate and synthesis the HDL design under

given constraints.

COB 4: To familiarize the students with the necessary knowledge about the CAD

tools for design and implementation of given digital systems on FPGA and

CPLD devices.

COB 5: To enable the students to study the test pattern generation for digital

circuits.

Course Outcomes:


CO 1: Develop VHDL code for basic combinational and sequential digital

modules.

CO 2: Test for functional verification of digital circuits with the aid of I-Sim

simulator.

CO 3: Inspect the VHDL code under given user constraints using CAD tools.

CO 4: Analyse the synthesize report in order to meet the given constraints.

CO 5: Utilize the FPGA and CPLD devices for real time verification.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K3) 1 2 - 3 - - - - 3 - 2

CO 2(K3) 1 - - - 3 - - - - - -

CO 3(K4) 2 - 2 2 3 - 1 3 2 - -

CO 4(K4) 2 3 - 2 3 - 1 3 2 - 3

CO 5(K3) 1 - 1 3 2 1 1 2 - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K3) 1 1 2

CO 2(K3) 1 1 1

CO 3(K4) 2 2 3

CO 4(K4) 2 2 3

CO 5(K3) 1 1 2

I Semester L P C

Course Code: 172VD1L01 4 0 3



VLSI Front End Design programs:

Programming can be done using any HDL complier, Verification of the Functionality

of the module using functional Simulator, Timing Simulation for Critical Path time

Calculation, Synthesis of module, Place& Route and implementation of design using

FPGA/CPLD Devices.

List of Experiments:

1. Realization of Logic gates.

2. Parity Encoder.

3. Random Counter

4. Single Port Synchronous RAM.

5. Synchronous FIFO.

6. ALU.

7. UART Model.

8. Dual Port Asynchronous RAM.

9. Fire Detection and Control System using Combinational Logic circuits.

10. Traffic Light Controller using Sequential Logic circuits

11. Pattern Detection using Moore Machine.

12. Finite State Machine (FSM) based logic circuit.

Lab Requirements:

Software:

Industrial standard software with prefectural licence consisting of required simulator,

synthesizer, analyzer etc. in an appropriate integrated environment.

Hardware:

Personal Computer with necessary peripherals, configuration and operating System

and relevant VLSI (CPLD/FPGA) hardware Kits.

Reference Books:

1. A VHDL Primer, Prentice Hall India Learning Private Limited, 3rd Edition ,

2003.

2. Xilinx XST User Guide.

3. Digital Design: Principles and Practices, Pearson; 4th Edition 2005.

https://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf



CMOS MIXED SIGNAL CIRCUIT DESIGN

Course Objectives:

COB 1: To impart the knowledge on CMOS based switched capacitor circuits

COB 2: To motivate the students about design of mixed signal circuits

COB 3: To familiarize the students with fundamentals of data converters

COB 4: To impart the knowledge on different architectures of data converters.

COB 5: To enable he students to design a complete mixed signal system that

includes efficient data conversion and RF circuits.

Course Outcomes:


CO 1: Apply the knowledge of basic sciences and engineering to design CMOS

analog and digital circuits.

CO 2: Analyze the concepts of basic topology in Phase locked loops

CO 3: Illustrate the fundamentals of different types of data converters.

CO 4: Design flash converters, successive approximation type and pipelined

converters.

CO 5: Analyze delta sigma modulators, noise shaping data converting circuits

using filters.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K3) 1 2 - 3 - - - - - - -

CO 2(K4) 2 3 - 3 - - - - - - -

CO 3(K2) - - - 2 - - - - - - -

CO 4(K3) - - - 3 3 - - - - - -

CO 5(K4) 2 3 - 3 - - - - - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K3) 1 1 3

CO 2(K4) 2 2 3

CO 3(K2) - - -

CO 4(K3) 1 3 3

CO 5(K4) 2 2 3

II Semester L P C




UNIT-I

Switched Capacitor Circuits:

Introduction to Switched Capacitor circuits basic building blocks, Operation and

Analysis, Non ideal effects in switched capacitor circuits, Switched capacitor

integrators first order filters, Switch sharing, bi quad filters. Sample and Hold Circuits,

Charge Injection, Other Switched Capacitor Circuits.

UNIT-II

Phased Lock Loop (PLL):

Basic PLL topology, Dynamics of simple PLL, Charge pump PLLs-Lock acquisition,

Phase/Frequency detector and charge pump, Basic charge pump PLL, Non-ideal

effects in PLLs- PFD/CP non-idealities, Jitter in PLLs, Delay locked loops,

applications

.

UNIT-III

Data Converter Fundamentals:

DC and dynamic specifications, Quantization noise, Nyquist rate D/A converters-

Decoder based converters, Binary-Scaled converters, Thermometer-code converters,

Hybrid converters.

UNIT-IV

Nyquist Rate A/D Converters:

Successive approximation converters, Flash converter, Two-step A/D converters,

Interpolating. A/D converters, Folding A/D converters, Pipelined A/D converters,

Time-interleaved converters

UNIT-V

Over Sampling Converters:

Noise shaping modulators, Decimating filters and interpolating filters, Higher order

modulators, Delta sigma modulators with multi bit quantizes, Delta sigma D/A

Text Books:

1. Design of Analog CMOS Integrated Circuits, Behzad Razavi, TMH

Edition,2002

2. CMOS Analog Circuit Design, Philip E. Allen and Douglas R. Holberg,

Oxford University Press, International Second Edition/Indian Edition,2010

3. Analog Integrated Circuit Design, David A. Johns, Ken Martin, Wiley Student

Edition,2016.



Reference Books:

1. CMOS Integrated Analog-to- Digital and Digital-to-Analog converters, Rudy

Van De Plassche, Kluwer Academic Publishers,2003.

2. Understanding Delta-Sigma Data converters-Richard Schreier, Wiley

Interscience,2005

3. CMOS Mixed-Signal Circuit Design, R. Jacob Baker, Wiley Interscience,2009.

4. Analog MOS Integrated Circuits, John Wiley, Gregolian&Temes, 1986

Web Links:

1. http://nptel.iitm.ac.in/courses/


3. http://www.ee.ncu.edu.tw/~jfli/vlsi1/

4. http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/EDA_Chapter1.pdF

****

http://nptel.iitm.ac.in/courses/

http://nptel.iitm.ac.in/courses/


http://www.ee.ncu.edu.tw/~jfli/vlsi1/

http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/EDA_Chapter1.pdF



EMBEDDED SYSTEM DESIGN

Course Objectives:

COB 1: To impart the knowledge on concepts of Embedded systems

COB 2: To facilitate the students to gain knowledge about the basic functions of

embedded system components such as memories, I/O components, Buses.

COB 3: To facilitate the knowledge about hardware and software tools, device

drivers for embedded industry

COB 4: To train the students to design systems, test and critically evaluate

embedded solutions to real world situations

COB 5: To illustrate the case studies of different processors for approaching to

design the real time embedded systems.

Course Outcomes:


CO 1: Describe the differences between the general computing system and the

embedded system.

CO 2: Analyze the hardware components, processor performance of an

embedded system design.

CO 3: Make use of operating systems and embedded programming languages to

develop a real-time system.

CO 4: Utilize modern development tools, CAD tools for integrating software and

hardware components in embedded system designs.

CO 5: Design an embedded system by understanding the various processor

architectures case studies along with its applications.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1 (K5) 3 - - - - - - - - - -

CO2 (K4) 2 3 2 - - 3 - - 3 - -

CO3 (K3) 1 2 1 3 3 2 - - 3 - -

CO4 (K3) 1 2 1 3 3 2 - - 3 - -

CO5 (K3) 1 2 1 3 3 2 - - 3 - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K5) 3 3 2

CO2 (K4) 3 3 1

CO3 (K3) 3 2 -

CO4 (K3) 3 2 -

CO5 (K3) 3 3 3

UNIT-I

Introduction to Embedded Systems:

Definition of Embedded System, Embedded Systems Vs General Computing Systems,

I Semester L P C




History of Embedded Systems, Classification, Major Application Areas, Purpose of

embedded systems, characteristics and quality attributes of embedded systems.

UNIT-II

Embedded Hardware:

Embedded hardware building blocks, Embedded Processors – ISA architecture

models, Internal processor design, processor performance, Board Memory – ROM,

RAM, Auxiliary Memory, Memory Management of External Memory, Board Memory

and performance. Embedded board Input / output – Serial versus Parallel I/O,

interfacing the I/O components, I/O components and performance, Board buses – Bus

arbitration and timing, Integrating the Bus with other board components, Bus

performance.

UNIT-III

Embedded Software:

Device drivers, Device Drivers for interrupt-Handling, Memory device drivers, On-

board bus device drivers, Board I/O drivers, Explanation about above drivers with

suitable examples. Embedded operating systems – Multitasking and process

Management, Memory Management, I/O and file system management, OS standards

example – POSIX, OS performance guidelines, Board support packages, Middleware

and Application Software – Middle ware, Middleware examples, Application layer

software examples.

UNIT-IV

Embedded System Design, Development, Implementation and Testing:

Embedded system design and development lifecycle model, creating embedded system

architecture, introduction to embedded software development process and tools- Host

and Target machines, linking and locating software, getting embedded software into

the target system, issues in Hardware-Software design and co-design. Implementing

the design-The main software utility tool, CAD and the hardware, Translation tools,

Debugging tools, testing on host machine, simulators, Laboratory tools, System Boot-

Up.

UNIT-V

Embedded System Design-Case Studies:

Case studies- Processor design approach of an embedded system –Power PC Processor

based and Micro Blaze Processor based Embedded system design on Xilinx platform-

NiosII Processor based Embedded system design on Altera platform-Respective

Processor architectures should be taken into consideration while designing an

Embedded System

Text Books:

1. Embedded Systems Architecture: A Comprehensive Guide for Engineers and

Programmers, Tammy Noergaard, Elsevier(Singapore) Pvt.Ltd. Publications,2005.

2. Embedded system Design: A Unified Hardware/Software Introduction, Frank

Vahid, Tony D. Givargis, John Wily & Sons Inc,2002.

3. Introduction to Embedded Systems, Shibu K.V, Mc Graw Hill.

Reference Books:



1. Embedded System Design, Peter Marwedel, Science Publishers,2007.

2. Embedded System Design, Arnold S Burger, CMP.

3. Embedded Systems: Architecture, Programming and Design, TMH, Rajkamal.

Web Links:

1. https://www.tutorialspoint.com/embedded_systems/


3. http://www.nptelvideos.in/2012/11/embedded-systems.html

4. http://www.dauniv.ac.in/Embedded_Sys.php

5. https://sites.google.com/site/embeddedsystemddr/ppt

*****

https://www.tutorialspoint.com/embedded_systems/

https://www.tutorialspoint.com/embedded_systems/


http://www.nptelvideos.in/2012/11/embedded-systems.html

http://www.dauniv.ac.in/Embedded_Sys.php

https://sites.google.com/site/embeddedsystemddr/ppt



LOW POWER VLSI DESIGN

Course Objectives:

COB 1: To impart the knowledge on analysis of CMOS digital electronics circuits,

including logic components.

COB 2: To impart the knowledge on CMOS technology-specific layout rules in

the placement and routing of transistors and interconnect, and to verify the

functionality, timing, power, and parasitic effects

COB 3: To demonstrate the students about the Integrated Circuits using Computer

Aided Design (CAD) Tools

COB 4: To train the students to design static CMOS combinational and sequential

logic at the transistor level, including mask layout

COB 5: To facilitate the students to design for higher performance or lower area

using alternative circuit families

COB 6: To enable the students to design project prototype with a satisfactory level

of design constraints

Course Outcomes:


CO 1: Use mathematical methods and circuit analysis models in analysis of

CMOS digital electronics circuits.

CO 2: Apply CMOS technology-specific layout rules in the placement and

routing of transistors and interconnect, and to verify the functionality,

timing, power, and parasitic effects.

CO 3: Compare the different low power VLSI Design techniques that are

available to design an Integrated Circuit for commercial applications

CO 4: Analyze CMOS circuit by knowing the characteristics of various CMOS

technologies and processes.

CO 5: Develop a VLSI project having a set of objective criteria and design

constraints.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1 (K2) - 1 - - 2 - - - - - 1

CO2 (K3) 1 2 - 3 - 2 - - - 3 -

CO3 (K3) - - 1 - 3 - - - - - -

CO4 (K4) 2 3 - 3 3 - 1 - - - 3

CO5 (K3) - - - - - - - - 3 3 2

II Semester L P C





CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K2) - - 1

CO2 (K3) 1 1 3

CO3 (K3) 1 1 3

CO4 (K4) 2 2 3

CO5 (K3) 3 2 -

UNIT-I

Fundamentals of Low Power VLSI Design:

Basics of MOS circuits: MOS Transistor structure and device modeling, MOS

Inverters, MOS, Combinational Circuits – Different Logic Families. Need for Low

Power Circuit Design. Sources of Power dissipation: Dynamic Power Dissipation,

Short Circuit Power, Switching Power, Glitch Power, and Static Power Dissipation.

Short Channel Effects –Drain Induced Barrier Lowering and Punch Through, Surface

Scattering, Velocity Saturation, Impact Ionization, Hot Electron Effect.

UNIT-II

Low-Power Design Approaches:

Low-Voltage Low-Power Design Techniques –Trends of Technology and Power

Supply Voltage, Low-Voltage Low-Power Logic Styles. .

Low-Power Design through Voltage Scaling:

VTCMOS circuits, MTCMOS circuits, Architectural Level Approach –Pipelining and

Parallel Processing Approaches. Switched Capacitance Minimization Approaches:

System Level Measures, Circuit Level Measures and Masklevel Measures.

UNIT-III

Low-Voltage Low-Power Adders & Multipliers:

Introduction, Standard Adder Cells, CMOS Adder’s Architectures – Ripple Carry

Adders, Carry Look-Ahead Adders, Carry Select Adders, Carry Save Adders,

Introduction, Overview of Multiplication, different types of Multiplier Architectures,

Baugh-Wooley Multiplier, Booth Multiplier.

UNIT-IV

Low-Voltage Low-Power Memories:

Basics of ROM, Low-Power ROM Technology, Future Trend and Development of

ROMs, Basics of SRAM, Memory Cell, Pre-charge and Equalization Circuit, Low-

Power SRAM Technologies, Basics of DRAM, Self-Refresh Circuit, Future Trend and

development of DRAM.

UNIT V

Energy recovery and low power latches and Flip Flops:

Energy Recovery Circuit Design: Design with Partially Reversible Logic- Need for

Low Power Latches and Flip Flops- Evolution of Latches and Flip Flops-Quality

Measures for Latches and Flip Flops.



Text Books:

1. Practical Low Power Digital VLSI Design, Gary Yeap, Kluwer academic

publishers,2001.

2. Low Power CMOS VLSI Circuit Design, Kaushik Roy, Sharat prasad, John

Wiley & Sons Inc,2000.

3. CMOS Digital Integrated Circuits – Analysis and Design,Sung, Mo Kang,

Yusuf Leblebici, TMH,2011.

Reference Books:

1. Low Power CMOS Design, Anantha Chadrasekaran and Robert Broderson,

Standard Publishers,2000.

2. Low-Voltage, Low-Power VLSI Subsystems, Kiat-Seng Yeo, Kaushik Roy,

TMH Professional Engineering.

3. Low Power CMOS Design, Anantha Chandrakasan, IEEE Press/Wiley

International,1998

Web Links:

1. http://www.eeherald.com/section/design-guide/Low-Power-VLSI-Design.html

2. http://www.worldscientific.com/doi/abs/10.1142/S0129156496000098?journal

Code=ijhses


4. https://link.springer.com/chapter/10.1007/978-1-4615-2355-0_8

*****

http://www.eeherald.com/section/design-guide/Low-Power-VLSI-Design.html

http://www.worldscientific.com/doi/abs/10.1142/S0129156496000098?journalCode=ijhses

http://www.worldscientific.com/doi/abs/10.1142/S0129156496000098?journalCode=ijhses




DESIGN FOR TESTABILITY

Course Objectives:

COB 1: To impart the knowledge on testability of digital ASIC devices and VLSI

technology trends.

COB 2: To enable the students to understand the manual techniques for generating

tests for faults in digital circuits and Fault diagnosis algorithms.

COB 3: To impart the knowledge on design verification, Test Evaluation, the

concept SCOAP Controllability and Observability.

COB 4: To impart the knowledge on testability measures and the concept of BIST

architecture.

COB 5: To make the students to know the various techniques which are designed

to reduce the amount of input test patterns required to ensure that an

acceptable level of Fault coverage has been obtained.

Course Outcomes:


CO 1: Apply the fundamental concepts of Testing in VLSI design.

CO 2: Apply simulation algorithms for verification and validation.

CO 3: Evaluate a digital system using Testability Measures.

CO 4: Develop skills in the modelling of BIST Architecture and Memory BIST.

CO 5: Assess logic and technology-septic parameters in Boundary Scan

Standards


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1 (K3) 1 2 1 3 - 2 - - 3 - 2

CO2 (K3 ) 1 2 1 - 3 2 - - 3 - 2

CO3 (K5 ) - - 3 - - 3 2 - - - -

CO4 (K3 ) - 2 1 - 3 2 - - - 3 -

CO5 (K5 ) - - 3 - - - 2 - - - 3


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K3) 3 2 -

CO2 (K3 ) 3 4 -

CO3 (K5 ) 3 - 1

CO4 (K3 ) 3 2 -

CO5 (K5 ) 3 - 2

II Semester L P C




UNIT-I

Introduction to Testing:

Testing Philosophy, Role of Testing, Digital and Analog VLSI Testing, VLSI

Technology Trends affecting Testing, Types of Testing, Fault Modeling: Defects,

Errors and Faults, Functional Versus Structural Testing, Levels of Fault Models,

Single Stuck-at Fault.

UNIT-II

Logic and Fault Simulation:

Simulation for Design Verification and Test Evaluation, Modeling Circuits for

Simulation, Algorithms for True value Simulation, Algorithms for Fault Simulation.

UNIT –III

Testability Measures:

SCOAP Controllability and Observability, High Level Testability Measures, Digital

DFT and Scan Design: Ad-Hoc DFT Methods, Scan Design, Partial-Scan Design,

Variations of Scan.

UNIT-IV

Built-In Self-Test:

The Economic Case for BIST, Random Logic BIST: Definitions, BIST Process,

Pattern Generation, Response Compaction, Built-In Logic Block Observers, Test-Per-

Clock, Test-Per-Scan BIST Systems, Circular Self-Test Path System, Memory BIST,

Delay Fault BIST.

UNIT-V

Boundary Scan Standard:

Motivation, System Configuration with Boundary Scan: TAP Controller and Port,

Boundary Scan Test Instructions, Pin Constraints of the Standard, Boundary Scan

Description Language: BDSL Description Components, Pin Descriptions

Text Books:

1. Digital Systems and Testable Design, M. Abramovici, M.A.Breuer and A.D

Friedman, Jaico Publishing House.

2. VLSI Test Principles and Architectures, L-T. Wang, C-W. Wu and X. Wen,

Morgan Kaufman Publishers,2006.

3. Testing of Digital Systems, N.K. Jha and S. Gupta, Cambridge University

Press,2004.



Reference Books:

1. Essentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI

Circuits - M.L. Bushnell, V. D. Agrawal, Kluwer Academic Pulishers

2. Digital Circuits Testing and Testability, P.K. Lala, Academic Press.

3. Advanced Computer Architecture, A Design Space Approach, DezsoSima,

Terence Fountain, Peter Kacsuk, Pearson Edition.

Web links:

1. https://www.slideshare.net/labishettybhanu/trends-and-challenges-in-vlsi

2. http://www.engr.uconn.edu/~tehrani/teaching/test

3. http://nptel.ac.in/courses/106103116/34

4. http://eesemi.com/bist.html

5. http://slideplayer.com/slide/6546550/

*****

https://www.slideshare.net/labishettybhanu/trends-and-challenges-in-vlsi

http://www.engr.uconn.edu/~tehrani/teaching/test

http://nptel.ac.in/courses/106103116/34

http://eesemi.com/bist.html

http://slideplayer.com/slide/6546550/



CAD FOR VLSI

(Elective-III)

Course Objectives:

COB 1: To enable the students to explain the Basic VLSI physical design flow.

COB 2: To enable the student to identify the various algorithms for partitioning,

floor planning and Pin assignment.

COB 3: To make the student to be able to differentiate between global routing and

detailed routing.

COB 4: To impart the knowledge on various algorithms for global and detailed

routing.

COB 5: To train the students to explain the physical design automation of FPGAs

and MCMs

COB6: To enable the student to understand the necessity of chip input and output

circuits necessary to overcome problems of ESD

Course Outcomes:


CO 1: Explain the VLSI physical Design automation

CO 2: Apply Algorithms Required for partitioning, floor planning, pin assignment and

placement

CO 3: Explain global and detailed routing

CO 4: Demonstrate Physical design automation of FPGAs and MCMs.

CO 5: Analyze the Chip input and output circuits to protect against ESD


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1(k2) - 1 - - - - - 3 - - -

CO2(k3) 1 2 - - - - - 3 3 - -

CO3(k2) - 1 - - - - - 3 3 - -

CO4(k2) - 1 - - - - - 3 3 - -

CO5(k4) 2 3 - - - - - 3 3 - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K2) 2 - -

CO2 (K3) 3 2 -

CO3 (K2) 2 1 -

CO4 (K2) 2 - -

CO5 (K4) 3 3 1

II Semester L P C




UNIT-I

VLSI Physical Design Automation:

VLSI Design Cycle, New Trends in VLSI Design Cycle, Physical Design Cycle, New

Trends in Physical Design Cycle, Design Styles, System Packaging Styles;

UNIT-II

Partitioning, Floor Planning, Pin Assignment and Placement:

Partitioning – Problem formulation, Classification of Partitioning algorithms,

Kernighan-Lin Algorithm, Simulated Annealing, Floor Planning – Problem

formulation, Classification of floor

planning algorithms, constraint based floor planning, Rectangular Dualization, Pin

Assignment –problem formulation, Classification of pin assignment algorithms,

General and channel Pin assignments, Placement – Problem formulation,

Classification of placement algorithms, Partitioning based placement algorithms;

UNIT-III

Global Routing and Detailed Routing:

Global Routing – Problem formulation, Classification of global routing algorithms,

Maze routing algorithms, Detailed Routing – Problem formulation, Classification of

routing algorithms, Single layer routing algorithms;

UNIT-IV

Physical Design Automation of FPGAs and MCMs:

FPGA Technologies, Physical Design cycle for FPGAs, Partitioning, Routing –

Routing Algorithm for the Non-Segmented model, Routing Algorithms for the

Segmented Model; Introduction to MCM Technologies, MCM Physical Design Cycle.

UNIT-V

Chip Input and Output Circuits:

ESD Protection, Input Circuits, Output Circuits and noise, On-chip clock Generation

and Distribution, Latch-up and its prevention.

Text Books:

1. Algorithms for VLSI Physical Design Automation, Naveed Shervani, Springer

International Edition,3rd Edition,2005.

2. CMOS Digital Integrated Circuits Analysis and Design, Sung-Mo Kang, Yusuf

Leblebici, TMH, 3rd Edition,2011.

Reference Books:

1. VLSI Physical Design Automation-Theory and Practice , Sadiq M Sait, Habib

Youssef, World Scientific.

2. Algorithms for VLSI Design Automation, S. H. Gerez, Wiley student Edition,

JohnWiley and Sons (Asia) Pvt. Ltd,1999.

3. VLSI Physical Design Automation, SungKyu Lim, Springer International

Edition.



Web Links:

1. www.facweb.iitkgp.ernet.in/~isg/CAD/SLIDES/01-intro.pdf

2. www.facweb.iitkgp.ernet.in/~isg/CAD/index.html

3. nptel.ac.in/courses/106106088/

4. nptel.ac.in/courses/106106089/

*****

www.facweb.iitkgp.ernet.in/~isg/CAD/SLIDES/01-intro.pdf

http://www.facweb.iitkgp.ernet.in/~isg/CAD/index.html

http://www.facweb.iitkgp.ernet.in/~isg/CAD/index.html



DIGITAL SIGNAL PROCESSORS AND ARCHITECTURES

(Elective – III)

Course Objectives:

COB 1: To make the students to know the basics of DSP system, number formats,

various DSP related errors & other nomenclature.

COB 2: To impart the knowledge on pipelining, basics of black fin processor, DSP

basic functional units like MAC.

COB 3: To enable the students to develop a program for a DSP algorithm that can

run on TMS320C54XX processor.

COB 4: To illustrate the features of on-chip peripheral devices and its interfacing

along with its programming details.

COB 5: To impart the knowledge on concepts of digital signal processing

techniques

Course Outcomes:


CO 1: Demonstrate various issues that are needed in implementing DSP

algorithms under given constraints.

CO 2: Interpret the various modules involved in a DSP system

CO 3: Apply the concepts of Interrupts and on-chip peripherals in programming

CO 4: Analyze different architecture details and instruction sets of fixed, floating

point DSPs.

CO 5: Perceive the interfacing of DSP devices with various modules such as

DMA, parallel I/O interface


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K2) 1 2 - 3 - - - 3 - - -

CO 2(K2) - 1 - - 2 - - 3 - - -

CO 3(K3) - - - - - - - - - - -

CO 4(K4) 2 3 - 3 - - 2 - - - 2

CO 5(K5) - - 3 3 - - 3 3 - - 3


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K2) - 1 2

CO 2(K2) - - 2

CO 3(K3) 2 - 3

CO 4(K4) 2 2 3

CO 5(K5) - 2 3

II Semester L P C




UNIT-I

Introduction to Digital Signal Processing:

Introduction, a Digital signal-processing system.

Computational Accuracy in DSP Implementations

Number formats for signals and coefficients in DSP systems, Dynamic Range and

Precision, Sources of error in DSP implementations, A/D Conversion errors, DSP

Computational errors, D/A Conversion Errors, Compensating filter.

UNIT-II

Architectures for Programmable DSP Devices:

Basic Architectural features, DSP Computational Building Blocks, Bus Architecture

and Memory, Data Addressing Capabilities, Address Generation UNIT,

Programmability and Program Execution, Speed Issues, Features for External

interfacing.

UNIT–III

Programmable Digital Signal Processors:

Commercial Digital signal-processing Devices, Data Addressing modes of

TMS320C54XX DSPs, Data Addressing modes of TMS320C54XX Processors,

Memory space of TMS320C54XX Processors, Program Control, TMS320C54XX

Instructions and Programming, On-Chip Peripherals, Interrupts of TMS320C54XX

Processors, Pipeline Operation of TMS320C54XX Processors.

UNIT-IV

Analog Devices Family of DSP Devices:

Analog Devices Family of DSP Devices – ALU and MAC block diagram, Shifter

Instruction, Base Architecture of ADSP 2100, ADSP-2181 high performance

Processor. Introduction to Black fin Processor - The Black fin Processor, Introduction

to Micro Signal Architecture, Overview of Hardware Processing UNITs and Register

files, Address Arithmetic UNIT, Control UNIT, Bus Architecture and Memory, Basic

Peripherals

UNIT-V

Interfacing Memory and I/O Peripherals to Programmable DSP Devices:

Memory space organization, External bus interfacing signals, Memory interface,

Parallel I/Ointerface, Programmed I/O, Interrupts and I/O, Direct memory access

(DMA).

Text Books:

1. Digital Signal Processing, Avtar Singh and S. Srinivasan, Thomson

Publications,2004.

2. A Practical Approach to Digital Signal Processing, K Padmanabhan, R. Vijaya

rajeswaran, Ananthi S, New Age International,2006.

3. Embedded Signal Processing with the Micro Signal Architectures, Woon-

SengGan, Sen M. Kuo, Wiley-IEEE Press,2007.



Reference Books:

1. Digital Signal Processors, Architecture, Programming and Applications,

B.Venkataramani and M. Bhaskar, TMH,2002.

2. DSP Processor Fundamentals, Architectures & Features, Lapsley et al, S.

Chand & Co,2000.

3. Digital Signal Processing Applications Using the ADSP-2100 Family by The

Applications Engineering Staff of Analog Devices, DSP Division, Edited by

Amy Mar, PHI.

4. The Scientist and Engineer's Guide to Digital Signal Processing by Steven W.

Smith, Ph.D., California Technical Publishing, ISBN 0-9660176-3-3.

Web Links:

1. https://www.mathworks.com/products

2. http://www.futureelectronics.com

3. https://www.ti.com › Processors

4. http://ieeexplore.ieee.org/document/826411

****

https://www.mathworks.com/products

http://ieeexplore.ieee.org/document/826411



VLSI SIGNAL PROCESSING

(Elective-III)

Course Objectives:

COB 1: To enable the students to learn about the concept of pipelining and parallel

processing in VLSI. COB 2: To enable the students to identify applications for unfolding algorithm

COB 3: To make the students to understand the analysis of VLSI system with high

speed and low power

COB 4: To equip the students with knowledge of Systolic Design for Space

Representations containing Delays

COB 5: To make the students to understand the concept of Power Reduction and

Estimation techniques in VLSI signal processing

Course Outcomes:


CO 1: Explain parallel and pipelining processing techniques.

CO 2: Identify applications for unfolding algorithm

CO 3: Analyse Systolic Design for Space Representations containing Delays

CO 4: Explain Cook-Toom Algorithm, Fast Convolution algorithm by Inspection

method.

CO 5: Analyze Power Reduction techniques and Power Estimation techniques


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K2) 2 3 3 - 3 3 - 3 - - -

CO 2(K3) 3 1 - - 2 - - - - - -

CO 3(K4) 3 3 2 - - - - - - - -

CO 4(K2) 2 1 1 - 2 - - - - - -

CO 5(K4) 3 3 2 - - - - 3 - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K2) 2 - -

CO 2(K3) 3 - -

CO 3(K4) 3 - -

CO 4(K2) 2 - -

CO 5(K4) 4 - 1

II Semester L P C




UNIT-I

Introduction to DSP:

Typical DSP algorithms, DSP algorithms benefits, Representation of DSP algorithms

Pipelining and Parallel Processing:

Introduction, Pipelining of FIR Digital filters, Parallel Processing, Pipelining and

Parallel Processing for Low Power

Retiming:

Introduction – Definitions and Properties – Solving System of Inequalities – Retiming

Techniques

Introduction to Testing:

Testing Philosophy, Role of Testing, Digital and Analog VLSI Testing, VLSI

Technology Trends affecting Testing, Types of Testing, Fault Modeling: Defects,

Errors and Faults, Functional Versus Structural Testing, Levels of Fault Models,

Single Stuck-at Fault.

UNIT-II

Folding:

Introduction -Folding Transform - Register minimization Techniques – Register

minimization in folded architectures – folding of multirate systems

Unfolding:

Introduction – An Algorithm for Unfolding – Properties of Unfolding – critical Path,

Unfolding and Retiming – Applications of Unfolding

UNIT-III

Systolic Architecture Design:

Introduction – Systolic Array Design Methodology – FIR Systolic Arrays – Selection

of Scheduling Vector – Matrix Multiplication and 2D Systolic Array Design – Systolic

Design for Space Representations contain Delays

UNIT-IV

Fast Convolution:

Introduction,Cook-Toom Algorithm, Winogard algorithm – Iterated Convolution –

Cyclic Convolution – Design of Fast Convolution algorithm by Inspection

UNIT-V

Low Power Design:

Scaling Vs Power Consumption –Power Analysis, Power Reduction techniques –

Power Estimation Approaches Programmable DSP: Evaluation of Programmable

Digital Signal Processors, DSP Processors for Mobile and Wireless Communications,

Processors for Multimedia Signal Processing

Text Books:

1. VLSI Digital Signal Processing- System Design and Implementation, Keshab

K. Parhi, Wiley Inter Science,1998.

2. VLSI and Modern Signal Processing, Kung S. Y, H. J. While House, T.

Kailath,Prentice Hall,1985.



Reference Books:

1. Design of Analog Digital VLSI Circuits for Telecommunications and Signal

Processing, Jose E. France, YannisTsividis, Prentice Hall,1994.

2. VLSI Digital Signal Processing, Medisetti V. K, IEEE Press (NY), USA,1995.

Web Links:

1. www.egr.msu.edu/~mason/iucee/bog1/Joshi-VLSI_Signal_Processing.ppt

2. www.thirudan.com/vlsi/vlsi-signal-processing-parhi-solution-manual.pdf

3. www.umiacs.umd.edu/~joseph/classes/enee640/

4. https://www.safaribooksonline.com/library/view/vlsi-digital-

signal/9780471241867/

5. www.xiangyinsi.org/vlsi/vlsi-dsp-parhi-solution-manual.pdf

www.egr.msu.edu/~mason/iucee/bog1/Joshi-VLSI_Signal_Processing.ppt

https://www.safaribooksonline.com/library/view/vlsi-digital-signal/9780471241867/

https://www.safaribooksonline.com/library/view/vlsi-digital-signal/9780471241867/

http://www.xiangyinsi.org/vlsi/vlsi-dsp-parhi-solution-manual.pdf



SYSTEM ON CHIP DESIGN

(Elective-IV)

Course Objectives:

COB 1: To train the students to know the fundamental concepts of SOC Design.

COB 2: To impart the knowledge on interconnection necessities between

computational block and memory block.

COB 3: To enable the students to understand the VLIW Processors, Superscalar

Processors etc.

COB 4: To demonstrate the hardware and software programmability verses

performance.

COB 5: To impart the knowledge on designing SoCs.

Course Outcomes:


CO 1: Explain all the building blocks of System-on-Chip.

CO 2: Classify the concept of processors and instruction handling.

CO 3: Analyze vector, VLIW and superscalar processors.

CO 4: Design a Memory as part of System-on-Chip.

CO 5: Illustrate the concepts of interconnect optimization and configuration in

System-on-Chip.


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1 (K2) - - - 2 - 1 - - 3 - -

CO2 (K2) - - - 2 - 1 - - 3 - -

CO3 (K4) 2 3 2 3 - 3 1 3 3 - 3

CO4 (K3) 1 2 1 3 - 2 - 3 - - 2

CO5 (K2) - - - 2 - 1 - - 3 - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1 (K2) 2 - -

CO2 (K2) 2 - -

CO3 (K4) 3 - 1

CO4 (K3) 3 2 -

CO5 (K2) 2 - -

II Semester L P C




UNIT-I

Introduction to the System Approach:

System Architecture, Components of the system, Hardware & Software, Processor

Architectures, Memory and Addressing. System level interconnection, an approach for

SOC Design, System Architecture and Complexity.

UNIT- II

Processors:

Introduction, Processor Selection for SOC, Basic concepts in Processor Architecture,

Basic concepts in Processor Micro architecture, Basic elements in Instruction

handling. Buffers: minimizing Pipeline Delays, Branches, More Robust Processors,

Vector Processors and Vector Instructions extensions, VLIW Processors, Superscalar

Processors.

UNIT-III

Memory Design for SOC:

Overview of SOC external memory, Internal Memory, Size, Scratchpads and Cache

memory, Cache Organization, Cache data, Write Policies, Strategies for line

replacement at miss time, Types of Cache, Split – I, and D – Caches, Multilevel

Caches, Virtual to real translation, SOC Memory System, Models of Simple Processor

–memory interaction.

UNIT- IV

Interconnect Customization and Configuration:

Inter Connect Architectures, Bus: Basic Architectures, SOC Standard Buses, Analytic

Bus Models, Using the Bus model, Effects of Bus transactions and contention time.

SOC Customization: An overview, Customizing Instruction Processor,

Reconfiguration Technologies, Mapping design onto Reconfigurable devices,

Instance- Specific design, Customizable Soft Processor,

UNIT- V

Application Studies / Case Studies:

SOC Design approach, AES algorithms, Design and evaluation.

Text Books:

1. Computer System Design System-on-Chip, Michael J. Flynn and Wayne Luk,

Wiely India Pvt. Ltd.

2. ARM System on Chip Architecture, Steve Furber –2nd Edition, Addison

Wesley Professional,2000.

Reference Books:

1. Design of System on a Chip: Devices and Components, Ricardo Reis, 1st

Edition, Springer,2004.

2. Co-Verification of Hardware and Software for ARM System on Chip Design

(Embedded Technology), Jason Andrews,Newnes, BK and CDROM.

3. System on Chip Verification, Methodologies and Techniques, Prakash

Rashinkar, Peter Paterson and Leena Singh L, Kluwer Academic

Publishers,2001.



Web Links:

1. https://en.wikipedia.org/wiki/System_on_a_chip

2. https://www.peterindia.net/System-On-ChipLinks.html

3. https://www.ieee-socc.org/

4. http://nptel.ac.in/courses/108102045/10

*****

https://en.wikipedia.org/wiki/System_on_a_chip



OPTIMIZATION TECHNIQUES IN VLSI DESIGN

(Elective-IV)

Course Objectives:

COB 1: To impart the knowledge on statistical modelling methods such as Monte

Carlo techniques and Pelgroms mode

COB 2: To demonstrate the students about implementation issues for digital design

automation including optimization techniques.

COB 3: To make the students to know about the concept of optimization

algorithms and their applications.

COB 4: To expose students to the complexities and design methodologies of

current and advanced VLSI design technologies.

COB 5: To impart the knowledge on Physical Design Process such as Partitioning,

Floor planning, Placement and Routing

Course Outcomes:


CO 1: Compare various statistical modelling methods such as Monte carlo

techniques, Pelgroms methods, principle component based and quad tree

based modelling methods.

CO 2: Analyze the systems by using concepts of high level and gate level

statistical methods.

CO 3: Explain the concepts of geometric programming and convex functions.

CO 4: Develop the real time applications using optimization techniques such as

Genetic Algorithms.

CO 5: Apply CMOS technology -specific layout rules in the placement and

routing of transistor sand to verify the functionality, timing and power


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K2) - 1 - 2 2 - - - - - -

CO 2(K4) 2 3 2 3 - - - - - - -

CO 3(K2) - 1 - 2 2 - - - - - -

CO 4(K3) - - - 3 - 2 - - - - -

CO 5(K3) 1 2 - 3 3 - - - - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K2) - - -

CO 2(K4) 3 3 2

CO 3(K2) - - -

CO 4(K3) 3 - -

CO 5(K3) 3 2 -

II Semester L P C




UNIT-I

Statistical Modeling:

Modeling sources of variations, Monte Carlo techniques, Process variation modeling-

Pelgroms model, Principle component based modeling, Quad tree based modeling,

Performance modeling-Response surface methodology, delay modeling, interconnect

delay models.

UNIT-II

Statistical Performance, Power and Yield Analysis:

Statistical timing analysis, parameter space techniques, Bayesian networks Leakage

models, High level statistical analysis, Gate level statistical analysis, dynamic power,

leakage power, temperature and power supply variations, High level yield estimation

and gate level yield estimation.

UNIT- III

Convex Optimization:

Convex sets, convex functions, geometric programming, trade-off and sensitivity

analysis, Generalized geometric programming, geometric programming applied to

digital circuit gate sizing, Floor planning, wire sizing, Approximation and fitting-

Monomial fitting, Max monomial fitting, Posynomial fitting.

UNIT-IV

Genetic Algorithm:

Introduction, GA Technology-Steady State Algorithm-Fitness Scaling-Inversion GA

for VLSI Design, Layout and Test automation- partitioning-automatic placement,

routing technology, Mapping for FPGA- Automatic test generation- Partitioning

algorithm Taxonomy-Multi-way Partitioning Hybrid genetic-encoding-local

improvement-WDFR Comparison of CAS-Standard cell placement-GASP algorithm-

unified algorithm.

UNIT-V

GA Routing Procedures and Power Estimation:

Global routing-FPGA technology mapping-circuit generation-test generation in a GA

frame work-test generation procedures, Power estimation-application of GA-Standard

cell placement-GA for ATG problem encoding- fitness function-GA Vs Conventional

algorithm.

Text Books:

1. Statistical Analysis and Optimization for VLSI: Timing and Power

AshishSrivastava, Dennis Sylvester, David Blaauw, Springer,2005.

2. Genetic Algorithm for VLSI Design, Layout and Test Automation,

PinakiMazumder, E.Mrudnick, Prentice Hall,1998.

3. Introduction to Optimum Design, Elsevier, J. S. Arora, 2nd Edition,2004.



Reference Books:

1. Convex Optimization, Stephen Boyd, LievenVandenberghe, Cambridge

University Press,2004.

2. Multi-Objective Optimization Using Evolutionary Algorithms, K. Deb, John

Wiley,2003.

3. Optimization for Engg. Design: Algorithms & Examples, K. Deb, Prentice

Hall India,2006.

4. Engineering Optimization: Theory & Practice, S. S. Rao, New Age

International (P) Ltd, 3rd Edition, 1996, Reprint: June,2008.

Web Links:

1. https://books.google.co.in/books?isbn=0387265287

2. https://drive.google.com/file/d/0BzoKWH8M1BoTR1k0TGxfM3o0UU0/view

3. https://drive.google.com/file/d/0BzoKWH8M1BoTa21za3QxUU92SEk/view

4. www.egr.msu.edu/~kdeb/papers/nbook.pdf

https://books.google.co.in/books?isbn=0387265287

https://books.google.co.in/books?isbn=0387265287

https://drive.google.com/file/d/0BzoKWH8M1BoTR1k0TGxfM3o0UU0/view

https://drive.google.com/file/d/0BzoKWH8M1BoTa21za3QxUU92SEk/view

http://www.egr.msu.edu/~kdeb/papers/nbook.pdf



SEMICONDUCTOR MEMORY DESIGN AND TESTING

(Elective-IV)

Course Objectives:

COB 1: To impart the knowledge on different types of semiconductor memories.

COB 2: To make the students to study about architecture and operations of

different semiconductor memories.

COB 3: To enable the students to study reliable memories and to overcome effects

of radiation

COB 4: To demonstrate the students about low power design techniques and

methodologies.

COB 5: To enable the students to use advanced memory technologies, various high

density memories and packages.

Course Outcomes:


CO 1: Analyze the different RAM architectures and interconnects.

CO 2: Classify High-Performance Subsystem Memories.

CO 3: Explain different fault modeling and testing techniques.

CO 4: Develop reliable memory architectures by considering radiation affects.

CO 5: Identify new developments in semiconductor memory design


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO 1(K4) 2 3 - 3 - - - - - - -

CO 2(K4) 2 3 - 3 - - - - - - -

CO 3(K2) - - - 2 - - - - - - -

CO 4(K3) 1 2 - 3 - - - - - - -

CO 5(K3) 1 2 - 3 - - - - - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO 1(K4) 3 - 1

CO 2(K4) 3 - 1

CO 3(K2) 2 - -

CO 4(K3) 3 - -

CO 5(K3) 2 - -

II Semester L P C




UNIT- I

Random Access Memory Technologies:

SRAM – SRAM Cell structures, MOS SRAM Architecture, MOS SRAM cell and

peripheral circuit operation, Bipolar SRAM technologies, SOI technology, Advanced

SRAM architectures and technologies, Application specific SRAMs, DRAM – DRAM

technology development, CMOS DRAM, DRAM cell theory and advanced cell

structures, BICMOS DRAM, soft error failure in DRAM, Advanced DRAM design

and architecture, Application specific DRAM..

UNIT-II

Non-volatile Memories:

Masked ROMs, High density ROM, PROM, Bipolar ROM, CMOS PROMS, EPROM,

Floating gate EPROM cell, One time programmable EPROM, EEPROM, EEPROM

technology and architecture, Non-volatile SRAM, Flash Memories (EPROM or

EEPROM), advanced Flash memory architecture

UNIT-III

Memory Fault Modeling Testing and Memory Design for Testability andFault

Tolerance:

RAM fault modeling, Electrical testing, Pseudo Random testing, Megabit DRAM

Testing, nonvolatile memory modeling and testing, IDDQ fault modeling and testing,

Application specific memory testing, RAM fault modeling, BIST techniques for

memory.

UNIT-IV

Semiconductor Memory Reliability and Radiation Effects:

General reliability issues RAM failure modes and mechanism, Non-volatile memory

reliability, reliability modeling and failure rate prediction, Design for Reliability,

Reliability Test Structures, Reliability Screening and qualification, Radiation effects,

Single Event Phenomenon (SEP), Radiation Hardening techniques, Radiation

Hardening Process and Design Issues, Radiation Hardened Memory characteristics,

Radiation Hardness Assurance and Testing, Radiation Dosimetry, Water Level

Radiation Testing and Test structures

UNIT-V

Advanced Memory Technologies and High-density Memory Packing

Technologies:

Ferroelectric RAMs (FRAMs), GaAs FRAMs, Analog memories, magneto resistive

RAMs (MRAMs), Experimental memory devices, Memory Hybrids and MCMs (2D),

Memory Stacks and MCMs (3D), Memory MCM testing and reliability issues,

Memory cards, High Density Memory Packaging Future Directions.

Text Books:

1. Semiconductor Memories Technology, Ashok K. Sharma, Wiley,2002.

2. Advanced Semiconductor Memories, Architecture, Design and Applications,

Ashok K.Sharma, Wiley,2002.

3. Modern Semiconductor Devices for Integrated Circuits,Chenming C Hu, 1st

Ed., Prentice Hall.



Reference Books:

1. Memory Technology, Design and Testing, Bernard Courtois, Thomas

Wik, YervantZorian, IEEE Computer Society Press,2002.

2. High Performance Memory Testing: Design Principles, Fault Modeling and

Self-Test, R. Dean Adams, Springer publications,2003.

3. High Speed Semiconductor Devices,Anjan Ghosh, NPTEL Courseware,2009.

Web links:

1. www.vlsifacts.com/classification-of-semiconductor-memories-and-computer-

memories/

2. http://technav.ieee.org/tag/682/emerging-memory-technologies

3. http://ieeexplore.ieee.org/Xplore/home.jsp

*****

www.vlsifacts.com/classification-of-semiconductor-memories-and-computer-memories/

www.vlsifacts.com/classification-of-semiconductor-memories-and-computer-memories/



BACK END VLSI DESIGN LAB

Course Objectives:

COB 1: To train the students on mathematical methods and circuit analysis models

in analysis of CMOS digital electronics circuits.

COB 2: To impart the knowledge on technology-specific layout rules in the

placement and routing of Transistors.

COB 3: To enable the students to understand the characteristics of CMOS to

design different circuits.

COB 4: To facilitate the knowledge to design a significant VLSI design project

having a set of objective criteria and design constraints.

COB 5: To make the students to gain knowledge in designing integrated circuits

using Computer Aided Design (CAD) Tools.

COB 6: To enable the students to estimate and optimize combinational circuit

delay and power using Schematics.

Course Outcomes:


CO 1: Identify different HDL description styles for various logic designs.

CO 2: Compare schematics for all digital designs and implement using

simulation tools.

CO 3: Extracted layouts physically through various Back end EDA Tools.

CO 4: Examine the performance extracted layouts through DRC,LVS, and PEX

CO 5: Evaluate the performance of combinational and sequential designs for its

speed and other performance parameters


CO/PO PO 1

(K5)

PO 2

(K4 )

PO 3

(K5)

PO 4

(K3)

PO 5

(K3)

PO 6

(K4)

PO 7

(K6)

PO 8

(K2)

PO 9

(K2)

PO 10

(K2)

PO 11

(K4)

CO1(K3) - 2 1 3 - - - - - - -

CO2(K5) 3 3 3 3 - - - - - - -

CO3(K4) - - 2 3 3 3 - - 3 - -

CO4(K6) 3 - - - - - - - 3 3 3

CO5(K5) 3 3 3 3 - 3 2 - - - -


CO / PSO PSO 1

(K3 )

PSO 2

(K4 )

PSO 3

(K6)

CO1(K3) 1 1 3

CO2(K5) 3 3 3

CO3(K4) 2 2 3

CO4(K6) 3 3 3

CO5(K5) 3 3 3

II Semester L P C

Course Code: 172VD2L02 4 0 3



List of Experiments:

1. Digital circuit simulation:

a. Design and verify the functional response of Shift Register by describing it in

Verilog HDL.

b. Design and verify the functional response of Adders by describing it in Verilog

HDL.

2. IIR/FIR design using Matlab Simulink

Note:-The students are required to design schematics and implement the layout of the

following experiments using CMOS 130nm Technology with Mentor Graphics Tool.

3. Schematics and its functional response verification for the following Circuits

a. CMOS Inverter b. Universal gates c. Full Adder. d. D-latch

e. Ring Counter f. Differential Amplifier g. SRAM

4. Layout extraction for the following Circuits



5. Performing DRC for the following Circuits



6. Performing LVS / Net list extraction for the following Circuits



7. PEX estimation for the following logic circuits



Reference Books:

1. Mentor Graphics user guide

2. Digital Integrated Circuits, Pearson, 2nd Edition, 2003.

3. Design of Analog CMOS Integrated Circuits, BehzadRazavi, TMH Edition.

4. CMOS: Circuit Design, Layout and Simulation, Baker, Li and Boyce, PHI.

program structure and syllabus

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