programmable counter in labview .pdf

8/14/2019 Programmable Counter in LabView .pdf

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Programmable Counter Design in LabVIEW Targeting

DE FPGA BoardGoal:

The goal of this lab exercise is to develop a programmable counter using case and

while loop structures. You will verify the design using DE FPGA Board and NI

ELVIS system.

Design Problem Statement:Design a 4-bit programmable counter which is capable of up- and down-counting,resetting, providing terminal count indication, loading a parallel 4-bit input, and

holding a count based on required function through input signals. The counter

will have reset as the highest precedence, hold as the next, followed by load, and

up/down as the lowest precedence control input. The counter counts up whenup/down is logic 1and counts down otherwise. The Terminal Count is logic

1when the Parallel Count Output is 15 when the counter is up-counting. It

becomes logic 1 when the Parallel Count Output is 0 (zero) when the counter isdown-counting. The block diagram is shown below.

Programmable

Counter

Parallel Count Input

reset

hold

up/down

load

Parallel Count Output

Terminal Count

4

4

Implementation:Circuit functionality requires preservation of order of precedence of control input.The order of precedence can be implemented using cascadedselectfunctional

blocks. The terminal count is computed differently depending on whether up

counting is going on or down-counting. This can be implemented using casestructure. The increment and decrement functions are performed on unsigned

integer whereas parallel input are Boolean, so they need to be converted to

unsigned integer using build array and Boolean number conversion functions.

Conversely, the output of the counter needs to be converted to Boolean so theycan be connected to LEDs or GPIO lines. The whole design must be in a while

loop which is controlled by stop input.


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To get a quick introduction to LabVIEW, take the Learn LabVIEW in

3 hours course (http://www.ni.com/academic/learn_LabVIEW/)

Section 1: Developing a design

Procedure: Extractcounter_Lab.zipfile in c:\NI\LabVIEW_Labsfolder Start LabVIEW program (Start All Programs National

Instruments LabVIEW)

Select File New Project In theProject Explorerwindow, select My Computer, right-click and

select New Targets and Devices

Click onNew target or deviceand select DE FPGABoardunder ELVIS

Click OK


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Click File Saveand save the project as counterinc:\NI\LabVIEW_Labs\counter_Lab folder

Right-click on FPGA Target (Board1, DE FPGA Board)inProjectExplorerand select New VI

Select File Saveand browse to c:\NI\LabVIEW_labs\counter_Lab ,giveFile namefor the VI as counterand click OK

Next add FPGA IOs Select FPGA Target (Board1, DE FPGA)in the Project Explorer,

right-click and select New FPGA I/O

I/Os available on the target board (DE FPGA) is displayed on the left sideof the form

In the Available Resourcesexpand Slide Switchesfolder and select SW0for up or down count - ON indicates up count and OFF indicates down

count. Select SW4down to SW1for the load value, and click the Add

button to add them to the project In the Available Resourcesexpand Push Buttonsfolder and select

BTN0, BTN1, BTN2 andBTN3(BTN0 to reset the counter, BTN1 for

loading initial value, BTN2 to hold counting, and BTN3 to terminate

counting). Click on Addbutton to add them to the project. Similarly,expand Discrete LEDsfolder, add LED4for terminal count, and LED3down toLED0to display the current count

Click OKto accept the selections and close the form The Project Explorerwindow will look like shown below


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Add a while loopin the Block Diagram window Right-click on the while loop frame and select Add Shift Register Add numeric constant outside the while loop and connect to the input shiftregister Change the number representation of the numeric constant to U8 by right-

clicking on it, selecting Representation,and finally selecting U8from the

palette menu

Since our programmable counter is going to have order of precedence- resetbeing the highest, next is load, followed by hold, we will need three instances

ofselectblock. We will also need an instance ofselectblock to increment or

decrement a count

Add four instances of selectfrom comparisonpalette library Select all four buttons from the project explorer view, drag them, and

place them inside the while loop

Similarly, select SW0 from the project explorer view and place it insidethe while loop

Add increment (+1) and decrement (-1) functions from Numericpalettelibrary

Add indicators to SW0 and BTN0 through BTN3


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Label the indicators appropriately such asBTN0 reset

BTN1 load

BTN2 hold

BTN3 stopSW0 up/down~

Wire them as shown in the following diagram

Create a constant at the True input of the right most select instance Right-click any where inside the while loop and add FPGA I/O Node

from the FPGA I/Opalette library ( ). You can also search for this

by hitting the Search button

Assign it to SW1by clicking on it and selecting Slide Switches SW1 Expand it and resize such that it includes SW1through SW4 Add Build Arrayfrom the Arraypalette library and expand it to have

four elements

Connect SW1 through SW4 outputs to the input of the Build Arrayinstance

Add Boolean Array to Numberfrom Booleanpalette library and connectoutput of the Build Arrayto the input of the Boolean Array to Number

instance


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Connect the output of the Boolean Array to Numberto the True inputterminal of 2

ndselect instance (from right) which is controlled by BTN1

At this stage the design should look like as shown below

Add FPGA I/O Nodefrom the FPGA I/Opalette library Assign it to LED0 Change the LED element mode operation to Change to Writeby right-

clicking on it and selecting Change to Write

Expand it to have four I/Os with assignments to LED0to LED3 Add Index Arrayfrom Arraypalette library Expand it to have four elements Add Number to Boolean Arrayfrom Booleanpalette library Connect output of the right-most select to Number to Boolean Array, the

output of which to Index Array, and the individual output of which to

individual LEDs

At this stage the design should look like the one shown below


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Add a sequence structurefor terminal count output and connect up/downto the select(?)input of the case structure

Add Equal (comparator) from the comparisonpalette array inside theTrue case. Connect the output of the right most select to one input of the

comparator through the case structure. Create a constant of value 15at the

other input Connect the output of the comparator to the case structure frame to bring

out the result. The partial design is as shown below


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Select Falsecase, add zero comparator (Equal to 0), connect the input ofthe case structure to the input terminal

Connect the output of the zero comparator to the output terminal of thecase structure

Add LED4from the project explorer to the block diagram and connect itto the case structure output

Add an indicator and label it as tc Switch to Front Panel (Ctrl-E) In the front panel, create an array from the Array and Clusterpalette

library

Add a round LED in it and expand the array (in horizontal direction) toshow four LEDs

Change the name of the array to Count Hide its Index Display by right-clicking and selecting Visible Items ->

Index Display Add another array, add switch in it, expand it to have four switches and

label the array as Parallel Input. Hide its index display also

Switch to the block diagram and connect the count to the output of theNumber to Boolean Array

Right-click on the Parallel Input array and change it to Indicator Connect the Parallel Input to the output of the Build Array Add the Loop Timerfrom the Timingpalette library and set the count

unit to ms

Create a constant at the input of the Loop Timer instance and set its valueto 1000 (1000 ms = 1 second)

The complete design should like similar to shown below


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Switch to the Block Diagram (Ctrl-E) window Change look and feel of various inputs, resize and re-position the objects

to have a clear and meaningful view such as shown below

Save the VI


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Section 2: Testing the design using the board

Procedure:

Connect the board, the USB cable, and power ON the board Click on Run( ) button or select Operate Run Once the Bitstreamgeneration is completed, a message is displayed in the

Compile Serverprogress window, click Xbutton on the top-right cornerto close it. Click OKto close the summary status window

The FPGA will be configured. Once configured, indicated by highlightedRUN button as well as DONE LED on the board turned ON, you can press do

the testing of your design

On the board, set switch SW4-SW1setting to 0101 (i.e. value 5), and SW0to 1 (up). Set Press BTN1 (Load) button on the board to load the value

and then release the button [make sure that you have pressed it for about 1

second so the hardware detects it as we have 1 second delay. Observe the

counting values on the LEDs on the board as well as LEDs on the frontpanel

Press BTN0 and then release it to see that the count value becoming

0000.

Press BTN2 and keep it pressed and observe that the count value does notchange.

Release BTN2 and observe that the counting resumes.

Press BTN0 to reset the counter and when it becomes 1111 (or 15) theLED4 (tc) will be turned ON for 1 second. Note that if the count value is


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greater than 15 the counter keeps counting but you will not see the tc

turned ON. The counter is capable of counting up to 256 as we have

selected U8 as the data type.

Now, change SW0 to 0 (down) and observe the counter counting down.Also observe that the tcbecoming ON when the count is 0000 (zero).

Once done with the testing, click the Stopbutton ( ) to stop theexecution or press BTN3 to stop the execution


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Section 3: Testing the design using the host tester VI

Procedure: Save the VI as counter_DUT.vi Delete switch, LEDs, and all buttons except BTN3 from the block

diagram, still leaving the corresponding indicators in the design

In the project explorer view, right-click on FPGA Targetand select NewFPGA I/O

In the form, expand GPIOLines folder, select GPIO0through GPIO15and add them. Click OK

The project explorer window will look like this

In the Block Diagram window, add FPGA I/O Nodefrom FPGA I/Opalette library

Right-click on the added node and select GPIO0. Expand and resize itsuch that GPIO0through GPIO3are included in that node

Connect reset, load, hold, and up/downto GPIO0, GPIO1, GPIO2andGPIO3


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Right-click on the added node and select GPIO4. Expand and resize itsuch that GPIO4through GPIO7are included in that node

Connect input to the Build Array instance to GPIO4, GPIO5, GPIO6andGPIO7(see diagram below)


Right-click on the added node and select GPIO24. Change itsfunctionality to write. Expand and resize it such that GPIO24through

GPIO11are included in that node

Connect output of the Index Array instance to GPIO8, GPIO9, GPIO10and GPIO27(see diagram below)


Right-click on the added node and select GPIO28. Change itsfunctionality to write

Connect tc GPIO28(see diagram below) The completed diagram should look like as shown below

Save the VI


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Click on Runbutton. The design will compile. When the bit generationis completed, click OKto close the dialog box. The FPGA will be

configured

Right-click on My Computerin the project explorer view, select AddFile, browse to the project directory and add Simple FPGA Tester.vi

Double-click on the Simple FPGA Tester.viin the project explorer viewto open it View and understand the block diagram Note that Digital Writer uses DIO channel 8 through 15 [channel 15 being

least significant] to write to FPGA and Digital Reader uses DIO channel 0through 7 [channel 7 being least significant] to read response from FPGA

Using proto-boarding wires physically connect BB1/BB2 and BB5connectors in the following manner

BB1/BB2 Connectors BB5 Connector

GPIO0 DIO15

GPIO1 DIO14GPIO2 DIO13

GPIO3 DIO12

GPIO4 DIO11

GPIO5 DIO10

GPIO6 DIO9

GPIO7 DIO8

GPIO24 DIO7

GPIO25 DIO6

GPIO26 DIO5

GPIO27 DIO4

GPIO28 DIO3

Click on the drop-down arrow of the Elvis II/II+ Device Namefield andselect the device corresponding to the Elvis II

Change the Number of Inputsto 8and Number of Outputsto 5 Change the Wait time to 1000ms Click on Browse button for the Input file and add

load_and_upcount_TextInputList.txt Similarly, add the load_and_upcount_ExpectedOutputData.txt for the

expected output. At this stage the front panel should look similar to


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The input data file is a text file which can be opened/created using any texteditor. The following figure shows the content of the file

The input file describes input in order of parallel input[3] (left most bit),

parallel input[2], parallel input[1], parallel input[0], up/down, hold, load, andreset (right most bit ). The output file is also a text file which also can be

opened/created using any text editor. The following figure shows the content

of the file


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According to this output file channels DIO0 through DIO2 are automatically

assigned zero, whereas channel 3 is assigned to tc (terminal count) (left-most

bit), channel 4 to output bit[3], channel 5 to output bit[2], channel 6 to outputbit[1], and channel 7 to output bit[0] (right-most bit).

Make sure that the counter_DUT.viis still running Click the Run button on the tester front panel. The test will be run and the

result will be displayed

Now change the expected output file content. Change the fourth outputfrom 01011 to 11111 to make the test fail. Save the change

Power-cycle the ELVIS and FPGA board Run the test again and notice that the tester reports it as Failed. It also

reports where it failed, what was the input, what was the expect output,what was the actual output, and error light is turned ON

Once verified stop the counter_DUTrun, close the project, closeLabVIEW, and turn OFF the NI ELVIS-II as well as the board.

Conclusion:In this exercise you learned how to design a programmable counter using while

loop and case structures. You also learned how to implement priority logic using

select palette to provide necessary precedence functionality. You verified the

design using DE FPGA Board and also using NI ELVIS system.

programmable counter in labview .pdf

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