programmable logic system design
DESCRIPTION
Programmable Logic System Design. Lab03- Simulation Preliminary SOC LAB . Chang-Ting Chen 2013.10. Lab Description. 認識實驗版 Spartan-3 Starter Kit Board 撰寫 VHDL ,利用 Switch 模組控制 LED 模組 定義 I/O 腳位 (I/O Pins) ,產生燒錄檔 (*.bit) ,燒錄並觀察在 FPGA 板子上的結果. Spartan-3 Starter Kit Board. - PowerPoint PPT PresentationTRANSCRIPT
-
Programmable Logic System DesignLab03- Simulation PreliminarySOC LAB.
Chang-Ting Chen2013.10
-
Lab Description Spartan-3 Starter Kit Board
VHDL Switch LED
I/O(I/O Pins)(*.bit) FPGA
-
Spartan-3 Starter Kit Board
-
Create Xilinx Project Xilinx Project Lab1
Device Family Spartan3
Device (xc3s200/xc3s400)
Package ft256
Xilinx
-
Use Switches to Light LEDslibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demo isPort (swt : in std_logic_vector(7 downto 0);led : out std_logic_vector(7 downto 0));end demo;
architecture Behavioral of demo isbeginled(7 downto 0)
-
Pin AssignmentAdd the Implementation Constraints File
-
Pin Assignment (Contd)FPGA Loc
-
Pin Assignment (Contd)Properties of Generate Programming File Properties
-
Pin Assignment (Contd)Check Create Bit File ()FPGA Start-Up Clock => JTAG Clock
-
Programming Process
-
Programming Process (Contd)Select Boundary-Scan Mode ()Select Automatically connect and identify ()
-
Detecting Boundary-scan Chain
-
Assign Configuration File to FPGA
-
Bypass Platform Flash PROM
-
Program ProcessProgram
-
Programming succeeded Verify OK
-
AssignmentVHDL Download