programmers reference manualapplication-notes.digchip.com/027/27-46117.pdf · intel® 80310 i/o...

Intel® 80310 I/O ProcessorChipset DMA Support LibraryProgrammers Reference Manual

December 2001

Document Number: 273559-002

2 Programmers Reference Manual

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Copyright© Intel Corporation, 2001

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Programmers Reference Manual 3

Contents

Contents1.0 Intel® Embedded I/O Processors DMA Library ...........................................................................9

1.1 DMA Controller .....................................................................................................................91.2 Introduction to DMA Library ................................................................................................10

1.2.1 The DMA Library Provides Intel Customers...........................................................101.2.2 The DMA Testbench..............................................................................................10

1.3 Highlights ............................................................................................................................111.3.1 DMA Library Architecture.......................................................................................111.3.2 Testbench Features ...............................................................................................11

1.4 Document Organization ......................................................................................................121.5 Recommendation on How to Use this Library ....................................................................121.6 Further Enhancements .......................................................................................................13

1.6.1 Performance Related .............................................................................................131.6.2 Features Related ...................................................................................................13

2.0 Related Documents .....................................................................................................................15

3.0 Definition of Terms Used and Acronyms ..................................................................................17

4.0 Basic Assumptions .....................................................................................................................19

4.1 Multi-Tasking Environment .................................................................................................194.2 Library Provides Memory Space for Descriptors ................................................................194.3 Uses Processor Modes IRQ, FIQ and Abort for Operations and Error Handling................194.4 Frame Management ...........................................................................................................194.5 Compiler .............................................................................................................................194.6 Upper Bound on Number of DMA Threads Created ...........................................................19

5.0 DMA Library Architecture ...........................................................................................................21

5.1 Overview.............................................................................................................................215.2 DMA Library Data Structures..............................................................................................22

5.2.1 Public Data Structures: Declaration .......................................................................225.2.2 Private Data Structures: Declarations....................................................................225.2.3 DMA Library Data Structures: Descriptions ...........................................................25

5.2.3.1 struct Thread_DMA Data Structure........................................................255.2.3.2 struct Global_DMA Data Structure.........................................................27

5.3 Critical Hardware Operations and Resulting Programming Requirements.........................295.3.1 Initialization of DMA Controller...............................................................................295.3.2 Appending to Chain and Setting Chain Resume ...................................................305.3.3 Actions Resulting from DMA Channel Interrupt from an

End of Chain of Channel Active .............................................................................305.3.4 Cacheline Flush and Drain ....................................................................................305.3.5 Prefetch .................................................................................................................305.3.6 Cacheline Locking .................................................................................................315.3.7 Critical Code or Variables Semaphores.................................................................315.3.8 DMA PCI Commands ............................................................................................315.3.9 Enabling MWI for Maximium PCI Bus Throughput ................................................315.3.10 Intel® 80310 Backplane .........................................................................................315.3.11 Debugging and setting Breakpoints .......................................................................31


Contents

5.4 APIs ....................................................................................................................................335.4.1 Library API Listing.................................................................................................. 33

5.4.1.1 Initialization ............................................................................................ 335.4.1.2 Request.................................................................................................. 335.4.1.3 Finish .....................................................................................................345.4.1.4 Exception Handling ................................................................................ 345.4.1.5 Library Termination ................................................................................ 345.4.1.6 Library Debug ........................................................................................ 35

5.4.2 Library API Operation Descriptions ....................................................................... 365.4.2.1 Initialization ............................................................................................ 365.4.2.2 Request.................................................................................................. 36

Request Function Call Hierarchy 375.4.2.3 Finish .....................................................................................................385.4.2.4 Exception Handling ................................................................................ 40

Standard Handler Code 40Vector Specific Handler Code 40

5.4.2.5 Library Termination ................................................................................ 415.5 Single Thread: Example .....................................................................................................425.6 Running Multiple Threads on Channel 0: Example ............................................................ 435.7 Hardware Interrupts ............................................................................................................46

5.7.1 Exception Modes ................................................................................................... 465.7.2 Interrupts: Non-Error Source ................................................................................. 465.7.3 Interrupts: Error Source .........................................................................................47

5.8 Error Handling..................................................................................................................... 48

6.0 Optimization Related...................................................................................................................49

6.1 Makefile Directives.............................................................................................................. 496.2 Intel® 80310 Backplane Issues Related to Optimization .................................................... 496.3 User #defines Affecting Performance................................................................................. 496.4 Fully Optimize Custom Solutions........................................................................................ 49

7.0 Preprocessor User Defines ........................................................................................................ 51

7.1 Overview............................................................................................................................. 517.1.1 User Defines .......................................................................................................... 517.1.2 Hardware Defines.................................................................................................. 51

8.0 Function Reference ..................................................................................................................... 53

8.1 Initialization......................................................................................................................... 538.2 Request .............................................................................................................................. 578.3 Finish .................................................................................................................................. 648.4 Exception Handling............................................................................................................. 718.5 Library Termination............................................................................................................. 77

9.0 Single Threaded Library Modification .......................................................................................79

10.0 Conclusion ................................................................................................................................... 81

A Getting Started............................................................................................................................. 83

A.1 Components ...............................................................................................................................83A.2 Hardware and Software Setup ................................................................................................... 83A.3 Running the Images ...................................................................................................................84

B Testbench..................................................................................................................................... 85


Contents

B.1 Overview.....................................................................................................................................85B.2 Benefits.......................................................................................................................................85B.3 Testbench Components..............................................................................................................85

B.3.1 Directory: RunFromHere................................................................................................85B.3.2 Directory: testbench.......................................................................................................86B.3.3 Directory: DMALib..........................................................................................................86

B.4 Defining Creating Experiments ...................................................................................................87B.5 Test Generation ..........................................................................................................................87B.6 Descriptor Generation.................................................................................................................87B.7 Performance Measurements: PMU ............................................................................................87B.8 Output Generation and Manipulation..........................................................................................87

C DMA Library Source Code ..........................................................................................................89

C.1 DMA Library makefile that Builds Objects to be Integrated into Application...............................89C.2 userDefsDMALib.h......................................................................................................................91C.3 80310_ThreadDMA.h .................................................................................................................95C.4 80310_ThreadDMA.c................................................................................................................100C.5 80310_Global.h ........................................................................................................................112C.6 80310_Global.c.........................................................................................................................115C.7 80312_DMA.h...........................................................................................................................122C.8 80310_fiq_irq.h .........................................................................................................................125C.9 80310_fiq_irq.c .........................................................................................................................129C.10 dmalibHeaders.h.......................................................................................................................135

D Testbench Source Code ...........................................................................................................137

D.1 makefile for Testbench .............................................................................................................137D.2 datatypesDMALib.h ..................................................................................................................140D.3 userDefsDMA_TestBench.h .....................................................................................................143D.4 80310_main.c ...........................................................................................................................147D.5 TestBench.h..............................................................................................................................149D.6 TestBench.c..............................................................................................................................152D.7 80310_PMUs.h .........................................................................................................................160D.8 80310_timer.h...........................................................................................................................163D.9 80310_timer.c ...........................................................................................................................169D.10 80310_ATU.h............................................................................................................................185D.11 80310_ATU.c............................................................................................................................188D.12 benchHeaders.h .......................................................................................................................191


Contents

Figures

1 DMA Controller ........................................................................................................................... 102 Code and Data Structures Overview .......................................................................................... 213 FrameDMA ................................................................................................................................. 244 struct Thread_DMA .................................................................................................................... 285 Appending a DMA Descriptor to a Channel Chain ..................................................................... 326 Finish .......................................................................................................................................... 397 Flow Diagram ............................................................................................................................. 418 Multi-Threaded Chaining Example for Channel 0....................................................................... 449 Multi-Threaded Chaining Example for Channel 0 - Alternate View ............................................45

Tables

1 Terms and Acronyms .................................................................................................................172 ARM Operating Modes Relevant to DMA Transfers................................................................... 463 FIQ1 Interrupt Sources ............................................................................................................... 464 IRQ Interrupt Sources.................................................................................................................475 Data Abort Interrupt .................................................................................................................... 476 Error Conditions and Approaches to Handling ...........................................................................48


Revision History

Revision History

Date Revision Description

December 2001 002 Revised cover title.

December 2001 001 Initial Release.


Revision History

This page intentionally left blank.

Intel® 80310 I/O Processor Chipset DMA Support LibraryIntel® Embedded I/O Processors DMA Library


1.0 Intel® Embedded I/O Processors DMA Library

Increasing I/O demands are central to Network and Storage high performance applications. Intel®

XScale™ microarchitecture (ARM* architecture compliant) addresses this trend with the Intel® 80310I/O processor chipset (80310). Features of the Intel® 80310 solution include three DMA channels.

The objectives of this document and the accompanying source code are to provide a fast ramp forDMA software Developers using the 80310. This objective is accomplished by providing a Intel®

80310 DMA Library software solution that is documented with source code and build tools. At thehardware level, the Library provides working example code performing DMA hardwareoperations. At a system level it presents a thoughtful Library implementation that abstracts the80310 DMA capabilities to a set of high-level APIs. For their unique applications, Developers candesign and build their own custom solutions using this template along with Intel-referencedOptimization Guides.

1.1 DMA Controller

The DMA Controller provides low-latency, high-throughput data transfer capability. The DMAController optimizes block transfers of data between the PCI bus and the Intel® 80200 processorbased on Intel® XScale™ microarchitecture (80200) local memory. The DMA is an initiator on thePCI bus with burst capabilities providing a maximum throughput of 528 Mbytes/sec when the PCIbus is operating in 64-bit/66 MHz mode.

The DMA Controller hardware is responsible for executing data transfers and for providing theprogramming interface. The DMA Controller features:

• Three Independent Channels.

• 256-byte queues in Ch-0 and Ch-1.

• 64-byte queue in Ch-2.

• Utilization of the Intel® 80312 I/O companion chip Memory Controller Interface.

• 232 addressing range on the Internal Bus interface.

• 264 addressing range on the primary and secondary PCI interfaces by using PCI Dual AddressCycle (DAC).

• Independent PCI interfaces to the primary and secondary PCI buses.

• Hardware support for unaligned data transfers for both the PCI bus and the Internal Bus.

• Up to 528 Mbytes/sec burst support for the PCI bus.

• Up to 800 Mbytes/sec burst support for the Intel® 80312 I/O companion chip (80312) internal bus.

• Direct addressing to and from the PCI bus.

• Fully programmable directly from the Intel® 80200 processor.

• Support for automatic data chaining for gathering and scattering of data blocks.

• 64-bit/66 MHz PCI.

• 64-bit/100 MHz Intel® 80312 I/O companion chip Internal Bus interface.



Figure 1 shows the connections of the DMA channels to the PCI busses.

Note: Channels 0 and 1 map to the primary PCI while channel 2 maps to the secondary PCI. Statedalternatively, all channel 0 and 1 transactions are directed to the primary PCI while channel 2transactions are directed to the secondary PCI.

1.2 Introduction to DMA Library

DMA Library provides a software infrastructure to manage DMA transfers between Primary PCIand Local memory and between Secondary PCI and Local memory on the Intel® IQ80310Evaluation Platform Board (IQ80310). The DMA Controller executes data transfers usingapplication programming interfaces (APIs).

The DMA Library supports PCI commands Memory Read Multiple and Memory Write andInvalidate. See Intel® 80312 I/O Companion Chip Developer’s Manual Table 9-13.

1.2.1 The DMA Library Provides Intel Customers

• The DMA Library implementation includes descriptor management and use of DMA Channels 0, 1and 2. This solution is provided to be used as a template for customer custom applications.

• Source code posted on web (See Related Documents, Section 2.0 for web link).

• Programmers Reference Manual (This manual) that includes:

— DMA Library Data Structures with design considerations

— Important algorithms

— Critical hardware operations and resulting programming requirements

— Compiler Optimizations

1.2.2 The DMA Testbench

In addition to the DMA Library, a software Testbench that supports IQ80310 DMA developmenteffort has been provided to accelerate Intel customers development efforts.

Figure 1. DMA Controller

Primary PCI Bus

Secondary PCI Bus

PCI-to-PCI Bridge

DMA Channel 0

DMA Channel 1

DMA Channel 2

Internal Bus



1.3 Highlights

1.3.1 DMA Library Architecture

In general, the DMA Library provides a solution that addresses architectures specificimplementation issues. More specifically:

• Critical hardware operations and resulting programming requirements identified.

• Efficient Frame management:

— Automated returning of executed Frames to the Free Stack with minimum performancepenalty. This is complex because multiple threads can share the communal DMAController.

— Frames are allocated during initialization so there is no performance penalty for dynamicmemory allocation during run time.

• Engineered data structures:

— Stacks used to manage Free Descriptors reduces cache misses. Additionally the intervalcan be set when finish is called to reclaim Frames to the Free Queue.

— Execution of operations on alternate DMA channels is performed with data structureindexing verses control structures. Avoiding control data structures reduces processorpipeline flushing.

— Data structures are aggregated for easy instantiation, referencing and memoryreclaimation.

— All data structures and their components are cache aligned

— User can define queue sizes of threads

— Preallocated Frames eliminate costly memory allocation during program execution

• Consolidated user defines in file userDefsDMALib.h. These consolidated user defines provideeasy to locate and change DMA Library tuning parameters.

• A single set of APIs that are channel and thread neutral.

• Example code for chipset hardware operations.

• Example exception handlers that can be implemented/attached in customized manner.

1.3.2 Testbench Features

• Automated DMA Transaction Generation: The bench generates a user defined set of DMAtransactions. Sets of transactions combine to comprise a experiment. Multiple experiments canbe defined and run in succession with PMU results saved for later output.

• Flexible PMU Output: (Performance Monitor Unit) The testbench PMU feature allows the flexibledefining and capturing performance data from the superset of the 80200 and 80312 PMUs.



1.4 Document Organization

This document contains four components:

1. DMA Library presentation.

2. DMA Library code.

3. Testbench overview.

4. Source code.

1.5 Recommendation on How to Use this Library

Recommendations on how to approach this body of work:

• Scan document to understand technical and documentation scope.

• When performing development, get code running and select implementions for you customapplication with cafeteria approach.

• Be sure to read:

— Highlights Section.

— Design considerations in each section.

— Hardware interfaces.

— Finish routine when using multi-threading.

— Further Enhancements section.

— Get understanding of design of testbench.

— Use Related Documents Section 2.0 for additional research.



1.6 Further Enhancements

This paper presents a thoughtful DMA implementation to assist developers. The method chosenwas that of a multi-threaded approach. The DMA of the 80200 provides a lot of flexibility to thedeveloper in developing solutions. In developing customize applications developer may makeimplement performance and/or feature enhancements. These enhancements may include:

1.6.1 Performance Related

Performance related enhancements include:

• Remove ChannelBusyDMA() function call used to synchronize garbage collection and wait for thechannel to become inactive only when transaction synchronization or error handling is required.

• Implement the full scope of Intel® XScale™ microarchitecture Optimization strategies (SeeIntel® XScale™ Microarchitecture Coding Techniques White Paper).

• Macros and inlining could be used more extensively to eliminate the overhead of function calls.

• Tune applications with the DMA Library user define parameters:

— QUEUE_FRAME_RECLAIM_INTERVAL.

— CHANNELSIZE.

• Tune applications by increasing the number of Frames prefetched.

• There may be a more efficient enhancement of circular queues.

1.6.2 Features Related

Feature enhancements could include:

• Allow a chain containing multiple descriptors to be appended and initiated. Currently eachFrame/Descriptor is appended and initiated individually.

• Adapt solution to single threaded approach.

• Add more extensive error handling.

• Execute retries for transfer failures.

• Support for Suspend / Resume Processes.

• Provide notification to Operating System of completion of transfers with status informationverses the current implementation of Marking the Frame.

Intel® 80310 I/O Processor Chipset DMA Support LibraryRelated Documents


2.0 Related Documents

• Intel® 80312 I/O Companion Chip Developer’s Manual (273410).

• Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Developer’s Manual(273411).

• Intel® IQ80310 Evaluation Platform Board Manual (273431).

• Intel® XScale™ Microarchitecture Coding Techniques White Paper (273578).

Many other App notes and tools:

• http://www.intel.com/design/iio/docs/iop310.htm.

• http://www.intel.com/design/iio/devtools/tptools.htm.

• http://www.intel.com/design/intelxscale/.

Get DMA Library and Testbench source files with makefiles to build from:

• http://www.intel.com/design/iio/docs/iop310.htm.

http://www.intel.com/design/iio/docs/iop310.htm

http://www.intel.com/design/iio/devtools/tptools.htm

http://www.intel.com/design/intelxscale/

http://www.intel.com/design/iio/docs/iop310.htm

Intel® 80310 I/O Processor Chipset DMA Support LibraryRelated Documents



Intel® 80310 I/O Processor Chipset DMA Support LibraryDefinition of Terms Used and Acronyms


3.0 Definition of Terms Used and Acronyms

Table 1. Terms and Acronyms

Term/Acronym Definition

Application A application or OS that uses the DMA Library.

.bss section A object files section which holds uninitialized data.

.data section A object file section which holds initialized writable data.

.text section A object files section which holds instructions and read-only data.

Chain

A set of DMA Descriptors chained together using the NDA (next descriptoraddress) fields. Note each channel maps to a single chain. When the command“resume” is executed by setting bit 1 in the Channel Control Register, alldescriptors in the chain are executed as a single transaction.

Channel The DMA Controller contains three channels, channel 0, channel 1 and channel 2.Each channel can have a single chain.

Channel Reference to three DMA Controller channels which include: DMA Channel 0(Primary PCI)DMA Channel 1 (Primary PCI)DMA Channel 2 (Secondary PCI).

DMA Descriptor DMA Chain Descriptor as defined in Figure 9-3 of the Intel® 80312 I/O CompanionChip Developer’s Manual.

Error Reporting Value posted to global variable liberror that represents error condition as defined inliberror.h file.

FIFO First in first out.

Frame The data structure that contains a DMA Chain Descriptor and Tracking informationas shown in Figure 2. The data structure is aligned on a eight word boundary.

LIFO Last in first out.

Mark To identify a Frame/Descriptor as processed. This is accomplished by settingframeDMA.status bit 15.

Private Data Structure/API Access is limited to the DMA Library application. This is in contrast to a PublicData Structure.

Process A single process is running on the system while multiple threads are running withinthe process.

Public Data Structure/API A public data structure is accessible by the application user. This is in contrast to aPrivate Data Structure.

Queue

Data structure container that uses FIFO (First in, first out). Each ThreadDMAcontains a single Queue for each Channel. The queue is used to manage framesthat have been removed from the Free Stack, are completed and added to thechannel chain.

Return Value Value returned from a function call.

Stack Data structure container that uses LIFO (Last in, first out). Each thread has asingle stack that manages the free frames.

Thread Refers to the ThreadDMA data structure declared for a thread. Note this is amulti-threaded application.

Intel® 80310 I/O Processor Chipset DMA Support LibraryDefinition of Terms Used and Acronyms



Intel® 80310 I/O Processor Chipset DMA Support LibraryBasic Assumptions


4.0 Basic Assumptions

4.1 Multi-Tasking Environment

It is assumed a multitasking environment exist that provides data access between threads. This isrequired to chain descriptor between threads.

4.2 Library Provides Memory Space for Descriptors

When a thread is created, the thread allocates all frames/descriptors during initialization. Theframes/descriptors are managed using pointers.

4.3 Uses Processor Modes IRQ, FIQ and Abort for Operationsand Error Handling

Exception handlers are installed to the interrupt vectors for handling DMA Controller interrupts.When the DMA Controller invokes a interrupt, the DMA Channel Status Register value is writtento the Frame causing the interrupt.

4.4 Frame Management

Each thread allocates and manages its own set of data structures that include Frame Pool, FreeStack and Post Queues or Channel 0, 1 and 2. Note for each channel, frames/descriptors arechained between threads using a global data structures.

4.5 Compiler

The compiler used for the code implementation is Redhat GNUPro.

4.6 Upper Bound on Number of DMA Threads Created

The number of DMA threads created concurrently should be upper bounded based on:

• The size of the struct Thread_DMA data structure verses RAM.

• Competition between threads for struct Global_DMA.

Intel® 80310 I/O Processor Chipset DMA Support LibraryBasic Assumptions



Intel® 80310 I/O Processor Chipset DMA Support LibraryDMA Library Architecture


5.0 DMA Library Architecture

5.1 Overview

The DMA Library is a multi-threaded implementation. Individual threads are run within a singleprocess and all data is available between threads. On a thread level, each thread has its own Framesand frame management. On a system level the DMA Library maintains the interface to thehardware and management of the DMA Channel Chains.

The purpose of Figure 2 is present a overview of the DMA Library data structures and code:

• Data Structures: The data structures specific to the Library are the Global_DMA andThread_DMA. There is a single declaration of the Global_DMA data structures per DMAController while there is one declaration of a Thread_DMA data structure per thread. Multiplethreads can be instantiated.

• Code: There is a single copy of the Operating System, User Application and DMA Library code.

Figure 2. Code and Data Structures Overview

Data Structures

Code

OperatingSystem DataStructures

GlobalDMAData Structure

N

0ThreadDMA

Data Structures 1

OperatingSystem Code

Library CodeApplication

Code

N-1



5.2 DMA Library Data Structures

Below are all the DMA Library data structure definitions. The below data structures aggregate intotwo composite data structures: Thread_DMA (Figure 3) and Global_DMA (Figure 4). Note all datastructures are private except for the Frame_DMA. FrameDMA is used by the application to build aDMA transaction and issue a request to the DMA Controller.

5.2.1 Public Data Structures: Declaration

struct Frame_DMA{

/* DMA Chain Descriptor */

void * nda; /* Next Descriptor Address */

void * pad; /* Source Address (Lower) */

void * puad; /* Source Address (Upper) */

void * lad; /* Destination Address */

int bc; /* Byte Count */

unsigned int dc; /* Descriptor Control */

/* Transaction Tracking Information */

short pid; /* process id */

short tid; /* transaction id */

short mark; /* set any bits mark */

short csr; /* channel status register */

};

5.2.2 Private Data Structures: Declarations

/* Thread_DMA component */

struct Queue_DMA{

int CircQ_Front;

int CircQ_Length;

int CircQ_Limit;

unsigned int * ccr_ptr;

unsigned int * csr_ptr;

struct FrameDMA * dar_ptr;

struct FrameDMA * pad1;

struct FrameDMA * pad2;

struct FrameDMA * CircQ[CHANNELSIZE];

};

/* Thread_DMA component */



struct Stack_DMA{

int Stack_Length;

int Stack_Limit;

int pad[6]; /* To stay on cacheline. */

struct FrameDMA * Stack[FRAMEPOOL];

};

/* Composite thread data structure */

struct Thread_DMA{

struct FrameDMA Frame[FRAMEPOOL];

struct StackDMA FreeStack; /* Unissued descriptors. */

struct QueueDMA Channel[DMA_CHANNELS];/* Issued descriptors */

void * toFreeMem;

};

----------------------------------------------------------------------------------

/* DMA Channel Chain variable */

struct Channel_DMA{

struct Frame_DMA *Head; /* Last Frame appended */

struct Frame_DMA *PriorHead;/* Next to last appended */

struct Frame_DMA *Tail; /* Oldest unmarked frame */

unsigned int *dar_ptr; /* Channel DAR */

void *pad1;

void *pad2;

void *pad3;

void *pad4;

};

/* Structure mapping three Channel_DMAs to DMA Controller Channels */

struct Global_DMA{

struct Channel_DMA Channel[DMA_CHANNELS];

};

/* Declaration of Global_DMA */

struct Global_DMA ChainsDMA __attribute__((aligned(32)));



Figure 3. FrameDMA

NDAR

DCR

Pid

BCR

LADR

PAD

PUADR

Tid

CSRStatus

Tracking

Chain Descriptor

Frame

32 Bits



5.2.3 DMA Library Data Structures: Descriptions

There are two composite data structures: Thread_DMA and Global_DMA. Thread_DMA isdeclared once for each thread while Global_DMA is declared once for each DMA Controller. TheDMA Library is multi-threading and data is available between threads within a process. However,the Library interface allows only access to the Public Data Structure Frame_DMA. This sectiondescribes each data structure.

5.2.3.1 struct Thread_DMA Data Structure

The Thread_DMA provides DMA Chain Descriptor management for a thread. For each thread, allDMA frames/descriptors are allocated in memory during initialization and managed with pointersusing the data structures Stack_DMA and Queue_DMA. Figure 4 provides a graphicalrepresentation of Thread_DMA.

• DMA Chain Descriptor (Public): A DMA Chain Descriptor consists of six contiguous wordsthat are 8-word aligned and used by the DMA Controller to perform a DMA transfer. SeeIntel® 80312 I/O Companion Chip Developer’s Manual Section 9.3.1 for further detail. EachDMA Chain Descriptor is build into a FrameDMA data structure.

• Frame_DMA (Public): See Figure 3. The FrameDMA structure contains a DMA ChainDescriptor and tracking information fields that include:

— PID: process id.

— TID: transaction id.

— mark: to identify requests that have been executed.

— csr: to record channel status registers (CSR) value or interrupts.

The application obtains a pointer to a frame and fills out both the DMA Chain Descriptor andthe tracking information. Each Thread_DMA contains its own allocation of Frame_DMA datastructures. The quantity allocated for each thread is determined by the #define CHANNELSIZEthat is defined by the user in file: userDefsDMALib.h.

• Stack_DMA (Private): Data structure is a stack (LIFO) maintaining pointers to unallocatedframes. Each Thread_DMA contains one stack for free Frames that is used by all three channels.

• Queue_DMA (Private): Data structure is a queue (FIFO) of pointers to Frames. There are threequeues in each thread, one per channel. Each queue maintains pointers to frames that havebeen moved from the Stack and filled out by the application. The Frame is then linked to thechannel chain and Chain Resume is set for the channel to initiate transfer. Each Queue_DMAis mapped to one of the three channels with the data structure arrayQueue_DMA.Channel[CHANNELS]. The variables for each channel: ccr_ptr, csr_prt anddar_ptr contain the addresses of the channel unique memory mapped registers.

• Channel[CHANNELS] (Private): The Channel[CHANNELS] is a array of three Queue_DMAdata structures. Each is mapped to a channel (channel 0 maps to Channel[0], channel 1 maps toChannel[1] and channel 2 maps to Channel[2]). With each queue being mapped to a channel,each channels specific registers and data structures can be accessed by passing in a integerindex with a Thread_DMA.



• Thread_DMA (Private): The Thread_DMA contains a set of preallocated contiguous Frames.The frames are managed by moving pointers between Stack_DMA and the three Queue_DMAqueues. The Thread_DMA is instantiated and initialized by the InitThreadDMA() function call.

— Instantiation: By instantiating the Thread_DMA data structure, all composite datastructures also instantiated. The size of the allocation varies based on the #definesCHANNELSIZE included in the userDefsDMALib.h file. These #defines determine thesize of the stack = (CHANNELSIZE * 3) and the size of each of the three queues of size =CHANNELSIZE.

— Initialization: Following the initialization, all frames (pointers) are loaded to theStack_DMA and each of the three Queue_DMAs are initialized as empty. Also the ccr_ptr,csr_prt and dar_ptr variables are loaded with the memory map registers locations.

• Data Structure Design Benefits:

— For a Thread_DMA, any of the three channel queues with all containing information canbe selected using a with a integer as a parameter since Channels are set up as an array.With the channel selection, channel unique memory mapped address locations are used toreference the channel specific memory mapped registers. This eliminates conditionalstatements to access channel specific registers and resulting pipeline flush.

— Free frames are in a stack data structure (LIFO) in order to maximize the probability thatFrames used still remain in cache memory. The #define variableQUEUE_FRAME_RECLAIM_INTERVAL can be set to determine how often Framesthat have been executed are reclaimed. The trade-offs are, the more often frames arereclaimed the more likely they remain in cache when requested while the offsetting cost isthat of calling the Finish routine to reclaim them.

— Using pointers allows out of order use of Frames within Thread_DMA and movement ofthe frame ownership from queues to the stack is accomplished by only writing a 32 bitvalue for the address.

— Aligning a Thread_DMA on a 32 byte boundary aligns all composite data structures aswell. The 32 byte alignment serves two benefits.

1.) For Queue_DMA and Stack_DMA, all control variables and register memory mappedregister locations are grouped and fall on a single contiguous cachelines of 32 bytes. Sothe none of the control variables for Queue_DMA and Stack_DMA data structuresstraddle cachelines.

2.) By aligning the Thread_DMA all contained DMA Chain Descriptors are 32 bytealigned as required by the DMA Controller.

• Returning Marked Frames To Free Stack. This algorithm follows the Mark algorithmperformed on Global_DMA data structures:

— Start: at Tail of Queue_DMA: Is Frame Marked?

— Yes: move Frame from Queue to Free Stack, move to next Frame and repeat. You can alsotest csr value to determine when errors occurred.

— No: Stop. All marked frames in a queue are contiguous. Therefore, once a unmarkedFrame is encountered, while moving from the tail toward the head, stop since noadditional Frames have been marked.



5.2.3.2 struct Global_DMA Data Structure

The Global_DMA data structure is used to maintain a single DMA Descriptor Chain for each of theDMA Controller’s three channels. The mapping of the data structures Thread_DMA toGlobal_DMA is many-to-one. For example when there are three Threads executing DMAtransactions on Channel 0, then the single declaration of the Global_DMA data structure would beused to append Frames from any of the three threads. Below is the composite data structure:

• Channel_DMA (Private): The purpose of the Channel_DMA is to manage a individual DMAChannel. Channel_DMA components:

— Head: Pointer to the last frame appended to the chain.

— PriorHead: Pointer to prior last frame appended to the chain.

— Tail: Pointer to the oldest unmarked frame in the chain.

— dar_ptr: Channel Descriptor Address Register. Address of the current address descriptor.

• DMA Descriptor Chain Management Algorithms:

— Appending a Frame: Appending a new Frame requires getting the address of the priorFrame appended to the channel chain, setting the Next Descriptor Address pointer of theprior Frame appended to the address of the new frame, flushing the cachelines of the newand prior Frame and setting CSR resume. Each operation is channel specific.

— Marking Executed Frames: Requires traversing the Chain from the tail to the currentchannel DAR value, marking each Frame in the Chain. Then setting the tail to the lastunmarked Frame following the last unmarked Frame.

• Global_DMA (Private): The purpose of Global_DMA {struct Channel_DMAChannel[DMA_CHANNELS];}; is to provide a array of Channel_DMA variables eachmapping to one of three DMA channels. Indexed variable Channel[0] maps to channel 0,Channel[1] maps to channel 1 and Channel[2] maps to channel 2. Note when the #defineCHANNEL_2is set to FALSE, only Channel 0 and 1 are used.

— Instantiation: Variable Global_DMA is declared as a cacheline aligned global static.

— Initialization: During GlobalDMA Init(), each Channel is initialized with the performance ofa zero size DMA transfer. When channel 2 is not used only channels 0 and 1 are initialized.Performing this initial transfer allows chaining and resume for successive transfers.Additionally the variables for each channel are set as follows: Tail = Head = PriorHead.



Figure 4. struct Thread_DMA

DMA Fram e

NULL Pointer

Frame Address

Frame Address

Frame Address

Frame Address

Frame Address

Frame Address

NULL Pointer

NULL Pointer

NULL Pointer

NULL Pointer

NULL Pointer

Frame Address

NULL Pointer

NULL Pointer

Frame Address

Frame Address

NULL Pointer

Free Stack

Channel 0Circular Post Queue

Post QueueChannel 1

Post QueueChannel 2

Frame Pool

DMA Fram e

DMA Fram e

DMA Fram e

DMA Fram e

DMA Fram e

DMA Fram e

DMA Fram e

DMA Fram e

Circular Post Queue

Circular Post Queue

Circular Queues

struct ThreadDMA

� Stack_Length� Stack_Limit� Stack[]

� CircQ_Front� CircQ_Length� CircQ_Limit� CircQ[]� ccr_ptr� csr_ptr� dar_prt

� See Ch0

� See Ch0

Status Variables

Status Variables

Status Variables

Status Variables



5.3 Critical Hardware Operations and Resulting ProgrammingRequirements

5.3.1 Initialization of DMA Controller

The DMA controller initialization: ATU Related allowing Memory Write and Invalidate. When anyof the conditions are not met, the channel converts the MWI command to a Memory Writecommand for the complete DMA transfer. (See Intel® 80312 I/O Companion Chip Developer’sManual, section 9.5.3) See code below.

Note: When transferring between cards, both source and destination need to be initialized.

• The ATUCLSR value must be any valid value other than 0.

• The ATUCLSR must have a legal value that is less than or equal tot he number of queueentries in the DMA Channel queue.

• The Memory Write and Invalidate Enable bit in the Primary or Secondary ATU CommandRegister must be set.

/* Setting ATU for MWI */

#define ATUCLSR (volatile unsigned int *) 0x120c

#define PATUCMD (volatile unsigned int *) 0x1204

#define SATUCMD (volatile unsigned int *) 0x1298

#define ATU_CACHELINE_SIZE_16DWORDS 0x10

#define MEMORY_WRITE_AND_INVALIDATE_ENABLE 0x10

*ATUCLSR|= ATU_CACHELINE_SIZE_16DWORDS;

*PATUCMD|= MEMORY_WRITE_AND_INVALIDATE_ENABLE;

*SATUCMD|= MEMORY_WRITE_AND_INVALIDATE_ENABLE;



5.3.2 Appending to Chain and Setting Chain Resume

In order to perform a DMA transfer, the DMA Chain Descriptor is appended to the channel chain andthe Chain Resume bit is set in the Channel Status Register. Figure 5 provides a Flowchart of thisprocess as presented in Intel® 80312 I/O Companion Chip Developer’s Manual, Section 9.3.5. Thepurpose of the flowchart is to ensure all cases are accounted for and covered in the DMA Library.

After the initialization of the DMA Controller to enable Chaining, there are three states a channelcan be in when a Descriptor is appended (excluding the occurrence of a error):

1. The Channel is idle.

2. The Channel is in the middle of processing a existing chain.

3. The Channel is processing the last item in a existing chain.

All cases are covered by setting the Chain Resume bit for each descriptor that is appended.

The only other case to consider when there is an error. This needs to be tested. When a erroroccurs the objective is to record the CSR value to the Frame and continue:

• Error occurs during DMA transaction.

• Error, triggers a interrupt.

• The Channel Status Register value is recorded to Frame.

• The interrupt is cleared at the source by writing 1s to CSR.

• The DMA Controller continues with the next descriptor in the Channel Chain.

5.3.3 Actions Resulting from DMA Channel Interrupt from an End of Chainof Channel Active

The DMA End of Chain Interrupt results from Bit 04:Interrupt Enable being set in the descriptorbeing executed. A interrupt handler is installed to record the CSR value to the Frame executing andthen cleaning the interrupt. The interrupt is cleared by writing 1s to the CSR. This is referred to asclearing the interrupt at the source.

5.3.4 Cacheline Flush and Drain

The DMA Controller executes transactions based on values written to RAM. This processor doesnot enforce cache / RAM memory coherency. Therefore after descriptors are written to cache theymust be flushed to memory before the transaction takes place. With chaining, two cachelines arerequired to be flushed:

• The prior descriptor in the chain since Frame NDA is used to link the descriptor appended.

• The appended descriptor.

5.3.5 Prefetch

Prefetch is used to preload cachelines.This application implements prefetch for the next Frame tobe requested on the stack for the Thread. The implementation could be improved to allow avariable number of Frames to prefetched. This would enable a additional tuning parameter.



5.3.6 Cacheline Locking

This is not implemented. Potential implementation include locking descriptors, threads, globalstatus variables or critical code.

5.3.7 Critical Code or Variables Semaphores

This is OS specific and not implemented. The only variable subject to a race condition is structGlobal_DMA. Therefore with multi-threading, semaphores are required to manage access to thisvariable. The function accessing this variable are LinkDescriptorDMA(). Note that each structThreadDMA is accessed by a single execution thread so no race conditions can occur within a thread.

5.3.8 DMA PCI Commands

Defined in the DMA Chain Descriptor field, Descriptor Control Register. See Intel® 80312 I/OCompanion Chip Developer’s Manual, Table 9-13. Note to generate the correct PCI commands onthe bus, you need to avoid interference with the Messaging Unit which is 4K from BAR (baseaddress register). You also need to avoid overwriting the OS and program. Either of these can leadto unpredictable results.

For the DMA Library the DMA PCI commands are:

• Memory Read Multiple:[1100b] Memory Read of more than one cacheline.

• Memory Write and Invalidate:[1111b] Memory Write which guarantees the transfer ofcomplete cache line (s) during the current transaction.

5.3.9 Enabling MWI for Maximium PCI Bus Throughput

When the ATU is not set up in compliance with section 9.5.3 in Intel® 80312 I/O Companion ChipDeveloper’s Manual, memory write and invalidate performs as memory write. Sequential memorywrites are are much more costly in terms of PCI bus transfer time than sequential memory writeand invalidates. Note that the PCI command is defined in each DMA descriptor. Also arbitration onthe PCI bus can also affect performance.

5.3.10 Intel® 80310 Backplane

The CPLD may need to be upgraded to improve performance across PCI bus.

5.3.11 Debugging and setting Breakpoints

When setting breakpoints in code and examining DMA related execution states, be aware thatDMA execution is stalled as well. Also problem may be encountered in entering and exitingexception modes.



Figure 5. Appending a DMA Descriptor to a Channel Chain

Entered after DMAController

Initialization

Append Descriptorand set ChainResume bit in

CCR

Channel Idlebefore

Transaction?

Prior ExecutingDescriptorCompleted

Last in priorchain?

Clear ChainResume and

continue to finishoriginal Chain

Load and executeappendeddescriptor

Examine ChainResume bit which

is now clear

Set channel to idle

Writting to CCR causesexamination of Chain

Resume bit1. Set, re-read Last

Descriptor2. NDAR != 0x0 due to

Descriptor appended

Chain Resume bit examined-Set, re-read last descriptor

and clear bit-NDAR != 0x0 due toDescriptor appended

Yes

No

Yes

No



5.4 APIs

Following are DMA Library APIs by categories: Initialization, Request, Finish, ExceptionHandling and Library Termination. A full description of the functions is included in Section 7.0,“Preprocessor User Defines” on page 51.

5.4.1 Library API Listing

5.4.1.1 Initialization

Public:

int ThreadSizeDMA(void)

struct Thread_DMA* InitThreadDMA(void *thread1)

Bool GlobalDMAInit(void)

Private:

void FlushDrainFullCacheDMA(void)

None

5.4.1.2 Request

Public:

struct Frame_DMA * MoveDescriptorToPostDMA(int channel, struct Thread_DMA*thread1)

bool ExecuteDMA(int channel, struct Frame_DMA *frame, structThread_DMA *thread1)

Private:

struct Frame_DMA * PopFreeStackDMA(struct Thread_DMA *thread1)

struct Frame_DMA * PutPostQueueDMA(int channel, struct Frame_DMA *frame, structThread_DMA *thread1)

void LinkDescriptorDMA(int channel, struct Frame_DMA *frame)

void FlushDrainDMA(struct Frame_DMA *frame1,struct Frame_DMA*frame2)

Bool ChannelBusy(int channel, struct Thread_DMA* thread1);



5.4.1.3 Finish

Public:

Bool FinishQueueDMA(int channel, struct Thread_DMA *thread1)

Private:

int MarkChanneDMA(int channel)

int QueueCleanMarkedDMA(int channel, struct Thread_DMA *thread1)

Bool MoveDescriptorToFreeDMA(int channel, struct Thread_DMA*thread1)

struct Frame_DMA* GetPostQueueDMA(int channel, struct Thread_DMA *thread1)

Bool PushFreeStackDMA(int channel, struct Frame_DMA *frame,struct Thread_DMA *thread1)

struct Frame_DMA *PntrLastInQueueDMA(int channel, struct Thread_DMA *thread1)

5.4.1.4 Exception Handling

Public:

None

Private:

void intHandlerAttachDMA(void (*irq)(void),void (*fiq)(void),void(*abrt)(void));

void intHandlerDetachDMA(void);

void irqHandlerDMA(void)__attribute__ ((__naked__));

void fiqHandlerDMA(void)__attribute__ ((__naked__));

void abrtHandlerDMA(void)__attribute__ ((interrupt ("ABORT")));

void intHandlerABRTDMA(void);

void (*irq)(void);/* Pointer to a function. */

void (*fiq)(void);/* Pointer to a function. */

void (*abrt)(void);/* Pointer to a function. */

5.4.1.5 Library Termination

Public:

Bool TerminateGlobalDMA(void)

struct Thread_DMA * TerminateThreadDMA(struct Thread_DMA * thread1)

Private:

None



5.4.1.6 Library Debug

Public:

void printChannelChain(int channel)

void * TestMemoryAlloc(void)

int ChannelBusy(int channel, struct Thread_DMA *thread1)

Private:

None



5.4.2 Library API Operation Descriptions

The purpose of this section is to present a general description of how the functions work in concert.See Figure 7, “Flow Diagram” on page 41 and Section 8.0, “Function Reference” on page 53 foradditional function information.

5.4.2.1 Initialization

• InitGlobalDMA(): Initializes Global_DMA variables to enable chaining and sets ATU bits toenable MWI (memory write invalidate). Required before thread initialization.

• InitThreadDMA(): Allocate Thread_DMA data structure, initialize free stack and channel queues.

5.4.2.2 Request

In order to perform a DMA request on Channel 0:

• Move Descriptor from free to post queue.

— MoveDescriptorToPostDMA(): removes a Frame from struct Stack_DMA by callingPopFreeStackDMA() and posts Frame to struct Queue_DMA by callingPutPostQueueDMA(). A pointer to the Frame is returned. When a NULL pointer returnedthen FinishQueueDMA() is called.

• Using pointer to the Frame, the application fills out the frame fields:

— DMA Chain descriptor fields pad, puad, lad, bc and dc.

— Tracking fields pid and tid.

• Execute a DMA descriptor: ExecuteDMA(). The operations performed include linking thedescriptor to the Channel Chain, flushing the prior and new descriptor from Cache and settingthe Chain Resume bit in the Channel Control Register.

— Link Descriptor/Frame to the channel chain and flush cachelines and drain fill/write buffers.

o LinkDescriptorDMA(): appends the Frame to the channel chain. The frame address ofGlobalDMA[0].Head is transferred to GlobalDMA[0].PriorHead. The address of the newframe is written to GlobalDMA[0].Head. Then set GlobalDMA[0].PriorHead.nda =GlobalDMA[0].PriorHead to append Descriptor to the chain.

o FlushDrainDMA() Then flushes current and prior descriptor cache lines to RAMmemory and drains write (&fill) buffers.

— Set DMA Channel Resume Enables bits with macroRESUME_ENABLE(channel,thread1).

— Preload next descriptor in threads free stack with macro PRELOADFRAME(thread1).



5.4.2.2.1 Request Function Call Hierarchy

• MoveDescriptorToPostDMA() calls:

— PopFreeStack().

— PutPostQueue().

When MoveDescriptorToPostDMA() fails then FinishQueueDMA() is called to move Framesof processed descriptors from Post Queue to the Free Stack.

• ExecuteDMA() calls:

— LinkDescriptorDMA();

— RESUME_ENABLE(channel,thread1);

— PRELOADFRAME(thread1);



5.4.2.3 Finish

FinishQueueDMA() is the frame reclamation algorithm implemented for multi-threadedimplementation. The algorithm goal is to allow any threads to call the function FinishQueueDMA()to reclaim Frames on the communal Channels Descriptor Chain without any Descriptor beinghandled more than two times. This is accomplished, the routine visits each Frame only two times.Once to mark the Frame as executed and once to return marked Frame to Free Stack.

Finish call interval is defined by the user with #define QUEUE_FRAME_RECLAIM_INTERVALin file userDefsDMALib.h and can be used for tuning application. Also, the number of Free Framesdeclared in a Thread_DMA is enough to fill all three queues. Therefore, the condition of having afull Queue is the only condition requiring the reclaiming of Frames. The number of Frames in eachof three queues is a #define CHANNELSIZE in the same file, userDefsDMALib.h.

To understand Finish:

• Finish Algorithm: See Figure 6.

• In summary this finish performs the following: Call FinishQueue() to free Frames ofprocessed descriptors when MoveDescriptorToPostDMA() fails by returning a NULL pointer.



Figure 6. Finish

Call FinishQueueDMA()

Last Frame inQueue Marked?

num = MarkChanneDMA()

num > 0

num =QueueCleanMarked()

ReturnMoveDescriptorToPostDMA()

Return NULL

Yes

num > 0

Yes

No

No

Yes

No



5.4.2.4 Exception Handling

When the state of the DMA Controller causes a exception, the processor changes mode to IRQ,FIQ or ABRT and jumps to the specific vector. The function handlers are chained to the exceptionvectors with intHandlerAttach(). The handlers are functions irqHandler(), fiqHandler() andabrtHandler(). Each of the three handlers are comprised of standard and vector specific code.These handlers and handler installation routine are templates that should be customized and testedfor user applications being developed:

5.4.2.4.1 Standard Handler Code

1. Test status bits to determine when interrupt is DMA related. The following is performed when DMAis related:

2. Using DAR, write CSR to DMA Frame being executed.

3. Clear the interrupt at the source by writing 0xffffffff to channel 0, 1 or 2 DMA Controller Unit CSR.

5.4.2.4.2 Vector Specific Handler Code

• irqHandler(): When called tests bits 00, 01 and 02 of the FIQ1 Interrupt StatusRegister-FIQ1ISR 0x0000 1708. Performed standard handler code. Handler is chained.

• fiqHandler(): When called tests bits 00, 01 and 02 of the IRQ Interrupt StatusRegister-IRQISR 0x0000 1700. Performed standard handler code. Handler is chained.

• abrtHandler(): When called tests bits 00, 01 and 02 of the IRQ Interrupt StatusRegister-IRQISR 0x0000 1700. Performed standard handler code. Handler is not chained.



5.4.2.5 Library Termination

• Thread Termination Function: TerminateThreadDMA().

Used to terminate a Thread. The Library stays intact. User must determine thread is in statethat contains no uncompleted transactions by first calling ThreadCompleteDMA().

— Frees malloced Thread_DMA memory.

• Library Termination Function: TerminateGlobalDMA().

Terminate the library. User must ensure there are no existing threads.

— Frees malloced Thread_DMA memory.

— Detaches exception handlers..

Figure 7. Flow Diagram

CacheIRQ/FIQ/Abort DMA Controller

Hardware

GlobalThreadSystemApplication

Init

Request

Finish

Terminate

Loop = traverse chain

InitGlobalDMA()

InitThreadDMA()

MoveDescriptorToPostDMA()

Return Pointer

Fill out descriptor

ExecuteDMA()

Interrupt triggeredirqHandler()fiqHandler()

abrtHandler()

FinsihQueueDMA()

TerminateThreadDMA()

TerminateGlobalDMA()



5.5 Single Thread: Example

To initiate library, call GlobalDMAInit(). This function attaches interrupt handlers, initiates globalvariables, sets the DMA Controller to enable chaining and the ATU for PCI command MWI. Atthis point InitThreadDMA() can be called to allocate memory and initialize the Thread_DMA datastructures. A view of a single thread is represented with Figure 8 and Figure 9.

In order to initiate a transfer, obtain a Frame from Thread’s Free Stack and moving it to the ThreadsChannel’s Post queue. This is accomplished by calling MoveDescriptorTo PostDMA() whichreturns a pointer to a Frame. Using the pointer to the Frame, the application completes the Framedata structure. To initiate the transfer, the application calls ExecuteDMA() which appends theFrame to the channel chain, initiates the transfer by setting the Chain Resume bit in the ChannelStatus Register causing the DMA descriptor to be executed and preload the next Frame in theThread stack. When, during a DMA transfer, a error occurs or the Interrupt Enable bit is set in theDescriptor, the DMA Controller causes a interrupt/change of processor mode and jumps to IRQ,FIQ or ABORT vector. For each of the vectors, a interrupt routine has been chained, so the installedhandler, irqHandlerDMA(), fiqHandlerDMA() or abrtHandlerDMA() is jumped to and executed.When the interrupt is DMA related the CSR value is written to the Frame and the interrupt iscleared. So the record of the error condition is recorded to the Frame being executed.

When moveDescriptorToPostQueueDMA() is called, and the function returns NULL pointer, thenFinishDMA() is called to reclaim Frames. Then function MoveDescriptorToPostQueueDMA() isthen called again and a pointer to the Frame returned.

To terminate a thread and return the deallocated memory to the system, TerminateThreadDMA() iscalled. To terminate the entire DMA Library and detach the interrupt handlers,TerminateGlobalDMA() is called.



5.6 Running Multiple Threads on Channel 0: Example

• Same as running single thread in regard to:

— There is still a single descriptor chain for each channel. With multiple threads, the chain fora single channel can link Frame_DMA/DMA Chain Descriptors across multiple threads.

— All function calls remain the same. The input parameters change to reflect the individualThreads.

• See Figure 8 and Figure 9 for presentation of the same multi-threaded chaining example forChannel 0:

— Thread 0, 1 and 2: Three threads have been declared, each is declared as a structThread_DMA as represented in Figure 4. Note the Channel Chain to spans multiplethreads as is allowed with threads within a process.

— Chain: Figure 9 presents an alternate view of the Channel 0 chain. Figure 9 has the ChainFrames mapped to their execution sequence. Figure 8 provides the Chain presented ascontained in their data structures. The chain state is maintained by Global_DMA variable.The chain is created by linking each appended Frame using the prior Frames nextdescriptor address to create a singly linked list. The chain shown in Figure 8 and Figure 9links Frames sequentially: #1->2->3->4->5. The chain Tail is identified by #1 and Head#5. Each item in the chain has been moved from the Threads Free Stack to the ChannelPost Queue (Channel[0]). Other Frames, not in the Chain reside in the Free Stack. Whenfunction ExecuteDMA() calls macro RESUME_ENABLE() is called for Channel 0, theexecution of the DMA Chain Descriptors follows the direction of the nda pointers fromTail to the Head.

— Global Variables: The Global_DMA contains chain status variables for Channel 0. TheGlobal_DMA mapping to Thread_DMAs is one to many. The global variables and chain arethe same for single or multi-threaded. The only difference is the chain spans multiple threads.



Figure 8. Multi-Threaded Chaining Example for Channel 0

1

5

2

4

3

Head

PriorHead

Tail

dar_ptr

Cacheline Pad

Cacheline Pad

Cacheline Pad

Cacheline Pad

ndar

ndar

ndar

ndar

ndar

Free

PostQ

Free

PostQ

Free

PostQ

Frames

Frames

Frames

Thread 1 - Channel 0



Global Variables - Channel 0

GlobalDMA



Figure 9. Multi-Threaded Chaining Example for Channel 0 - Alternate View

1

5

2

4

3

Head

PriorHead

Tail

dar_ptr

Cacheline Pad

Cacheline Pad

Cacheline Pad

Cacheline Pad

ndar

ndar

ndar

ndar

ndar

Free

PostQ

Free

PostQ

Free

PostQ

Frames

Frames

Frames




Global Variables - Channel 0

GlobalDMA

1

5

4

3

2

ndar

ndar

ndar

ndar

ndar



5.7 Hardware Interrupts

The purpose of this section is to present the DMA related Exception Modes including the ChannelStatus Register bits that are set by the hardware and must be cleared by the interrupt handler. AllDMA Controller hardware interrupts are cleared by clearing the interrupt at the source. In this caseclearing the CSR (Channel Status Register) by writing 1s to register bits to be cleared. Allinformation presented is provided from the Intel® 80312 I/O Companion Chip Developer’s Manual.

5.7.1 Exception Modes

Table 2 shows the three exception modes that can be invoked by the DMA Controller. For the threemodes IRQ, FIQ and Abort, the vector address and CPSR is also shown. All interrupts are handledin the DMA Library by writing the CSR value to the Frame, clearing the interrupt and loading thenext instruction. See Intel® 80312 I/O Companion Chip Developer’s Manual, Table 9-5 forChannel Status Register and description and Table 9-12 for Descriptor Control Register Values.

5.7.2 Interrupts: Non-Error Source

FIQ1 Interrupt Sources (0x0000001C)These interrupts are invoked for a DMA Chain Descriptor bysetting bit 04 Interrupt Enable in the Descriptor ControlRegister (DCR). See Table 3.

Table 2. ARM Operating Modes Relevant to DMA Transfers

Exception Mode Vector Address CPSR[4:0]

IRQ (Normal Interrupt) IRQ 0x00000018 10010

FIQ (Fast Interrupt) FIQ 0x0000001C 10001

Data Abort (data access memory fault) Abort 0x00000010 100111

Table 3. FIQ1 Interrupt Sources

Unit Interrupt Condition Register

DMA Channel 0,1 & 2 End of Chain DMA Channel Status Register, Bit 08

DMA Channel 0,1 & 2 End of Transfer DMA Channel Status Register, Bit 09



5.7.3 Interrupts: Error Source

IRQ Interrupt Sources (0x00000018)These are caused by hardware related errors. See Table 4.

Data abort Interrupt (0x00000010) This interrupt is created by putting values in the DMA ChainDescriptor that are unsupported state by the DMA Controller.For example when a Unsupported PCI Command is entered inDescriptor Control Register. See Table 5.

Table 4. IRQ Interrupt Sources

Unit Register Error Condition

DMA Channel 0,1 & 2 DMA Channel Status Register: Bit 00 PCI Master Parity Error

DMA Channel Status Register: Bit 02 PCI Target Abort (Master)

DMA Channel Status Register: Bit 03 PCI Master Abort

DMA Channel Status Register: Bit 05 IB Master Abort

Table 5. Data Abort Interrupt

Unit Register Error Condition

DMA Channel 0,1 & 2 DMA Channel Status Register: Bit03 PCI Master Abort



5.8 Error Handling

Below is a listing of potential DMA Library errors and methods to handle the errors.

Table 6. Error Conditions and Approaches to Handling

Error Description Handling Approaches

Hardware/Interrupt Invoked:

- InternalBus Master Abort.

- PCI Master Abort.

- PCI Target Abort.

- Parity Error.

-Prevention beyond scope of DMA Library, Library writes CSR value toexecuting Frame and continue with next Frame.

User Input: Descriptor Values:

- Invalid PCI Command(DCR).

- Exceed Transfer Size.

- Bad Pointer NDA.

- Bad PAD/PUAD.

- Bad LAD.

-Software Test: User required to prevent.


-Software Test: DMA Library prevents.



Queue States:

- Channel Queue Full with nointerrupts after calling mark.

-FinsihQueueDMA() handles by using DAR to determine last Frameprocessed by the DMA engine.

Recoverable/Non-recoverable:

-Recoverable - can retry.

-Non-Recoverable - retry futile.

-No retry is implemented, write CSR value to Frame and continues

-Write CSR to Frame and continue.

Thread Termination:

- With incomplete transactions inqueues. -terminate waits until channel is inactive before terminating thread.

Intel® 80310 I/O Processor Chipset DMA Support LibraryOptimization Related


6.0 Optimization Related

6.1 Makefile Directives

Compiler directives related to optimization:

• Set optimization level to -O1,-O2 and -O3. Note inlining is a optimization and work only whenone of these optimization is used.

• Also try -funroll-loops and -foptimize-comparisons.

Profile code (use PMUs) using different ones to see which runs faster for particular application.

6.2 Intel® 80310 Backplane Issues Related to Optimization

Be aware when using the IQ80310 Backplane to optimize code, the BUS Arbiter is very slow whenthe CPLD needs to be upgraded.

6.3 User #defines Affecting Performance

• CHANNELSIZE: the user can specify the channel size declared by each thread.

• QUEUE_FRAME_RECLAIM_INTERVAL: The user can specify the interval set in whichFinishDMA is called. Each entry to MoveDescriptorToPostDMA() the interval is checked bymacro FINISHTEST().

• CHANNEL_2: when you try to use channel 2 and do not set CHANNEL_2 to TRUE thetransfer fails.

6.4 Fully Optimize Custom Solutions

To fully optimize custom solution, reference extensive documentation listed in Section 2.0,“Related Documents” on page 15. To being, start with the Intel® XScale™ MicroarchitectureCoding Techniques White Paper.

Intel® 80310 I/O Processor Chipset DMA Support LibraryOptimization Related



Intel® 80310 I/O Processor Chipset DMA Support LibraryPreprocessor User Defines


7.0 Preprocessor User Defines

The DMA Library has consolidated all user defines into one file to provide easy location,understanding and modification.

7.1 Overview

The DMA Library has consolidated all user defines into one file userDefsDMALib.h, to provideeasy location, understanding and modification. Note the User Defines are #defines and handled bypreprocessor during compilation.

7.1.1 User Defines

CHANNELSIZE: (integer) The size of the channel queues. This number should be a power of 2.One queue of this size is allocated for each Channel (0, 1 and 2). The Free Stackequals (CHANNELSIZE * 3).

CHANNEL_2: (TRUE or FALSE) Enter TRUE when Channel 2 (secondary bus) is being usedand FALSE when it is not.

Below represents dummy descriptor values used only during initialization to place each of the threechannels in state that enables chaining and resume. The only requirement is the DMA enginerecognize the addresses. Note BC is typically set at 0x0 for a zero transfer.

NDA: Next Descriptor Address.

PAD: PCI Address [31:0].

PUAD: PCI Upper Address [63:32].

LAD: 80200 Processor Local Address.

BC: Byte Count.

DC: Descriptor Control.

7.1.2 Hardware Defines

CHANNELS: The number of DMA Channels contained in the DMA Controller = 0x3.

Intel® 80310 I/O Processor Chipset DMA Support LibraryPreprocessor User Defines



Intel® 80310 I/O Processor Chipset DMA Support LibraryFunction Reference


8.0 Function Reference

8.1 Initialization

ThreadSizeDMA: Public

int ThreadSizeDMA(void)

The purpose of this function is to provide a user who wants to allocate his own memory for a thread,the size of the memory in bytes he is required to allocate. The size calculated includes the additionalspace for alignment to a 32 byte boundary (0x20 bytes). This is how the size is calculated:

return (sizeof(struct Thread_DMA) + 0x20)

The size of the queues and stacks in a thread are defined as shown in the userDefsDMALib.h file asshown below:

#define CHANNELSIZE defined by user

This definition would create channels 0, 1 and 2 each including 0x30 Frames. The FreeStack wouldcontain (0xTBD * 3) Frames.

Overview

Option

Called by Application

Calls to None

Parameters

Parameter Description

None Uses #define CHANNELSIZE in file: userDefDMALib.h.

Return Value

Status Description

NULL Failure: Call to sizeof() failed.

Integer Value > 0 Successful: The size of memory in bytes required for a ThreadDMAstructure.

Error Reporting

Status Description

SIZEOF_CALL_FAILED Call to sizeof failed.



InitThreadDMA: Public

)struct Thread_DMA* InitThreadDMA(void * thread)

The purpose of InitThreadDMA is:

• Align and cast the input parameter from void * to struct ThreadDMA *thread.

• Initialize the data structure.

• When a NULL pointer is passed in as a input parameter, then the struct Thread_DMA memoryis allocated by this function.

• Save the pointer to the memory in order to enable free() to be called when the thread is terminated.

The state of the Thread_DMA after initialization:

• FreeStack, FULL with pointers to free descriptors.

• Queues for Channel 0, 1 & 2 set as EMPTY.

• Memory mapped address locations saved to Queue_DMA for each channel: CCR, CSR and DAR.

• All Frames/Descriptors aligned to 32 byte boundaries.

• All control variables fill single cacheline (no cacheline boundaries straddled).

• ATU set to enable MWI.

Overview

Option Description

Called by Application using DMA Library.

Call to Calls malloc() when input parameter = NULL.

Parameters


thread

This is a pointer to a unaligned memory location allocated for aThreadDMA data structure by the User of the size returned fromfunction ThreadSize. When NULL is passed as a parameter thenmemory is allocated by this function. Otherwise, this function takespointer and initializes memory.

Return Value

Status Description

NULL Failure: Call to malloc() failed. Initialization unsuccessful.

!= NULL Successful: Pointer to aligned and initialized Thread_DMA datastructure returned.

Error Reporting

Status Description

INIT_THREAD_MALLOC_FAILED Malloc failed, data structure not allocated or initialized.



GlobalDMAInit: Public

Bool GlobalDMAInit(void)

Function GlobalDMAInit() initializes thread independent aspects of the DMA Library:

• Attaches chained interrupt handlers for IRQ, FIQ and ABORT exceptions.

• Initializes each Channel for Chaining by performing a DMA of size 0 for each channel.

Overview

Option Description

Called by Called once by Operating System or Monitor.

Parameters


None

Return Value

Status Description

TRUE Channels in state to use Chaining.

FALSE At least one channel failed initialization.

Error Reporting

Status Description

CHANNEL_INIT_FAILED_ONE_CHANNEL During Global initialization, (1) of three channels failed insetup.

CHANNEL_INIT_FAILED_TWO_CHANNEL During Global initialization, (2) of three channels failed insetup.

CHANNEL_INIT_FAILED_THREE_CHANNEL During Global initialization, (3) of three channels failed insetup.



FlushDrainFullCacheDMA: Private

void FlushDrainFullCacheDMA(void)

Function flushes the full cache and drains the write and fill buffers.

Overview

Option Description

Called by GlobalDMAInit

Parameters


None

Return Value

Status Description

None

Error Reporting

Status Description

None



8.2 Request

MoveDescriptorToPostDMA: Public

struct Frame_DMA * MoveDescriptorToPostDMA(int channel, struct Thread_DMA*thread1)

The purpose of this function is to get a Frame from the channel Queue_DMA in Thread_DMA.MoveDescriptorToPostDMA() moves a Frame from the free stack to the post queue. This functionis called by the application using the DMA Library. When the parameterQUEUE_FRAME_RECLAIM_INTERVAL has been reached or when the Queue is full,FinishDMA() is called. When the operation fails a NULL pointer is returned. When successful, apointer to the descriptor obtained is returned. Using the pointer the application can then completethe descriptor.

Overview

Option

Called by Application using DMA Library.

Calls to FinishDMA(), PopFreeStackDMA, PutPostQueueDMA,PushFreeStackDMA.

Paramters


channel Integer 0, 1, 2 representing DMA channel 0, 1 or 2.

thread Pointer to the Thread_DMA the operation is to be performed on.

Return Value

Status Description

NULL Request to move descriptor from Free to Post queue failed.

Pointer to Frame When frame is successfully moved from Free stack to the Postqueue, pointer to the frame is returned.

Error Reporting

Status Description

POSTQ_FULL_RETURN_TO_FREE Post Queue full and would not accept Frame. Frame returned to freestack.

POSTQ_FULL_FREEQ_PUSH_FAILED Post Queue full and would not accept frame, followup push to FreeStack failed. Pointer to frame failed.

NO_FREE_DESCRIPTORS popFreeStackDMA failed. Attempt to obtain Free descriptor failed.



ExecuteDMA: Public

bool ExecuteDMA(int channel, struct Frame_DMA *frame, structThread_DMA *thread)

The purpose of this function is to execute a DMA transaction for a completed Frame. The functionExecuteDMA() links the descriptor to the channel’s chain, flushes the cachelines for the descriptor, sets“resume” in the CSR to initiate the transaction and preloads the next Frame in the Free stack to cache.

Overview

Option

Called by Application.

Calls to LinkDescriptor, RESUME_ENABLE and PRELOADFRAME.

Parameters



frame Pointer to frame to be executed.

thread Pointer to Thread_DMA.

Return Value

Status Description

TRUE Function call did not hang.

Otherwise Function call did not return.

Error Reporting

Status Description

None



PopFreeStackDMA: Private

struct Frame_DMA * PopFreeStackDMA(struct Thread_DMA *thread)

Function PopFreeStackDMA removes a single frame from the Free Stack in Thread data structure.When successful, returns pointer to frame and decrements the chain length. When unsuccessful,returns NULL pointer.

Overview

Option

Called by moveDescriptorToPostDMA.

Calls to None

Parameters


thread Pointer to ThreadDMA data structure for transaction.

Return Value

Status Description

NULL Request failed.

Pointer to Frame Retrieval of frame successful.

Error Reporting

Status Description

None



PutPostQueueDMA: Private

struct FrameDMA * PutPostQueueDMA(int channel, struct FrameDMA *frame, structThreadDMA *thread1)

The purpose of putPostQueueDMA is to place a frame in the specified ThreadDMA channel postqueue. The function PutPostQueueDMA places a frame into a ThreadDMA Post Queue specifiedby the channel (0, 1 or 2). When successful, adds frame to Post Queue and returns pointer to frame.

Overview

Option

Called by MoveDescriptorToPostDMA.

Calls to None

Parameters



frame pointer to frame to be added to Post Queue.

thread Thread for operation.

Return Value

Status Description

NULL Request to add frame failed.

!= NULL Frame successfully added and pointer to frame returned.

Error Reporting

Status Description

NULL_PTR_PASSED_POST_QUEUE Null pointer passed to be added to Post Queue.



LinkDescriptorDMA: Private

void LinkDescriptorDMA(int channel, struct FrameDMA *frame)

The purpose of function is to append the frame to the channel chain, update Global_DMA datastructures, flush cachelines for current and prior Frame and drain write and fill buffers.

Overview

Option

Called by ExecuteDMA.

Parameters


channel integer specifying the channel.

frame Pointer to frame being appended to chain.

Return Value

Status Description

None

Error Reporting

Status Description

None



FlushDrainDMA: Private

void FlushDrainDMA(struct FrameDMA *frame1, struct FrameDMA*frame2, struct Thread_DMA *thread1)

The purpose of function is to flush the cachelines for the two descriptors passed as parameters fromcache to RAM, drain the write (&fill) buffers and preload to cache the next available Frame in theFree Stack.

Overview

Option

Called by LinkDescriptorDMA

Parameters


frame Pointer to two Frames for to be Flushed from cache.

Return Value

Status Description

None .

Error Reporting

Status Description

None



ChannelBusyDMA: Public

Bool ChannelBusyDMA(int channel)

The purpose of function is to flush the two descriptors passed as parameters from cache to RAMand preload the next available Frame in the Free Stack.

Overview

Option

Called by Application

Parameters


channel DMA Controller Channel.

Return Value

Status Description

TRUE The DMA Controller Channel is still busy.

FALSE The DMA Controller Channel is not busy.

Error Reporting

Status Description

None



8.3 Finish

FinishQueueDMA: Public

int FinishQueueDMA(int channel, struct Thread_DMA * thread1)

The purpose of this function is to traverse the chain for the channel, mark processed descriptors andreturn marked Frames contained in Thread Channel Post Queue to the Free Stack. See Figure 6 andSection 5.4.2.3, “Finish” on page 38.

Overview

Option


Calls to MarkChannelDMA, QueueCleanMarkedDMA.

Paramters



thread1 Thread_DMA being handled with MoveDescriptorToPostDMA.

Return Value

Status Description

0 No descriptors marked.

>=1 At least one descriptor was marked as executed in the channel chainand returned from the Queue to the channel.

Error Reporting

Status Description

None



MarkChannelDMA: Private

int MarkChannelDMA(int channel)

The purpose of this function is to traverse the chain for the specified channel from the tail to theChannel address contained in the DAR (descriptor address register) and Mark those Frames asexecuted. See Section 5.2.3.2, “struct Global_DMA Data Structure” on page 27 (see MarkingExecuted Frames bullet).

Overview

Option

Called by FinishQueueDMA.

Calls to None.

Parameters



Return Value

Status Description

0 No descriptors marked.

>=1 At least one descriptor was marked as executed in the channelchain.

Error Reporting

Status Description

None



QueueCleanMarkedDMA: Public

int QueueCleanMarkedDMA(int channel, struct Thread_DMA *thread1)

The purpose of function is to move the marked Frames, out of the Channel Post Queue to the FreeStack. Its return value is the number of frames moved.

Overview

Option

Called by FinishQueueDMA.

Calls to GetPostQueueDMA, PushFreeStackDMA.

Parameters



thread Pointer to Thread_DMA from calling function.

Return Value

Status Description

Integer > 0x0 Success, at least one Frame was transferred from Post to FreeQueue for the specified channel.

FALSE = 0x0 Failure, no Frames were transferred from the Channel Post to FreeQueue.

Error Reporting

Status Description

MOVE_MARKED_FAILED Attempt move marked frame from Post Queue to Free Stack failed.



MoveDescriptorToFreeDMA: Private

Bool MoveDescriptorToFreeDMA(int channel, struct Thread_DMA *thread1)

Function moveDescriptorToFreeDMA() moves a descriptor from the Post queue for the channelspecified to the ThreadDMA Free Stack.

Overview

Option

Called by ChannelCleanMarkedDMA.

Calls To GetPostQueueDMA and PushFreeStackDMA.

Parameters



thread Pointer to ThreadDMA.

Return Value

Status Description

TRUE Descriptor successfully moved.

FALSE Move failed.

Error Reporting

Status Description

MOVE_TO_FREE_FAILED_PUSH_FREE_STACK_FAILED

Successfully obtained descriptor with getPostQueueDMA, howevercall pushFreeStackDMA failed.

MOVE_TO_FREE_FAILED_GET_POST_QUEUE_FAILED Attempt to remove descriptor from getPostQueueDMA failed.

MOVE_TO_FREE_FAILED_PQ_EMPTY_OR_FSTACK_FULL Post queue for channel empty or Freestack full.



GetPostQueueDMA: Private

struct FrameDMA* GetPostQueueDMA(int channel, struct Thread_DMA *thread1)

The purpose of function GetPostQueueDMA is to remove a Frame from the channel specifiedPost Queue and return a pointer to the Frame removed for the thread specified.

Overview

Option


Calls to None.

Parameters



thread Pointer to ThreadDMA data structure.

Return Value

Status Description

NULL Request to add descriptor to Post queue failed due to Post Queuebeing full or pointer to descriptor being added being NULL.

FrameDMA * Descriptor successfully moved from Post Queue.

Error Reporting

Status Description

POST_QUEUE_EMPTY Null pointer obtained with attempt to move frame from Post Queue.



PushFreeStackDMA: Private

Bool PushFreeStackDMA(int channel, struct Frame_DMA *frame,struct Thread_DMA * thread1)

Function pushFreeStackDMA() takes a pointer to a Frame and pushes it on the specified ThreadFree Stack.

Overview

Option

Called by MoveDescriptorToFreeDMA.

Calls to None.

Parameters


frame Pointer to frame to be pushed on stack.

thread Pointer to Thread_DMA data structure containing Free Stack.

Return Value

Status Description

TRUE Frame successfully pushed on the stack.

FALSE Frame not pushed on Free Stack. Null pointer passed or stack is full.

Error Reporting

Status Description

NULL_PTR_PASSED_PUSH_FREE_STACK Null pointer passed as parameter.



PntrLastInQueueDMA: Private

structFrame_DMA * PntrLastInQueueDMA(int channel, struct Thread_DMA * thread1)

Function return a pointer to the oldest item in a queue. The state of the Queue is not changed.

Overview

Option

Called by FinishDMA, QueueCleanMarkedDMA.

Calls to None.

Parameters


channel Channel specified.

thread thread specified.

Return Value

Status Description

struct Frame_DMA Pointer to oldest in stack.

Error Reporting

Status Description

None



8.4 Exception Handling

intHandlerAttachDMA: Private

void intHandlerAttachDMA(void (*ISR_SERVICE)(void) irq, void(*ISR_SERVICE)(void) fiq, void (*ISR_SERVICE)(void) abrt)

Function intHandlerAttachDMA() attaches handlers to the IRQ, FIQ and ABRT vectors. Note IRQand FIQ handlers are chained with prior vectors while ABRT is not. Also intHandlerABRTDMA()is called to initialize the stack in abrtHandlerDMA().

Overview

Option

Called by InitGlobalDMA.

Calls to intHandlerABRT.

Parameters


irq type ISR_SERVICE, pointer to the function irqHandlerDMA routine.

fiq type ISR_SERVICE, pointer to the function fiqHandlerDMA routine.

abrt type ISR_SERVICE, pointer to the function abrtHandlerDMA routine.

Return Value

Status Description

None

Error Reporting

Status Description

None



intHandlerDetachDMA: Private

void intHandlerDetachDMA(void)

Function intHandlerDetachDMA() detaches the installed interrupt handlers and re-installs the newinterrupt handler in place prior to calling intHandlerAttachDMA().

Overview

Option

Called by TerminateGlobalDMA.

Parameters


next_irq_service

next_fiq_service

next_abrt_service

Global variables containing values loaded to vectors prior to callingintHandlerAttach. Note these values are reloaded to the exceptionvector.

Return Value

Status Description

None

Error Reporting

Status Description

None



irqHandler: Private

void irqHandlerDMA(void)

Function irqHandlerDMA():

• Test the FIQ1ISR register (memory map location 0x1708) for a DMA interrupt pending

• When yes, loads the CSR value to the descriptor being processed

• Clears the interrupt at the source by writing 0xffffffff to the CSR register

Note: The 80312 FIQ causes Redboot to jump to the IRQ vector due to interrupt steering between 80312and 80200.

Overview

Option

Called by Mode change in 80200 IRQmode triggered by setting InterruptEnable in Descriptor Control Register.

Handles end of transfer and end of chain interrupts.

Parameters


None

Return Value

Status Description

None

Error Reporting

Status Description

None



fiqHandlerDMA: Private

void fiqHandlerDMA(void)

Function fiqHandlerDMA()

• Test the IRQISR register (memory map location 0x1700) for a DMA Channel Error pending

• When yes, loads the CSR value to the descriptor being processed

• Clears the interrupt at the source by writing 0xffffffff to the CSR register

Note the 80312 IRQ causes Redboot to jump to the FIQ vector due to interrupt steering between80312 and 80200.

Overview

Option

Called by Mode change to 80200 FIQmode triggered when a PCI or internalbus error condition exists within DMAchannel.

Handles DMA Channel Errors.

Paramters


None

Return Value

Status Description

None

Error Reporting

Status Description

None



abrtHandlerDMA: Private

void abrtHandlerDMA(void)

Function is used to initialize/create a stack for the ABORT mode (mode 0x7). This should havebeen performed by the monitor but was not.

Overview

Option

Called by intHandlerAttach.

Paramters


None

Return Value

Status Description

None

Error Reporting

Status Description

None



intHandlerABRTDMA: Private

void intHandlerABRTDMA(void)

Function is used to initialize/create a stack for the ABORT mode (mode 0x7). This should havebeen performed by the monitor but was not.

Overview

Option

Called by intHandlerAttach.

Paramters


None

Return Value

Status Description

None

Error Reporting

Status Description

None



8.5 Library Termination

TerminateGlobalDMA: Private

Bool TerminateGlobalDMA(void)

The function detaches interrupt exception handlers and restores original vector states. Alsomemory allocated by GlobalDMAInit.

Overview

Option


Calls to intHandlerDetachDMA, free.

Paramters


none

Return Value

Status Description

TRUE Exception handlers detached and memory freed.

FALSE TRUE conditions not meet.

Error Reporting

Status Description



TerminateThreadDMA: Private

struct Thread_DMA * TerminateThreadDMA(Thread_DMA * thread1)

The purpose of this function is to terminate a ThreadDMA by freeing the memory. Note thisrequires the original pointer to memory that is saved within the thread to execute the free() functioncall successfully.

Overview

Option


Calls to free().

Paramters


thread Pointer to ThreadDMA data structure to be terminated.

Return Value

Status Description

TRUE Thread successfully terminated.

FALSE Thread memory unable to be returned.

Error Reporting

Status Description

FREE_UNSUCCESSFUL Free() function call unsuccessful.

Intel® 80310 I/O Processor Chipset DMA Support LibrarySingle Threaded Library Modification


9.0 Single Threaded Library Modification

To run as single thread you can:

• Consolidate functions GlobalDMAInit and ThreadInitDMA.

• Declare single thread as a global data structure and eliminate thread from parameters.

• No semaphores are required to prohibit concurrent access to Global_DMA data structures.

Intel® 80310 I/O Processor Chipset DMA Support LibrarySingle Threaded Library Modification



Intel® 80310 I/O Processor Chipset DMA Support LibraryConclusion


10.0 Conclusion

A discussed increasing I/O demands are central to Network and Storage high performanceapplications. Intel® XScale™ microarchitecture addresses this trend with the 80310 chipset.Features of the Intel 80310 solution include three DMA channels.

This paper and the accompanying source code have presented a DMA Library architecturesspecific solution to provide DMA software developers a template for development fast ramp. Fortheir unique applications, Developers can design and build their own custom solutions using thistemplate along with the Intel-referenced Optimization Guides.

Intel® 80310 I/O Processor Chipset DMA Support LibraryConclusion



Intel® 80310 I/O Processor Chipset DMA Support LibraryGetting Started


Appendix A Getting Started

A.1 Components

The objective of this section is to present the environment prototype used to develop the DMALibrary and run the Testbench. Once started transfer to the specific user application environmentshould be simplified. Below are the components.

• Toolset:

— Redhat, GNUPro Intel® XScale™ microarchitecture toolset installed on host.

— http://www.intel.com/design/iio/devtools/tptools.htm.

— http://www.intel.com/design/intelxscale/.

• Hardware Environment:

— Host computer with com1 and com2 ports.

— IQ80310 Backplane with power supply.

— Two IQ80310 boards inserted in backplane.

— Two serial cables.

• Code unzips to three directories + readme.txt:

— directories:

1.) DMALib.

2.) RunFromHere.

3.) testbench.

+readme.txt file.

• To build goto directory RunFromHere and type “lib“:

— master.elf and slave.elf are binaries.

A.2 Hardware and Software Setup

• Software:

— Load GNUPro tools to Host and set path.

— Unzip tools to directory.

• Hardware:

— Connect backplane to power supply.

— Plug IQ80310 boards into backplane J2 and J3 PCI slots.

— Connect serial cables to serial port J9 on each board and the host ports: com1 and com2.

— Warning: BUS Arbiter on the back plane very slow.

http://www.intel.com/design/iio/devtools/tptools.htm

http://www.intel.com/design/intelxscale/

Intel® 80310 I/O Processor Chipset DMA Support LibraryGetting Started


A.3 Running the Images

Open two dos windows with cmd.exe.

In sequence:

1. Go to one dos window and type “s1”, this starts a command line gdb session and step to thecode following the setup/initialization sequence. Note m1.bat and m1.gdb automate theconnection process.

2. Go to the other dos window and type “m1”, this starts a GUI gdb session and step to the codefollowing the setup/initialization sequence. Note m1.bat and m1.gdb automate the connectionprocess.

3. You can now step through the executing DMA testbench in both windows. Performingtransfers and verifying transfer on destination.

Intel® 80310 I/O Processor Chipset DMA Support LibraryTestbench


Appendix B Testbench

B.1 Overview

The purpose of this section is to present the software testbench used in the development of DMALibrary. The following testbench template can be used as a vehicle to develop your own routines. Thetestbench developed should be tested against the requirements of your application and validated.

B.2 Benefits

• Allows automated easy to program running of multiple experiments.

• Each experiment output complete 80200 and 80312 PMU statistics.

B.3 Testbench Components

This testbench was created to exercise the DMA Library and provide PMU timing measurements.

Input: Testbench and Library files.

Output: Two .elf images, master.elf and slave.elf.

Both images set up the ATUs while only one image runs the testbench().

The zip file unzips to three directories.

B.3.1 Directory: RunFromHere

Contains GDB related files plus images:

• lib.bat

• m1.bat

• m1.gdb

• s1.bat

• s1.gdb

• slave.elf

• master.elf



B.3.2 Directory: testbench

Testbench files to set up ATUs on backplane, define and run experiments, set 80200 and 80312PMUs and save print PMU output:

• 80310_main.c

• 80310_PMUs.h

• TestBench.h

• TestBench.c

• 80310_timer.h

• 80310_timer.c

• 80310_ATU.h

• 80310_ATU.c

• benchHeaders.h

• core.h

• datatypesDMALib.h

• makefile

• master.elf

• slave.elf

• userDefsDMA_TestBench.h

B.3.3 Directory: DMALib

• 80310_fiq_irq.h

• 80310_fiq_irq.c

• 80310_Global.h

• 80310_Global.c

• 80310_ThreadDMA.h

• 80310_ThreadDMA.c

• 80310_DMA.h

• core.h

• dmalibHeaders.h

• liberror.h

• makefile

• userDefsDMALib.h



B.4 Defining Creating Experiments

The parameters generating experiments is defined in the file userDefsDMA_TestBench.h providesthe input for experiments. See data structure instructions in the referenced file.

struct exp{ /* Defines the structure of a single experiment.*/

......

}

Below the above data structure definition are the experiments with a description on how to define them.

B.5 Test Generation

The test data written to one card to be transferred with the DMA to the destination card is createdby function: createSourceTestData() contained in file 80310_TestBench.c.

B.6 Descriptor Generation

The generation of the descriptors used in the testbench is performed by functioncreateSourceDescriptors also contained in the file 80310_TestBench.c.

B.7 Performance Measurements: PMU

Performance programs are enabled for both the 80200 and 80312 performance monitors and thefunction calls and data structures reside in files 80310_timer.c and 80310_timer.h. Note the resultsare stored to a global variable and saved to the exp data structure. To understand requires a reviewof the Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Developer’s Manualand the Intel® 80312 I/O Companion Chip Developer’s Manual.

Performance measurements are started with:

• performance = timerStart_80200_80312(,);

Measurements are concluded with the:

• timerFinish_80200_80312();

• Experiments[currentExp].exp_results = performance;

The timing measurements are saved to the data structure: struct stats

B.8 Output Generation and Manipulation

By running using the GNUPro GUI and opening a console, the code can be moved through and theprint statements are reflected in the console window. Output is currently set up to print a indexnumber and Channel Status Register output for each DMA transaction.

Intel® 80310 I/O Processor Chipset DMA Support LibraryDMA Library Source Code


Appendix C DMA Library Source Code

C.1 DMA Library makefile that Builds Objects to be Integratedinto Application

#/******************************************************************************

# *

# * Copyright (c) 1993, 1994 Intel Corporation. All rights reserved.

# *

# *

# * Intel hereby grants you permission to copy, modify, and distribute this

# * software and its documentation. Intel grants this permission provided

# * that the above copyright notice appears in all copies and that both the

# * copyright notice and this permission notice appear in supporting

# * documentation. In addition, Intel grants this permission provided that

# * you prominently mark as not part of the original any modifications made

# * to this software or documentation, and that the name of Intel

# * Corporation not be used in advertising or publicity pertaining to the

# * software or the documentation without specific, written prior

# * permission.

# *

# * Intel provides this AS IS, WITHOUT ANY WARRANTY, INCLUDING THE WARRANTY

# * OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, and makes no

# * guarantee or representations regarding the use of, or the results of the

# * use of, the software and documentation in terms of correctness,

# * accuracy, reliability, currentness, or otherwise, and you rely on the

# * software, documentation, and results solely at your own risk.

# *

# **************************************************************************/

#/* */

#/* History: */

#/* 11Nov01 LGS Initial Release */

#/* */

#/****************************************************************************/

#****************************************************************************

# Use makefile for GNUPro XScale toolchain *



#****************************************************************************

#OBJS_SLAVE = s80310_main.o 80310_TestBench.o 80312_ATU.o 80310_timer.o dmalibops

#OBJS_MASTER= m80310_main.o 80310_TestBench.o 80312_ATU.o 80310_timer.o dmalibops

CC = xscale-elf-gcc

LD = xscale-elf-ld

OBJ = xscale-elf-objdump

SPECS = iq80310.specs

DB = -g

# for optimization try -O1,-O2 and -O3 to see which run fastest

OPT = -O0

.SUFFIXES: .o .c .s

LIST = -Wa,-alhd=$*.lst, -fverbose-asm

MASTERCFLAGS = $(DB) $(OPT) -Wall -specs=$(SPECS) -mcpu=xscale -DMASTER$(LIST)

SLAVECFLAGS = $(DB) $(OPT) -Wall -specs=$(SPECS) -mcpu=xscale

LDFLAGS = -specs=$(SPECS)

CMAP = -Wl,--cref,-Map,$*.map

#--------------------------------------------------------------------------

#build library object files

#--------------------------------------------------------------------------

all: 80310_ThreadDMA.o 80310_Global.o 80310_fiq_irq.o

80310_ThreadDMA.o: 80310_ThreadDMA.c

$(CC) $(MASTERCFLAGS) $(CMAP) -c -o 80310_ThreadDMA.o 80310_ThreadDMA.c

80310_Global.o: 80310_Global.c

$(CC) $(MASTERCFLAGS) $(CMAP) -c -o 80310_Global.o 80310_Global.c

80310_fiq_irq.o: 80310_fiq_irq.c

$(CC) $(MASTERCFLAGS) $(CMAP) -c -o 80310_fiq_irq.o 80310_fiq_irq.c



C.2 userDefsDMALib.h

/******************************************************************************

*

* Copyright (c) 1993, 1994 Intel Corporation. All rights reserved.

*

*

* Intel hereby grants you permission to copy, modify, and distribute this

* software and its documentation. Intel grants this permission provided

* that the above copyright notice appears in all copies and that both the

* copyright notice and this permission notice appear in supporting

* documentation. In addition, Intel grants this permission provided that

* you prominently mark as not part of the original any modifications made

* to this software or documentation, and that the name of Intel

* Corporation not be used in advertising or publicity pertaining to the

* software or the documentation without specific, written prior

* permission.

*

* Intel provides this AS IS, WITHOUT ANY WARRANTY, INCLUDING THE WARRANTY

* OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, and makes no

* guarantee or representations regarding the use of, or the results of the

* use of, the software and documentation in terms of correctness,

* accuracy, reliability, currentness, or otherwise, and you rely on the

* software, documentation, and results solely at your own risk.

*

**************************************************************************/

/* */

/* History: */

/* 11Nov01 LGS Initial Release */

/* */

/****************************************************************************/

#ifndef _USERDEFSDMALIB_H

#define _USERDEFSDMALIB_H



/*-----------------------------------------------------------------------------

**

** L I T E R A L S

**

**---------------------------------------------------------------------------*/

/*****************************************************************************

******************************************************************************

******************************************************************************

** Optimization Related: Use these to tune applications***********************

******************************************************************************

******************************************************************************

******************************************************************************/

/* Also try optimization values in Makefile

* -O1,O2 or O3

* -funroll-loops

* -foptimize-comparisons

*/

/*****************************************************************************

* Number of Frames declared for each channel. There are three channels for

* thread. The stack size is # of channels * 3

*****************************************************************************/

#define CHANNELSIZE 0x40

/*****************************************************************************

* Interval in which Finish routine is called Frames to Stack of executed

* descriptors.

*****************************************************************************/

#define QUEUE_FRAME_RECLAIM_INTERVAL 0x4

/* Do not alter value. To ensure Finish is triggered for value < Queue size. */

#if CHANNELSIZE <= QUEUE_FRAME_RECLAIM_INTERVAL

#define QUEUE_FRAME_RECLAIM_INTERVAL (CHANNELSIZE-1)

#endif



/*****************************************************************************

******************************************************************************

******************************************************************************

** Debug Related

******************************************************************************

******************************************************************************

******************************************************************************/

/*****************************************************************************

* Switch to generate output regarding Channel Chain. Prints items appended

* to chain and lists the Frames in Channel Chains as tracked by the

* global variables. FALSE disables, TRUE enables

*****************************************************************************/

#define DEBUG_FINISH_ROUTINEFALSE

/*****************************************************************************

* Error Reporting in global variable liberror. TRUE turn on. FALSE turn off.

*

*****************************************************************************/

#define ERROR_REPORTING FALSE

/*****************************************************************************

******************************************************************************

******************************************************************************

** Initialization Related

******************************************************************************

******************************************************************************

******************************************************************************/

/* TRUE if using Channel 2, else FALSE */

#define CHANNEL_2 FALSE

/* Dummy transfer for initialization & clean queue with not interrupts */

#define NDA 0x0

#define PAD (void*)0x4a000100

#define PUAD 0x0



#define LAD (void*)0xa1000100

#define BC 0x0

#define DC 0x1f

/*****************************************************************************

******************************************************************************

******************************************************************************

** Misc Other

******************************************************************************

******************************************************************************

******************************************************************************/

/* Requires change for multi-threading. This identifies where user OS/monitor

* semaphores are required for threading and protection of common data

* structures

*/

#define SEMGET() FALSE

#define SEMEXIT() FALSE

/* Do not change: hardware contains three channels*/

#define DMA_CHANNELS 0x3

/* Do not change: global define */

typedef int Bool;

#undef TRUE

#define TRUE 1

#undef FALSE

#define FALSE 0

#endif



C.3 80310_ThreadDMA.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _80310_THREADDMA_H

#define _80310_THREADDMA_H

#include “dmalibHeaders.h”



/*-----------------------------------------------------------------------------

**

** L I T E R A L S

**

**---------------------------------------------------------------------------*/

#define FRAMEPOOL (CHANNELSIZE * DMA_CHANNELS)

#define ATUCLSR (volatile unsigned int *) 0x120c

#define PATUCMD (volatile unsigned int *) 0x1204

#define SATUCMD (volatile unsigned int *) 0x1298


#define MEMORY_WRITE_AND_INVALIDATE_ENABLE 0x10;

/*-----------------------------------------------------------------------------

**

** S T R U C T U R E S / T Y P E D E F S

**

**---------------------------------------------------------------------------*/

struct Frame_DMA{


void * pad; /* Source Address (Lower)*/

void * puad; /* Source Address (Upper)*/

void * lad; /* Destination Address*/


unsigned int dc; /* Descriptor Control*/

short pid; /* pid */

short tid; /* tid */

short csr; /* CSR value */

short mark; /* If != 0 then executed*/

};

/* Container designed to fit one cacheline (32 bytes).*/

struct Queue_DMA{

int CircQ_Front;

int CircQ_Length;

int CircQ_Limit;





unsigned int * dar_ptr;

struct Frame_DMA * pad1;


struct Frame_DMA * CircQ[CHANNELSIZE];

};

struct Stack_DMA{

int Stack_Length;

int Stack_Limit;


struct Frame_DMA * Stack[FRAMEPOOL];

};

/* Align on 8 word boundary. */

struct Thread_DMA{

struct Frame_DMA Frame[FRAMEPOOL];

struct Stack_DMA FreeStack; /* Unissued descriptors. */

struct Queue_DMA Channel[DMA_CHANNELS];/* Channel 0 ,1 & 2. */

void * toFreeMem;

};

/*----------------------------------------------------------------------------

**

** M A C R O S

**

**---------------------------------------------------------------------------*/

/*****************************************************************************

* Macro: Returns DMA engine CSR value for the channel specified

*****************************************************************************/

#define CHANNEL_CSR(channel,thread1)(*(thread1)->Channel[channel].csr_ptr)

/*****************************************************************************

* Macro: Sets DMA engine resume and enable for channel specified

*****************************************************************************/

#define RESUME_ENABLE(channel,t) (*(thread1)->Channel[channel].ccr_ptr |= 0x3)



/*****************************************************************************

* Macro: Returns TRUE if DMA channel is busy

*****************************************************************************/

#define CHANNEL_BUSY(channel,thread1)((CHANNEL_CSR(channel,thread1)!=0x0)?(TRUE):(FALSE))

/*****************************************************************************

* Macro: Returns TRUE if either:

* - Queue length > QUEUE_FRAME_RECLAIM_INTERVAL

* - Queue length >= Queue size limit

*****************************************************************************/

#define FINISHTEST(c,t) ((FINISHTEST1(c,t)||FINISHTEST2(c,t))?(TRUE):(FALSE))

#define FINISHTEST1(c,t)(QUEUE_FRAME_RECLAIM_INTERVAL <((t)->Channel[(c)].CircQ_Length))

#define FINISHTEST2(c,t)((t)->Channel[(c)].CircQ_Length >=(t)->Channel[(c)].CircQ_Limit)

/*****************************************************************************

* Macro: Preload cacheline for next Frame one thread stack

*****************************************************************************/

#define PRELOADFRAME(t)asm("PLD [%0], #32":: "r" (TOS(t)))

#define TOS(t) (t->FreeStack.Stack[t->FreeStack.Stack_Length-1])

/*-----------------------------------------------------------------------------

**

** P R O T O T Y P E S

**

**---------------------------------------------------------------------------*/

/* Queue Management */

/* Public APIs*/

int ThreadSizeDMA();

struct Thread_DMA * InitThreadDMA(void * thread1);

struct Frame_DMA * MoveDescriptorToPostDMA(int channel, structThread_DMA* thread1);

inline Bool ExecuteDMA(int channel,struct Frame_DMA*frame,struct Thread_DMA * thread1);

Bool FinishQueueDMA(int channel, struct Thread_DMA *thread1);



/* Private APIs*/

struct Frame_DMA * PopFreeStackDMA(struct Thread_DMA* thread1);

struct Frame_DMA * PutPostQueueDMA(int channel, struct Frame_DMA *frame, struct Thread_DMA* thread1);

int MarkChannelDMA(int channel);

int QueueCleanMarkedDMA(int channel, struct Thread_DMA *thread1);

Bool MoveDescriptorToFreeDMA(int channel, structThread_DMA* thread1);

struct Frame_DMA * GetPostQueueDMA(int channel, struct Thread_DMA*thread1);

Bool PushFreeStackDMA(struct Frame_DMA * frame, structThread_DMA* thread1);

struct Thread_DMA * TerminateThreadDMA(struct Thread_DMA* thread1);

struct Frame_DMA * PntrLastInQueueDMA(int channel,struct Thread_DMA*thread1);

/* For debugging */

void * TestMemAlloc();

int ChannelBusy(int channel,struct Thread_DMA*thread1);

/*-------------------------------------------------------------------------------------------------*/

/*-----------------------------------------------------------------------------

**

** G L O B A L S V A R I A B L E S

**

**---------------------------------------------------------------------------*/

extern struct Global_DMA ChainsDMA; /* Global Chain Variables*/

extern int liberror;

#endif



C.4 80310_ThreadDMA.c

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

/*-----------------------------------------------------------------------------

**

** I N C L U D E F I L E S

**

**---------------------------------------------------------------------------*/



#include "80310_ThreadDMA.h"

/*-----------------------------------------------------------------------------

**

** G L O B A L V A R I A B L E ( S )

**

**---------------------------------------------------------------------------*/

int liberror;/* Global variable for error reporting */


/*****************************************************************************

* Function calculates and return sizeof a Thread_DMA in bytes plus room

* for alignment.

*****************************************************************************/

int ThreadSizeDMA(){

return (sizeof(struct Thread_DMA) + 0x20);

}

/*****************************************************************************

* Function either takes a pointer to memory or allocated memory for Thread_DMA

* data structure. Then aligns, initializes and returns a pointer it.

*****************************************************************************/

struct Thread_DMA* InitThreadDMA(void * thread1){

struct Thread_DMA*dma;

int i, j;/* Index*/

unsigned int addr;

void * ToFreeDMA;

if(thread1 == NULL){ /* Program to allocate memory */

ToFreeDMA= (void *)malloc(ThreadSizeDMA());

}else{ /* User allocated memory*/

ToFreeDMA = thread1;

}

if(ToFreeDMA == NULL){

liberror = INIT_THREAD_MALLOC_FAILED;



return FALSE;

}

dma = (struct Thread_DMA *)(((unsigned int)(ToFreeDMA) &0xffffffe0)+0x20);

dma->toFreeMem = ToFreeDMA;

dma->FreeStack.Stack_Length= FRAMEPOOL;

dma->FreeStack.Stack_Limit= FRAMEPOOL;

dma->Channel[0].CircQ_Front=0;

dma->Channel[0].CircQ_Length= 0;

dma->Channel[0].CircQ_Limit= CHANNELSIZE;

dma->Channel[0].ccr_ptr=(unsigned int *)CCR_0_80312;

dma->Channel[0].csr_ptr=(unsigned int *)CSR_0_80312;

dma->Channel[0].dar_ptr=(unsigned int *)DAR_0_80312;













/************************************************************/

/* Free Stack Initialization */

/* - Put all buffers in the free stack*/

/* - Set csr and mark to 0x0 */

/************************************************************/

for(i=0,j=0; i < FRAMEPOOL; i++,j++){



dma->FreeStack.Stack[i]=(struct Frame_DMA*)&dma->Frame[j];

dma->FreeStack.Stack[i]->csr=0x0;/* Set csr value to 0x0 */

dma->FreeStack.Stack[i]->mark= 0x0;/* Sets mark to 0x0 */

addr = (unsigned int)dma->FreeStack.Stack[i];

}

/* Set all pointers to Queues to NULL*/

for(i=0; i < CHANNELSIZE; i++){

dma->Channel[0].CircQ[i]=(struct Frame_DMA*)NULL;



}

return dma; /* Return pointer to Thread_DMA data structure */

}

/*****************************************************************************

* Moves Frame from thread Free Stack to Channel circular queue and returns

* pointer to Frame.

*****************************************************************************/

struct Frame_DMA * MoveDescriptorToPostDMA(int channel, structThread_DMA* thread1){

struct Frame_DMA * p1;

struct Frame_DMA * p2;

Bool push;

/* If Queue is full or QUEUE_FRAME_RECLAIM_INTERVAL met then call FinishRoutine */

if(FINISHTEST(channel,(struct Thread_DMA*)thread1)){

FinishQueueDMA(channel,(struct Thread_DMA*)thread1);

}

p1 = PopFreeStackDMA(thread1);/* Request descriptor*/

if(p1 != NULL){ /* (Successful) in getting descriptor*/

p2 = PutPostQueueDMA(channel,p1,thread1);/* (Successful) add to PostQueue */

if(p2 != NULL){

return p2; /* (Successful) return pointer */



}else{

push = PushFreeStackDMA(p1,thread1);/* (Failure) return to Free Stack*/

#if ERROR_REPORTING

if(push == FALSE){

liberror = POSTQ_FULL_FREEQ_PUSH_FAILED;

}else{

liberror = POSTQ_FULL_RETURN_TO_FREE;

}

#endif

return (struct Frame_DMA*)NULL;/* (Failure) return Null */

}

}else{ /* (Failure) No free frames*/

#if ERROR_REPORTING

liberror = NO_FREE_DESCRIPTORS;

#endif

return (struct Frame_DMA*)NULL;/* (Failure) return NULL*/

}

}

/*****************************************************************************

* Function takes Frame:

* - Appends it to the specified channel chain

* - For the channel, sets resume and enable

* - Preloads cacheline of next Frame on thread free stack

*****************************************************************************/

inline Bool ExecuteDMA(int channel, struct Frame_DMA *frame, struct Thread_DMA*thread1){

LinkDescriptorDMA(channel,frame);

RESUME_ENABLE(channel,thread1);

PRELOADFRAME(thread1);

return TRUE;

}

/*****************************************************************************

* Routine removes marked Frames from Channel Queue. If oldest Frame is marked



* then removes Frames starting with the oldest until the first unmarked Frame

* is encountered. If the oldest is not marked, then MarkChannelDMA() is called

* and then marked Frames are removed until unmarked Frame is encountered.

*****************************************************************************/

int FinishQueueDMA(int channel, struct Thread_DMA *thread1){

struct Frame_DMA * t;

#if DEBUG_FINISH_ROUTINE

printChannelChain(channel);

printf("((((CALL FINISH))))\n");

#endif

while(CHANNEL_BUSY(channel,thread1)){}

t = PntrLastInQueueDMA(channel,thread1);

if(t->mark != 0x0){

return QueueCleanMarkedDMA(channel,thread1); /* If marked, call clean*/

}else{

MarkChannelDMA(channel); /* If not marked, mark then clean */

return QueueCleanMarkedDMA(channel,thread1);

}

}

/*****************************************************************************

* For Thread, pops top Frame off the Stack and return pointer to removed

* Frame. If Stack is empty returns NULL.

*****************************************************************************/

struct Frame_DMA* PopFreeStackDMA(struct Thread_DMA* thread1){

struct Frame_DMA*p;

if(thread1->FreeStack.Stack_Length != 0x0){

p = thread1->FreeStack.Stack[--thread1->FreeStack.Stack_Length];

thread1->FreeStack.Stack[thread1->FreeStack.Stack_Length]=NULL;

p->csr = 0x0;

p->mark= 0x0;

return (struct Frame_DMA*)p;

}

else{

return (struct Frame_DMA*)NULL;

}



}

/*****************************************************************************

* Adds Frame to Queue to Channel and Thread specified and return pointer to

* appended Frame. If queue is full returns NULL.

*****************************************************************************/

struct Frame_DMA * PutPostQueueDMA(int channel, struct Frame_DMA * frame,structThread_DMA* thread1){

int pos;

if((thread1->Channel[channel].CircQ_Length !=thread1->Channel[channel].CircQ_Limit) &

((struct FrameDMA*)frame != (struct FrameDMA*)NULL)){

pos = (thread1->Channel[channel].CircQ_Front +thread1->Channel[channel].CircQ_Length) % thread1->Channel[channel].CircQ_Limit;

thread1->Channel[channel].CircQ[pos]=frame;

thread1->Channel[channel].CircQ_Length++;

return (struct Frame_DMA *)frame;/* return pointer to descriptor */

}

else if(frame != (struct Frame_DMA*)NULL){ /* (Non-Failure) Post Queue Full*/


}

else{ /* (Failure) Null pointer passed*/

liberror = NULL_PTR_PASSED_POST_QUEUE;


}

}

/*****************************************************************************

* Routine marks executed Frames. Traverses and marks chain for Channel

* specified starting from Tail until Channel Frame in Descriptor Address

* Register is encountered.

*****************************************************************************/

int MarkChannelDMA(int channel){

struct Frame_DMA * temp;

void * dar;



int counter = 0x0;

/* Get Tail and DAR values */

temp = (struct Frame_DMA *)ChainsDMA.Channel[channel].Tail;

dar = (void*)*ChainsDMA.Channel[channel].dar_ptr;

/* If Tail == DAR, Channel Chain contains 0 elements, exit and return 0x0*/

if(temp == dar){

return 0;

}

/* Traverse Chain until reach DAR, Marking all elements */

while(temp != dar){

counter++;

temp->mark = (short)0xffff;

temp = temp->nda;

}

ChainsDMA.Channel[channel].Tail = temp;/* Set Tail to unmarked Frame */

return counter; /* Return qty of elements marked */

}

/*****************************************************************************

* Removes all Marked Frames from the queue for the Channel and Thread

* specified.

*****************************************************************************/

int QueueCleanMarkedDMA(int channel, struct Thread_DMA *thread1){

int counter=0;

struct Frame_DMA *t;

while(1){

t = PntrLastInQueueDMA(channel,thread1);

if(t->mark != 0x0){

counter++;

if(!MoveDescriptorToFreeDMA(channel,thread1)){

return (counter * -1);

}

}

else{



return counter; /* Normal exit point */

}

} /* End while() */

}

/*****************************************************************************

* Moves Frame from the specified Thread and Channel queue to the Thread

* stack and returns pointer.

*****************************************************************************/

Bool MoveDescriptorToFreeDMA(int channel, struct Thread_DMA* thread1){

struct Frame_DMA * cd;

/* Test: it queue not empty. */

if((thread1->Channel[channel].CircQ_Length != 0x0) &(thread1->FreeStack.Stack_Length != thread1->FreeStack.Stack_Limit)){

cd = GetPostQueueDMA(channel,thread1);

/* printf("CSR Deleted (%x)\n",cd->csr); */

/* Push to error queue add here. */

if((struct Frame_DMA*)cd != NULL){

if(PushFreeStackDMA(cd,thread1)){


printf("Return Frame:-Index(%04d) Thread(%2d)Addr(0x%08X)\n",cd->tid,cd->pid,cd);

#endif

return TRUE;

}else{

cd = PutPostQueueDMA(channel,cd,thread1);

#if ERROR_REPORTING

liberror = MOVE_TO_FREE_FAILED_PUSH_FREE_STACK_FAILED;

#endif

return FALSE;

}

}else{

#if ERROR_REPORTING

liberror = MOVE_TO_FREE_FAILED_GET_POST_QUEUE_FAILED;

#endif



return FALSE;

}

}else{

#if ERROR_REPORTING

liberror = MOVE_TO_FREE_FAILED_PQ_EMPTY_OR_FSTACK_FULL;

#endif

return FALSE;

}


printf("Return Frame2:-Index(%04d) Thread(%2d)Addr(0x%08X)\n",cd->tid,cd->pid,cd);

#endif

return TRUE;

}

/*****************************************************************************

* Gets Frame from queue specified by the Channel and Thread and returns a

* pointer to the Frame.

*****************************************************************************/

struct Frame_DMA*GetPostQueueDMA(int channel,struct Thread_DMA* thread1){

struct Frame_DMA *p;

int x;

x = thread1->Channel[channel].CircQ_Length;

if(x != 0x0){

p =thread1->Channel[channel].CircQ[thread1->Channel[channel].CircQ_Front++];

thread1->Channel[channel].CircQ[thread1->Channel[channel].CircQ_Front-1]=NULL; /*For debug only */

thread1->Channel[channel].CircQ_Front %=thread1->Channel[channel].CircQ_Limit;

thread1->Channel[channel].CircQ_Length--;

return (struct Frame_DMA*)p;

}

else{

liberror = 3;


}



}

/*****************************************************************************

* Pushes Frame on the Stack specified by the Thread.

*****************************************************************************/

Bool PushFreeStackDMA(struct Frame_DMA * frame,struct Thread_DMA* thread1){

if((thread1->FreeStack.Stack_Length != thread1->FreeStack.Stack_Limit) &

(frame != (struct Frame_DMA*)NULL)

){

thread1->FreeStack.Stack[thread1->FreeStack.Stack_Length++] = frame;

return TRUE;

}

else if(frame != NULL){ /* Free Stack Full */

return FALSE;

}else{ /* Null pointer passed*/

liberror = NULL_PTR_PASSED_PUSH_FREE_STACK;

return FALSE;

}

}

/*****************************************************************************

* Frees memory for thread after ensuring executions have completed

*****************************************************************************/

struct Thread_DMA* TerminateThreadDMA(struct Thread_DMA* thread1){

while(CHANNEL_BUSY(0,thread1)){} /* Wait until channel not busy*/



free(thread1->toFreeMem); /* Free memory*/

return (struct Thread_DMA*)NULL;

}

/*****************************************************************************

* Returns pointer to oldest Frame in specified Channel and Thread.

*****************************************************************************/

struct Frame_DMA * PntrLastInQueueDMA(int channel,struct Thread_DMA* thread1){

return thread1->Channel[channel].CircQ[thread1->Channel[channel].CircQ_Front];



}

/*****************************************************************************

* Debug: Allocates memory and returns pointer to memory segment.

*****************************************************************************/

void * TestMemAlloc(){

return (void *)malloc(ThreadSizeDMA());

}

/*****************************************************************************

* Debug: Function call returns TRUE if channel busy and FALSE otherwise.

*****************************************************************************/

int ChannelBusy(int channel,struct Thread_DMA*thread1){

return CHANNEL_BUSY(channel,thread1);

}



C.5 80310_Global.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _80310_GLOBALS_H

#define _80310_GLOBALS_H

#include "dmalibHeaders.h"



/*-----------------------------------------------------------------------------

**

** L I T E R A L S

**

**---------------------------------------------------------------------------*/

#define CHANNEL_00 0x0



/* DMA memory mapped registers */

#define NDAR0 (volatile unsigned int *)0x1410



#define CCR0 (volatile unsigned int *)0x1400



/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

/* DMA Channel Chain variable */

struct Channel_DMA{

struct Frame_DMA *Head; /* Last Frame appended */

struct Frame_DMA *PriorHead;/* Next to last appended */

struct Frame_DMA *Tail; /* Oldest unmarked frame */

unsigned int *dar_ptr;/* Channel DAR */

void *pad1;

void *pad2;

void *pad3;

void *pad4;

};

/* Structure mapping three Channel_DMAs to DMA Controller Channels */



struct Global_DMA{

struct Channel_DMA Channel[DMA_CHANNELS];

};

/*-----------------------------------------------------------------------------

**

** M A C R O S

**

**---------------------------------------------------------------------------*/

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

/* Public*/

Bool GlobalDMAInit();

/* Private*/

inline void LinkDescriptorDMA(int channel, struct Frame_DMA *frame);

inline void FlushDrainDMA(struct Frame_DMA *frame1,struct Frame_DMA *frame2);

void TerminateGlobalDMA();

void FlushDrainFullCacheDMA();

/* Debug*/

void printChannelChain(int channel);

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/


#endif



C.6 80310_Global.c

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

/*-----------------------------------------------------------------------------

**


**



**---------------------------------------------------------------------------*/

#include "80310_Global.h"

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

struct Frame_DMA *Ch[DMA_CHANNELS];/* Used for init */

static void *FreeMem[DMA_CHANNELS];/* Used for init */

/* Global Chain Variables cacheline aligned */

struct Global_DMA ChainsDMA __attribute__((aligned(32)));

/*-----------------------------------------------------------------------------

**

** F U N C T I O N S (S)

**

**---------------------------------------------------------------------------*/

/*****************************************************************************

* Function called once or global initialization prior to creating threads

* - Attaches interrupt handlers (Chains handlers)

* - Puts each channel is state to use chaining by performing transfer

* - Returns TRUE if all three channels successfully initialized

*****************************************************************************/

BoolGlobalDMAInit(){

int size,

test;

test = 0; /* Incremented for each successful channel transfer */

intHandlerAttachDMA(irqHandlerDMA,fiqHandlerDMA,abrtHandlerDMA);

/* Allocate memory for one descriptor DMA each of three channels. */

size = (sizeof(struct Frame_DMA) + 0x20);

FreeMem[CHANNEL_00]= (void *)malloc(size);

if(FreeMem[CHANNEL_00] == NULL){ return FALSE; }

Ch[CHANNEL_00] =(struct Frame_DMA *)(((unsigned int)(FreeMem[0]) &0xffffffe0)+0x20);

/*-------------------------------------------------------------------*/






/*-------------------------------------------------------------------*/




/* Initialize Channel 0---------------------------------------------*/

Ch[CHANNEL_00]->nda = NDA;

Ch[CHANNEL_00]->pad = PAD;

Ch[CHANNEL_00]->puad= PUAD;

Ch[CHANNEL_00]->lad = LAD;

Ch[CHANNEL_00]->bc = BC;

Ch[CHANNEL_00]->dc = DC;

Ch[CHANNEL_00]->csr = 0x0;

ChainsDMA.Channel[CHANNEL_00].Head= Ch[CHANNEL_00];

ChainsDMA.Channel[CHANNEL_00].Tail= Ch[CHANNEL_00];

ChainsDMA.Channel[CHANNEL_00].dar_ptr= (unsigned int*)DAR_0_80312;

FlushDrainFullCacheDMA();

*CCR0 &= 0xfffe;/* Disable Channel */

*NDAR0 = (unsigned int)Ch[CHANNEL_00];/* Loadfirst Descriptor*/

*CCR0 |= 0x3; /* Resume */

if(Ch[CHANNEL_00]->csr != 0x0){

test++;

}

/* Initialize Channel 1---------------------------------------------*/



Ch[CHANNEL_01]->puad = PUAD;











*CCR1 &= 0xfffe; /* DisableChannel */

*NDAR1 = (unsigned int)Ch[CHANNEL_01];/* Loadfirst Descriptor */

*CCR1 |= 0x3; /*Resume/Enable */

if(Ch[CHANNEL_01]->csr != 0x0){

test++;

}

#if CHANNEL_2 == TRUE

/* Initialize Channel 2*/



Ch[CHANNEL_02]->puad = PUAD;









*CCR2 &= 0xfffe;/* Disable Channel*/

*NDAR2 = (unsigned int)Ch[CHANNEL_02];/* Loadfirst Descriptor */

*CCR2 |= 0x1; /* Resume/Enable */

if(Ch[CHANNEL_02]->csr == 0x0){

test++;

}

#endif

/*********************************************************************

* See Section 9.5.3 in Intel® 80312 I/O Companion Chip Developer’s Manual

* Required for memory write and invalidate PCI Command



**********************************************************************/

*ATUCLSR|= ATU_CACHELINE_SIZE_16DWORDS;



#if ERROR_REPORTING

if( test == 0x1){

liberror = CHANNEL_INIT_FAILED_ONE_CHANNEL;

}

else if(test == 0x2){

liberror = CHANNEL_INIT_FAILED_TWO_CHANNEL;

}

else if(test == 0x3){

liberror = CHANNEL_INIT_FAILED_THREE_CHANNEL;

}

#endif

if(test == 0x0){

return TRUE;

}else{

return FALSE;

}

}

/*****************************************************************************

* Function appends Frame/Descriptor to channel chain, updated globals

* chain variables, flushes cachelines and drains write/fill buffers.

* Semaphores required for multi-threading.

*****************************************************************************/

inline voidLinkDescriptorDMA(int channel, struct Frame_DMA *frame){

/* Semaphore required for Global Structure*/

if(SEMGET()){/* Put semaphore here */}

ChainsDMA.Channel[channel].PriorHead = ChainsDMA.Channel[channel].Head;

ChainsDMA.Channel[channel].Head= frame;

ChainsDMA.Channel[channel].Head->nda= NULL;

ChainsDMA.Channel[channel].PriorHead->nda= ChainsDMA.Channel[channel].Head;/*



Link */

FlushDrainDMA((struct Frame_DMA *)ChainsDMA.Channel[channel].PriorHead,(structFrame_DMA *)ChainsDMA.Channel[channel].Head);


printf("Appended Frame:+Index(%04d)Channel(%d) Thread(%02d) Tail(0x%08X)PriorHead(0x%08X)->Head(0x%08X)\n",current_descriptor->tid,channel,current_descriptor->pid,ChainsDMA.Channel[channel].Tail,ChainsDMA.Channel[channel].PriorHead,ChainsDMA.Channel[channel].Head);

#endif

if(SEMEXIT()){ /* Put semaphore here */}

}

/*****************************************************************************

* Flushs two cachelines corresponding to descriptor. Then drains write (&fill)

* buffers.

*****************************************************************************/

inline void FlushDrainDMA(struct Frame_DMA *frame1,struct Frame_DMA *frame2){

asm("MCR P15, 0, %0, C7, C10, 1" : : "r" (frame1)); /* Clean cacheline*/

asm("MCR P15, 0, %0, C7, C10, 1" : : "r" (frame2)); /* Clean cacheline*/

asm("MCR p15, 0, ip, C7, C10, 4"); /* Drain write (&fill) buffer */

}

/*****************************************************************************

* Called after ALL threads terminated. Detaches interrupt handlers returning

* vectors to pre-install state. Then frees memory used perform initialization.

*****************************************************************************/

void TerminateGlobalDMA(){

intHandlerDetachDMA();

free(FreeMem[0]);

free(FreeMem[1]);

free(FreeMem[2]);

}

/*****************************************************************************

* Flush full cache. Overkill..

*****************************************************************************/

void FlushDrainFullCacheDMA(){



int i;

unsigned int *clean_addr= (unsigned int*)0xa1080000;

for(i=0; i<(1024*2);i++){

_Allocate_D_Cache_Line(clean_addr);

clean_addr += 8;

}

_Invalidate_D_Cache;

}

/*****************************************************************************

* Debug: prints all unmarked Frames in a chain. To debug it is helpful to

* record sequential index in Frame tid

*****************************************************************************/

void printChannelChain(int channel){

struct Frame_DMA *tail;

tail = ChainsDMA.Channel[channel].Tail;

printf("----------------------------------------------------------------------------------------------\n");

while(1){

printf("Chain Listing : Index(%04d) Thread(%02d) Channel(%02d)Adr(0x%08X)->nda(0x%08X)\n",tail->tid, tail->pid, channel, (unsignedint)tail,(unsigned int)tail->nda );

if(tail->nda == NULL){

printf("----------------------------------------------------------------------------------------------\n");

break;

}

tail=tail->nda;

}

}



C.7 80312_DMA.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _80312_DMA_H

#define _80312_DMA_H




/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

/* FIQ1 Interrupt Status Registerp2-12*/

#define FIQ1ISR_80312 (volatile unsigned int *) 0x00001708

/* IRQISR p2-15*/

#define IRQISR_80312 (volatile unsigned int *) 0x00001700

/* Primary ATU Status Registerp5-64*/

/* Master Abort */

#define PATUSR_80312 (volatile unsigned int *) 0x00001206

/* Channel Control Register */

#define CCR_0_80312 (volatile unsigned int *) 0x00001400



/* Channel Status Register */

#define CSR_0_80312 (volatile short *) 0x00001404



/* Next Descriptor Address Register*/

#define NDAR_0_80312 (volatile unsigned int *) 0x00001410



/* Descriptor Address Register*/

#define DAR_0_80312 (volatile unsigned int *) 0x0000140c



/* Byte Count Register */

#define BCR_0_80312 (volatile unsigned int *) 0x00001420

#define BCR_1_80312 (volatile unsigned int *) 0x00001460

#define BCR_2_80312 (volatile unsigned int *) 0x000014a0

/* PCI Address Register */

#define PADR_0_80312 (volatile unsigned int *) 0x00001414

#define PADR_1_80312 (volatile unsigned int *) 0x00001454

#define PARD_2_80312 (volatile unsigned int *) 0x00001494



/* PCI Upper Address Register */

#define PUADR_0_80312 (volatile unsigned int *) 0x00001418

#define PUADR_1_80312 (volatile unsigned int *) 0x00001458

#define PUADR_2_80312 (volatile unsigned int *) 0x0 0001498

/* Intel 80200 Processor Local Address Register */

#define LADR_0_80312 (volatile unsigned int *) 0x0000141c



/* Descriptor Control Register*/

#define DCR_0_80312 (volatile unsigned int *) 0x00001424

#define DCR_1_80312 (volatile unsigned int *) 0x00001464

#define DCR_2_80312 (volatile unsigned int *) 0x000014a4


#define CHAIN_RESUME_CCR_80312 0x00000002

#define CHANNEL_ENABLE_CCR_80312 0x00000001

#endif



C.8 80310_fiq_irq.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _80310_FIQ_IRQ_H

#define _80310_FIQ_IRQ_H




/*-----------------------------------------------------------------------------

**

** L I T E R A L S

**

**---------------------------------------------------------------------------*/

#define IRQVECTOR (volatile unsigned int *) 0x00000038 /* FIQ vector@0x18 calls 0x38 */

#define FIQVECTOR (volatile unsigned int *) 0x0000003c /* IRQ vector@0x18 calls 0x38 */

#define ABORTVECTOR (volatile unsigned int *) 0x00000030

#define DMA_CHANNEL_0_ERROR 0x00000020



#define DMA_CHANNEL_0_INTERRUPT_PENDING 0x00000001



/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

typedef void (*ISR_SERVICE)(void);

/*-----------------------------------------------------------------------------

**

** M A C R O S

**

**---------------------------------------------------------------------------*/

/*****************************************************************************

* Macro: Save and restore registers inside exception handler

*****************************************************************************/

#define ISR_PROLOGasm volatile("stmfdsp!, {r0-r6,ip,lr}")

#define ISR_EPILOGasm volatile("ldmfd sp!,{r0-r6,ip,lr}\n\t" \

"subs pc, lr, #4")



/*****************************************************************************

* Macro: Restore registers and jump to original vector address

*****************************************************************************/

#define EXCEPTION_CHAIN(oldVec) \

asm volatile("stmfd sp!, {%0}; \n\t" \

"ldmfd sp!, {r0, r1, r2, r3, r4, r5, r6, ip, lr,pc}; \n\t" \

: /* Output list */ \

: "r" (oldVec) /* Input list */ \

/* Clobber list */);

/*****************************************************************************

* Macro: Read Stack pointer. Call in mode state to get register access

*****************************************************************************/

#define _Read_SP \

({ REGISTER unsigned _val_; \

asm volatile("mov %0,r13; \n\t" : "=r" (_val_)); \

_val_; \

})

/*****************************************************************************

* Macro: Load new stack pointer value

*****************************************************************************/

#define INIT_ABORT_STACK(address) asm volatile("mov r0, #0; \n\t" \

"movsp, %0; \n\t" \

: \

:"r" (address) \

)

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

/* Private*/

void intHandlerAttachDMA(void (*irq)(void),void (*fiq)(void),void(*abrt)(void));

void intHandlerDetachDMA();



void irqHandlerDMA(void)__attribute__ ((__naked__));

void fiqHandlerDMA(void)__attribute__ ((__naked__));

void abrtHandlerDMA(void)__attribute__ ((interrupt ("ABORT")));

void intHandlerABRTDMA();

void (*irq)(void);/* Pointer to a function. */

void (*fiq)(void);/* Pointer to a function. */

void (*abrt)(void);/* Pointer to a function. */

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

extern ISR_SERVICE next_irq_service;

extern ISR_SERVICE next_fiq_service;

extern ISR_SERVICE next_abrt_service;

#endif



C.9 80310_fiq_irq.c

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

/*-----------------------------------------------------------------------------

**


**



**---------------------------------------------------------------------------*/

#include "80310_fiq_irq.h"

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

ISR_SERVICE * irqval;

ISR_SERVICE * fiqval;

ISR_SERVICE * abrtval;

ISR_SERVICE next_irq_service;

ISR_SERVICE next_fiq_service;

ISR_SERVICE next_abrt_service;

char abortstack[1024]__attribute__ ((section("STACK")))= {0};

struct Frame_DMA * x;

/*-----------------------------------------------------------------------------

**

** I N T E R R U P T H A N D L I N G

**

**---------------------------------------------------------------------------*/

/* Note: All handlers check status bit to determine if channel and specific

* interrupt have occured. Then using the DMA Controller DAR, get pointer

* to Frame being executed, post DMA Controller CSR value to Frame and then

* clean interrupt at the source by writing 1's to CSR register to clear

* interrupt.

*/

/*****************************************************************************

* DMA Interrupt Pending Handler. Each Channel sets different bit in the

* FIQ1 Interrupt Status Register.

*****************************************************************************/

void irqHandlerDMA(){

ISR_PROLOG;

if( *FIQ1ISR_80312 & DMA_CHANNEL_0_INTERRUPT_PENDING){

x = (struct Frame_DMA*)*DAR_0_80312;/* Load csr to descriptor */



x->csr = (short)*CSR_0_80312;/* Load csr to descriptor */

*CSR_0_80312=0xffff; /* Clear csr */

_WaitForNoIRQ();

}

else if(*FIQ1ISR_80312 & DMA_CHANNEL_1_INTERRUPT_PENDING){




_WaitForNoIRQ();

}

else if(*FIQ1ISR_80312 & DMA_CHANNEL_2_INTERRUPT_PENDING){




_WaitForNoIRQ();

}

else{

/* Call the redboot interupt handler */

/* GoTo "OldVectorValue" stored in intHandlerAttach() */

EXCEPTION_CHAIN(next_irq_service);

}

ISR_EPILOG;

}

/*****************************************************************************

* DMA Error handling. WARNING: this is a untested handler

*****************************************************************************/

void fiqHandlerDMA(){

ISR_PROLOG;

if( *IRQISR_80312 & DMA_CHANNEL_0_ERROR){




_WaitForNoFIQ();

}

else if(*IRQISR_80312 & DMA_CHANNEL_1_ERROR){






_WaitForNoFIQ();

}

else if(*IRQISR_80312 & 0x00000080){




_WaitForNoFIQ();

}

else{

/* Call the redboot interupt handler */

/* GoTo "OldVectorValue" stored in intHandlerAttach() */

EXCEPTION_CHAIN(next_fiq_service);

}

ISR_EPILOG;

}

/*****************************************************************************

* ABRT exception handler. WARNING: This is a incomplete untested handler

*****************************************************************************/

void abrtHandlerDMA(){

/* ISR_PROLOG; */

if( *IRQISR_80312 & DMA_CHANNEL_0_ERROR){



*CSR_0_80312=0xffff;

_WaitForNoFIQ();

_WaitForNoIRQ();

}

else if(*IRQISR_80312 & DMA_CHANNEL_1_ERROR){




_WaitForNoFIQ();



_WaitForNoIRQ();

}

else if (*IRQISR_80312 & DMA_CHANNEL_2_ERROR){



*CSR_2_80312=0xffff;

_WaitForNoFIQ();

_WaitForNoIRQ();

}

/* ISR_EPILOG;*/

}

/*****************************************************************************

* Attach (chain) IRQ, FIQ and ABRT exception handlers

*****************************************************************************/

void intHandlerAttachDMA(ISR_SERVICE irq, ISR_SERVICE fiq,ISR_SERVICEabrt){

irqval = (ISR_SERVICE*)IRQVECTOR;/* IRQ vector @0x18 calls 0x38 */

next_irq_service=*irqval;/* Save IRQ value*/

*irqval = irq; /* Record new vector value*/

fiqval = (ISR_SERVICE*)FIQVECTOR;/* FIQ vector @0x1c calls 0x3c */

next_fiq_service=*fiqval;/* Save FIQ value*/

*fiqval = fiq; /* Record new vector value*/

abrtval = (ISR_SERVICE*)ABORTVECTOR;/* FIQ vector @0x1c calls 0x3c */

next_abrt_service=*abrtval;/* Save FIQ value*/

*abrtval= abrt;

intHandlerABRTDMA();

}

/*****************************************************************************

* Set up stack pointer for ABORT handler

*****************************************************************************/

void intHandlerABRTDMA(){

unsigned int cpsr;

cpsr = _Read_CPSR;



_Write_MODE(0xd7);/* Create individual #defines for each processor setting. */

INIT_ABORT_STACK(abortstack + sizeof(abortstack));

/* Read mode and rewrite to restore value */

/* Assume forward decending stack movmfd */

/* Make sure inital state return */

_Write_CPSR(cpsr);

}

/*****************************************************************************

* Restore original addresses to Exception Vector

*****************************************************************************/

void intHandlerDetachDMA(){

*IRQVECTOR = (unsigned int)next_irq_service;

*FIQVECTOR = (unsigned int)next_fiq_service;

*ABORTVECTOR= (unsigned int)next_abrt_service;

}



C.10 dmalibHeaders.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _DMALIBHEADERS_H

#define _DMALIBHEADERS_H

#include <stdio.h>

#include <stdlib.h>



#include <stdarg.h>

#include "userDefsDMALib.h"

#include "core.h"

#include "liberror.h"

#include "80310_ThreadDMA.h"

#include "80310_fiq_irq.h"

#include "80312_DMA.h"

#include "80310_Global.h"

#endif

Intel® 80310 I/O Processor Chipset DMA Support LibraryTestbench Source Code


Appendix D Testbench Source Code

D.1 makefile for Testbench

#/******************************************************************************

# *

# * Copyright (c) 1993, 1994 Intel Corporation. All rights reserved.

# *

# *

# * Intel hereby grants you permission to copy, modify, and distribute this

# * software and its documentation. Intel grants this permission provided

# * that the above copyright notice appears in all copies and that both the

# * copyright notice and this permission notice appear in supporting

# * documentation. In addition, Intel grants this permission provided that

# * you prominently mark as not part of the original any modifications made

# * to this software or documentation, and that the name of Intel

# * Corporation not be used in advertising or publicity pertaining to the

# * software or the documentation without specific, written prior

# * permission.

# *

# * Intel provides this AS IS, WITHOUT ANY WARRANTY, INCLUDING THE WARRANTY

# * OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, and makes no

# * guarantee or representations regarding the use of, or the results of the

# * use of, the software and documentation in terms of correctness,

# * accuracy, reliability, currentness, or otherwise, and you rely on the

# * software, documentation, and results solely at your own risk.

# *

# **************************************************************************/

#/* */

#/* History: */

#/* 11Nov01 LGS Initial Release */

#/* */

#/****************************************************************************/

#****************************************************************************

# Use nmake file for GNUPro XScale toolchain *



#****************************************************************************

OBJS_SLAVE = s80310_main.o 80310_TestBench.o 80312_ATU.o 80310_timer.o dmalibops

OBJS_MASTER= m80310_main.o 80310_TestBench.o 80312_ATU.o 80310_timer.o dmalibops

CC = xscale-elf-gcc

LD = xscale-elf-ld

OBJ = xscale-elf-objdump

SPECS = iq80310.specs

DB = -g

# for optimization try -O1,-O2 and -O3 to see which run fastest

OPT = -O0

.SUFFIXES: .o .c .s

LIST = -Wa,-alhd=$*.lst, -fverbose-asm

MASTERCFLAGS = $(DB) $(OPT) -Wall -specs=$(SPECS) -mcpu=xscale -DMASTER$(LIST)

SLAVECFLAGS = $(DB) $(OPT) -Wall -specs=$(SPECS) -mcpu=xscale

LDFLAGS = -specs=$(SPECS)

CMAP = -Wl,--cref,-Map,$*.map

all : master.elf slave.elf

master.elf : $(OBJS_MASTER)

$(CC) $(LDFLAGS) $(CMAP) -o master.elf $(OBJS_MASTER)

m80310_main.o: 80310_main.c

$(CC) $(MASTERCFLAGS) $(CMAP) -c -o m80310_main.o 80310_main.c

80312_ATU.o: 80312_ATU.c

$(CC) $(MASTERCFLAGS) $(CMAP) -c -o 80312_ATU.o 80312_ATU.c

80310_timer.o: 80310_timer.c

$(CC) $(MASTERCFLAGS) $(CMAP) -c -o 80310_timer.o 80310_timer.c

80310_TestBench.o: 80310_TestBench.c

$(CC) $(MASTERCFLAGS) $(CMAP) -c -o 80310_TestBench.o 80310_TestBench.c

#----------------------------------------------------------------------

slave.elf : $(OBJS_SLAVE)

$(CC) $(LDFLAGS) $(CMAP) -o slave.elf $(OBJS_SLAVE)



s80310_main.o: 80310_main.c

$(CC) $(SLAVEFLAGS) $(CMAP) -c -o s80310_main.o 80310_main.c

clean:

rm *.o

rm *.elf

rm *.lst

rm *.out



D.2 datatypesDMALib.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _DATATYPESDMALIB_H

#define _DATATYPESDMALIB_H

#undef TRUE



#define TRUE 1

#undef FALSE

#define FALSE 0

typedef int Bool;





/* Channel Status Register */




struct Frame_DMA{


void * pad; /* Source Address (Lower)*/

void * puad; /* Source Address (Upper)*/

void * lad; /* Destination Address*/


unsigned int dc; /* Descriptor Control*/

short pid; /* pid */

short tid; /* tid */

short csr; /* CSR value */

short mark; /* If != 0 then executed*/

};

/* Container designed to fit one cacheline (32 bytes).*/

struct Queue_DMA{

int CircQ_Front;

int CircQ_Length;

int CircQ_Limit;



unsigned int * dar_ptr;





struct Frame_DMA * CircQ[3];

};

struct Stack_DMA{

int Stack_Length;

int Stack_Limit;


struct Frame_DMA * Stack[3];

};

/* Align on 8 word boundry. */

struct Thread_DMA{

struct Frame_DMA Frame[12];

struct Stack_DMA FreeStack; /* Unissued descriptors. */

struct Queue_DMA Channel[3];/* Channel 0 ,1 & 2. */

void * toFreeMem;

};

extern struct Thread_DMA*InitThreadDMA(void * thread1);

extern void * TestMemAlloc();

extern inline Bool ExecuteDMA(int channel,struct Frame_DMA *frame ,structThread_DMA * thread1);

extern struct Thread_DMA*TerminateThreadDMA(struct Thread_DMA* thread1);

extern Bool GlobalDMAInit();

extern void TerminateGlobalDMA();

extern struct Frame_DMA*MoveDescriptorToPostDMA(int channel, struct Thread_DMA*thread1);

extern int ChannelBusy(int channel,struct Thread_DMA*thread1);

#endif



D.3 userDefsDMA_TestBench.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _USERDEFSDMA_TESTBENCH_H

#define _USERDEFSDMA_TESTBENCH_H

#include "benchHeaders.h"



/*-----------------------------------------------------------------------------

**

** L I T E R A L S

**

**---------------------------------------------------------------------------*/

/* Ensure TESTPOOL size is greater than largest experiment size */

#define TESTPOOL 0x205/* Qty of test descriptors generated.*/

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

/*****************************************************************************

* struct exp{} represents a experiment. It is here for easy reference

* Change data structure with care.

*****************************************************************************/

typedef int Bool;

enum PCICOMMAND { MRM= 0xc, MWI= 0xf };

struct exp{

Bool exp_dma; /*01*//* TRUE=Execute DMA else time queues*/

/* Channel Related*/

int channel; /*02*/ /* Queue number */

/* Chain Descriptor Values */

unsigned intexp_pad; /*03*/ /* PCI Address[31:00] */

unsigned intexp_puad; /*04*/ /* PCI Address [64:32]*/

unsigned int exp_lad; /*05*//* Local Address */

unsigned intexp_bc; /*06*//* Byte count */

enum PCICOMMANDexp_dc; /*07*/ /* Descriptor control (MRM or MWI)*/

/* Test data: Writes only */

unsigned intexp_addr; /*08*//* Address on source */

unsigned intexp_value; /*09*//* Initial value */

/* OS Specific Data */

int exp_pid; /*10*/



int exp_tid; /*11*/

/* Testset characteristics*/

int exp_total_DMAs; /*12*//* Total number of DMAs inexperiment.*/

int exp_chain_size; /*13*//* Chain number of element inchain. */

int exp_buffer_size; /*14*//* Setup */

/* 80312 PMU */

unsigned intexp_monitor_mode; /*15*/

/* 80200 PMU */

unsigned intexp_event_pmn0; /*16*/

unsigned int exp_event_pmn1; /*17*/

/* Architecture Switches*/

int exp_cache_policy; /*18*/

/* Reporting--Output*/

int exp_error; /*--*/

structstats * exp_results; /*--*/

};

/*****************************************************************************

* The experiments are defined here. To add a new experiment:

* - Add a new EXPR(N)

* - Add the new EXPR(N) to #define EXP line

* - Make sure the quantity "exp_total_DMAs" < TESTPOOL defined above

* - See data structure struct exp{} above

*****************************************************************************/

#define EXPEXPER0,EXPER1,EXPER2,EXPER3,EXPER4

/* |-dma-||-Channel-||----------------Descriptor------------------||--Write test data--| |-----OS----||-----Testset Characteritics-----| |----PMUs----| |--Arch--|*/

/* 01 02 03(pad) 04(puad) 05(lad) 06(bc) 07(dc) 0809 10(pid)11(tid)12(tot) 13 14 15 16 17 18 19 20 */

#define EXPER0{ TRUE , 0x0,0x4a000100,0x00000000,0xa1000100,0x0200,0x00c,0xa1000100,0x00000001,0x0000,0x0000,0x0010,0x0020,0x0000,0x0000,0x0000,0x01,0x08,0x09,0x00000000}

#define EXPER1{ TRUE , 0x0,0x4a000110,0x00000000,0xa1000110,0x0010,0x00f,0xa1000100,0x00000001,0x0000,0x0000,0x0010,0x0020,0x0000,0x0000,0x0000,0x01,0x08,0x09,0x00000000}




#define EXPER3{ TRUE , 0x0,0x4a000110,0x00000000,0xa1000110,0x0010,0x00f,0xa1000100,0x00000001,0x0000,0x0000,0x0010,0x0020,0x0000,0x0000,0x0000,0x01,0x08,0x09,0x00000000}


#endif



D.4 80310_main.c

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/


/*****************************************************************************

* 80310_main.c used to create 2 images to be run on separate cards on same



* backplane. master.elf calls benchRun() which executes the testbench.

*****************************************************************************/

void StopHere(){}/* Function prototype for reference */

int main(void){

int run;

printf("Start 80310_main.c\n");

#ifdef MASTER

SetupMaster_ATU_80312();/* Set up ATU for master card */

run = benchRun();

if(run == -1){

printf("Bench Failed.\n");

}

#endif

#ifdef SLAVE

SetupSlave_ATU_80312();/* Set up ATU for slave */

printf("End of main(). After this while(1){}...\n");

while(1){}/* This is here to allow the DMA to complete before */

/* main exits. */

#endif

return 1;

}



D.5 TestBench.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _80310_TESTBENCH_H

#define _80310_TESTBENCH_H




/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

struct TestPool{ /* To create test bench only */

struct Frame_DMA Frame[TESTPOOL];

};

struct run{

struct Thread_DMA*dma;

int randDMA;

int randChannel;

};

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

/* Workbench */

void benchInit();

int benchRun();

void ReportDMAPool(int channel);

unsigned int createSourceTestData(unsigned int addr, unsigned intvalue, unsigned int size, int num_desc);

void createSourceDescriptors(unsigned int pad,unsigned intlad,unsigned int bc,unsigned int dc, int num_desc);

void QueueTester(int add, int delete, int channel);

void CleanupAfterExp(int c, ...);

Bool testStub(Bool dma, /* With/without DMA*/

int channel, /* CD: Channel number */

unsigned int pad, /* CD: PCI Address*/

unsigned int lad, /* CD: Local Address */

unsigned int bc, /* CD: Byte Count */

unsigned int dc, /* CD: Descriptor Cntrl*/



unsigned int addr, /* Test data: location*/

unsigned int value, /* Test data: value*/

unsigned int size); /* Test data: size*/

void * buildDescriptor(int byte_count,

unsigned int value_written,

void * loc_addr,

void * PCI_addr,

unsigned intdc);

void writeTestData(void * loc_addr,unsigned intvalue_written, int word_count);

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

extern struct TestPool * TestDescriptors;/* Creation of descriptors.*/

extern int totalExp; /* Total # of experiments.*/

extern struct exp Experiments[];

extern int bencherror;

#endif



D.6 TestBench.c

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

/*-----------------------------------------------------------------------------

**


**



**---------------------------------------------------------------------------*/

#include "80310_TestBench.h"

/*-----------------------------------------------------------------------------

**

** G L O B A L I N S T A N I T I O N S

**

**---------------------------------------------------------------------------*/

struct TestPool * TestDescriptors;/* Creation of descriptors. */

int totalExp; /* Total # of experiments.*/

int bencherror;

/**********************************************************************************************************************************************************************/

/**/

/* User Defined - User Defined - User Defined - User Defined - User Defined - UserDefined - User Defined - User Defined - User Defined - User Defined - User Defined*/

/**/

/**********************************************************************************************************************************************************************/

struct exp Experiments[] = {

EXP

};

/*-----------------------------------------------------------------------------

**

** T E S T I N G S T U B S

**

**---------------------------------------------------------------------------*/

void benchInit(){

TestDescriptors = (struct TestPool *)((( unsigned int)malloc(sizeof(structTestPool) +0x20) & 0xffffffe0)+0x20);

totalExp= sizeof(Experiments)/sizeof(struct exp);

}

int benchRun(){

int index, /* Loop Counter */



currentExp; /* Current Experiment */

unsigned int data;

struct run randomRun;

struct Frame_DMA*x1;

struct stats * performance; /* Current Runs Performance*/

/* Four threads are declared to simulate multi-threading*/

struct Thread_DMA *dma0;




benchInit();

for(currentExp = 0; currentExp < totalExp; currentExp++){/*Experiment counter*/

printf("NEXT Experiment\n");

GlobalDMAInit(); /*Initialize globals*/

dma0= (struct Thread_DMA *)InitThreadDMA(NULL);

dma1= (struct Thread_DMA *)InitThreadDMA( (void*)TestMemAlloc() );



/* For writes: write source data to be transferred */

/* Quantity to be changed to exp_discrete_DMAs */

data = createSourceTestData(Experiments[currentExp].exp_addr,

Experiments[currentExp].exp_value,

Experiments[currentExp].exp_bc,

Experiments[currentExp].exp_total_DMAs);

/* Create descriptors, this needs to be changed*/

createSourceDescriptors(Experiments[currentExp].exp_pad,

Experiments[currentExp].exp_lad,

Experiments[currentExp].exp_bc,

Experiments[currentExp].exp_dc,

Experiments[currentExp].exp_total_DMAs);

/* Start timer, modes need to be defined and added to table*/

performance = timerStart_80200_80312(currentExp



,Event_0x08_80200,Event_0x09_80200,Event_mode1_80312);

for(index=0; index< Experiments[currentExp].exp_total_DMAs; index++){ /*Build chain */

randomRun.randChannel=rand() % 0x2; /* Enter 0x2 or 0x3 for 2 or 3channels */

randomRun.randDMA=rand() % 4; /* Number of threads running */

switch(randomRun.randDMA){

case 0: randomRun.dma = (struct Thread_DMA *)dma0; break;




default:

printf("Switch statement failed.\n");

return -1;

}

x1 = (structFrame_DMA*)MoveDescriptorToPostDMA((int)randomRun.randChannel,(structThread_DMA*)randomRun.dma);

if(x1 == NULL){

#if BENCH_DEBUG

bencherror = CLEAN_FAILED_NO_FREE_DESCRIPTORS;

#endif

return -1;

}

x1->pad = TestDescriptors->Frame[index].pad;

x1->puad= TestDescriptors->Frame[index].puad;

x1->lad = TestDescriptors->Frame[index].lad;

x1->bc = TestDescriptors->Frame[index].bc;

x1->dc = TestDescriptors->Frame[index].dc;

x1->tid = (short)index; /* Sequential index for tracking */

x1->pid = (short)randomRun.randDMA;

/* Setting "interrupt enable" inside descriptor */

/* if(mod == 0x0){ */

if(1){

x1->dc |= 0x10;

}



ExecuteDMA(randomRun.randChannel,x1,(struct Thread_DMA*)randomRun.dma);

while(ChannelBusy(randomRun.randChannel,(structThread_DMA*)randomRun.dma)){}

printf("Index(0x%04X) CSR(0x%04X) \n",x1->tid,x1->csr);

/*

printf("X1 Address(0x%08X) CSR(0x%04X) Th(%d) Ch(%d) i(%d) dma0(%d)dma1(%d) dma2(%d) dma3(%d)\n",x1

,x1->csr

,randomRun.randDMA

,randomRun.randChannel

,index

,dma0->FreeStack.DMAChain_Length



,dma3->FreeStack.DMAChain_Length);

*/

/*

while(CHANNEL_BUSY(randomRun.randChannel,(structThread_DMA*)randomRun.dma) ){}

x1->csr=0x0;

*/

}/* Build Chain */

/************************************************************************/

/* This while() loops continue until transfers completes. This is */

/* determined by waiting until channel is not busy*/

/************************************************************************/

while(ChannelBusy(0x0,(struct Thread_DMA*)randomRun.dma)){}



timerFinish_80200_80312(Event_0x08_80200,Event_0x09_80200,Event_mode1_80312); /*Record timing information*/



Experiments[currentExp].exp_results = performance;

/* Print results, open console to view output*/

print_80200_80312(Experiments[currentExp].exp_results,currentExp);

CleanupAfterExp(4,dma0,dma1,dma2,dma3);

printf("After Cleanup.\n");

/* break; */

}/* New Experiment */

printf("The End. After this while(1){}\n");

return TRUE;

}

/*****************************************************************************

* Calls TerminateThreadDMA() for each Thread to deallocate thread memory

* followed by TerminateGlobal() to detach Exception handlers and deallocate

* global memory.

*****************************************************************************/

voidCleanupAfterExp(int c, ...){

struct Thread_DMA* dma_temp;

int i;

va_list ap;

va_start(ap,c);

*CCR_0_80312 &= 0xfffffffe; /* Disable DMA Channel */



for(i=0; i<c; i++){

dma_temp = va_arg(ap,struct Thread_DMA* );

dma_temp = TerminateThreadDMA(dma_temp);

}

TerminateGlobalDMA();

}

/*****************************************************************************

* Iterates writes of test data to source card by calling writeTestData()

*****************************************************************************/



unsigned intcreateSourceTestData(unsigned int addr,

unsigned int value,

unsigned int num_bytes,

int num_desc){

int i;

/* Write out Test data */

for(i=0; i< num_desc; i++){

writeTestData((void*)addr,value,num_bytes/4);

/* addr += 0x10; */

addr += num_bytes;

value++;

}

return addr;

}

/*****************************************************************************

* Writes value to memory locations to provide test data

*****************************************************************************/

void writeTestData(void * loc_addr,unsigned int value_written, int word_count){

int i;

unsigned int * temp1;

temp1 = (void *)loc_addr;

/* Create data in sender */

for (i=0; i<word_count; i++){

*temp1 = value_written;

temp1 = temp1++;

}

}

/*****************************************************************************

* Loads values to test descriptors to be executed by DMA engine in testbench

*****************************************************************************/

void createSourceDescriptors(unsigned int pad,

unsigned int lad,

unsigned int bc,

unsigned int dc,



int num_desc){

int i;

/* Create data structures */

for(i=0; i< (num_desc); i++){

TestDescriptors->Frame[i].nda=0;

TestDescriptors->Frame[i].pad= (void*)pad; /* PCI address*/

TestDescriptors->Frame[i].puad=0;

TestDescriptors->Frame[i].lad=(void*)lad; /* Local address */

TestDescriptors->Frame[i].bc=bc;

TestDescriptors->Frame[i].dc=dc;

pad += bc;

lad += bc;

}

TestDescriptors->Frame[i-1].dc|=0x010;

}



D.7 80310_PMUs.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _80310_PMUS_H

#define _80310_PMUS_H




/*****************************************************************************

* PMU related #defines.

*****************************************************************************/

/****************************************************************************/

/* 80200 80200 80200 80200 80200 80200 80200 80200 80200 80200 80200 80200*/

/****************************************************************************/

#define PMCR_EVENT0_0X08_80200 0x00800000

#define PMCR_EVENT1_0X11_80200 0x00011000

#define PMCR_OVRFLW_FLAG_80200 0x00000700

#define PMCR_CLOCK_RESET_80200 0x00000004

#define PMCR_PERF_RESET_80200 0x00000002

#define PMCR_CNTRS_ENABLE_ALL_80200 0x00000001

#define PMCR_INTR_ENABLE_80200 0x00000070

#define PMCR_EVENTCOUNT1_MSK_80200 0xf00fffff

#define PMCR_EVENTCOUNT2_MSK_80200 0xfff00fff

#define PMCR_OVRFLWINT_FLAGS_MSK_80200 0xfffffcff

#define PMCR_INT_ENABLE_MSK_80200 0xffffff8f

#define PMCR_CC_DIV_MSK_80200 0xfffffff7

#define PMCR_CC_RESET_MSK_80200 0xfffffffb

#define PMCR_PC_RESET_MSK_80200 0xfffffffd

#define PMCR_CNTR_ENABLE_MSK_80200 0xfffffffe

/****************************************************************************/

/* 80312 80312 80312 80312 80312 80312 80312 80312 80312 80312 80312 80312 */

/****************************************************************************/

/*Registers Memory Map */

/* Global Timer Mode Regiser*/

#define GTMR_80312 (unsigned int *) 0x00001100

/* Event Select Register*/

#define ESR_80312 (unsigned int *) 0x00001104

/* Event Monitoring Interrupt Status Register*/

#define EMISR_80312 (unsigned int *) 0x00001108

/* Global Time Stamp Register*/

#define GTSR_80312 (unsigned int *) 0x00001110



/* Programmable Event Counter Registers*/

#define PECR1_80312 (volatile unsigned int *) 0x00001114


#define PECR3_80312 (volatile unsigned int *) 0x0000111c













/* Bit Definitions */

#define ESR_MODE_0_80312 0x00000000








#define E SR_INTERRUPT_ENABLE_80312 0x00010000

#endif



D.8 80310_timer.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _80310_TIMER_H

#define _80310_TIMER_H




/*-----------------------------------------------------------------------------

**

** # D E F I N E S F O R D P R I N T F s

**

**---------------------------------------------------------------------------*/

/*****************************************************************************

* dprintfs referenced in this release. Used to print performance numbers to

* Excel spreadsheet.

*****************************************************************************/

#define EXP1 XXEXP1XX

#define dprintf3(expr1,expr2,expr3)printf(" \"%s\",\"%s\",\"%s\"",expr1,expr2,expr3);

#define dprintf7( expr1,expr2,expr3,expr4,expr5,expr6,expr7) printf(" \"%s\",\"%s\", \"%s\", \"%s\", \"%s\", \"%s\",\"%s\"","expr1","expr2","expr3","expr4","expr5","expr6","expr7");

#define dprintf8( expr1,expr2,expr3,expr4,expr5,expr6,expr7,expr8) printf("\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",\"%s\"","expr1","expr2","expr3","expr4","expr5","expr6","expr7","expr8");

#definedprintf14(expr1,expr2,expr3,expr4,expr5,expr6,expr7,expr8,expr9,expr10,expr11,expr12,expr13,expr14)printf(",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\"",expr1,expr2,expr3,expr4,expr5,expr6,expr7,expr8,expr9,expr10,expr11,expr12,expr13,expr14);

#define dprintf37( expr01,expr02, \

expr03,expr04,expr05,expr06,expr07, \

expr08,expr09, \

expr10,expr11,expr12, \

expr13, \

expr14,expr15, \

expr16, \

expr17,expr18, \

expr19,expr20,expr21,expr22,expr23,expr24,expr25,expr26, \

expr27,expr28,expr29,expr30,expr31, \

expr32,expr33,expr34,expr35,expr36,expr37) \

printf("\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\",\"%s\"" \



,expr01,expr02,expr03,expr04,expr05,expr06,expr07,expr08,expr09,expr10,expr11,expr12 \

,expr13,expr14,expr15,expr16,expr17,expr18,expr19,expr20,expr21,expr22,expr23,expr24,expr25,expr26,expr27,expr28,expr29 \

,expr30,expr31,expr32,expr33,expr34,expr35,expr36,expr37);

/*-----------------------------------------------------------------------------

**

** L I T E R A L S

**

**---------------------------------------------------------------------------*/

/*****************************************************************************

* For 80200 PMU see 80200 Developer’s Manual Table 12-4

*****************************************************************************/

#define Event_0x00_80200 0x0










#define Event_0x0a_80200 0xa

#define Event_0x0b_80200 0xb

#define Event_0x0c_80200 0xc

#define Event_0x0d_80200 0xd










/*****************************************************************************

* For 80312 PMU see 80312 Developer’s Manual Table 11-6

*****************************************************************************/

#define Event_mode0_80312 0x0








/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

/*****************************************************************************

* 80312 PMU values: See 80312 Developer’s Manual Chapter 11

* These names map to register definitions in section 11.6

*****************************************************************************/

struct p80312{

unsigned int gtmr;

unsigned int esr;

unsigned int emisr;

unsigned int gtsr_start;

unsigned int gtsr_end;

unsigned int pecr1;

unsigned int pecr2;

unsigned int pecr3;

unsigned int pecr4;

unsigned int pecr5;

unsigned int pecr6;

unsigned int pecr7;

unsigned int pecr8;



unsigned int pecr9;

unsigned int pecr10;





};

/*****************************************************************************

* 80200 PMU values. See 80200 Developer’s Manual Chapter 12

* These names map to registers listed.

*****************************************************************************/

struct p80200{

unsigned int pmnc;

unsigned int ccnt_start;

unsigned int ccnt_end;

unsigned int pmn0;

unsigned int pmn1;

};

struct pmuCombined{

struct p80200 coy;

struct p80312 yav;

};

structstats{

int runNumber;

int currentExp;

unsigned int event0_80200; /* 80200 event0*/

unsigned int event1_80200; /* 80200 event 1*/

int mode_80312; /* 80200 PMU mode*/

struct pmuCombined c;

};

/*-----------------------------------------------------------------------------



**


**

**---------------------------------------------------------------------------*/

struct stats * timerStart_80200_80312(int currentExp,

unsigned int event0_80200,


int mode_80312);

struct stats *timerFinish_80200_80312(unsigned int event0_80200,


int mode_80312);

void printExl_80200_80312(struct stats * timeSummary, int currentExp);

void print_80200_80312(struct stats * timeSummary, int currentExp);

void printHeader_80200_80312();

void printData_80200_80312(struct stats * timeSummary, int currentExp);

/*-----------------------------------------------------------------------------

**


**

**---------------------------------------------------------------------------*/

extern struct stats *timeSummary;

#endif



D.9 80310_timer.c

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/


/*-----------------------------------------------------------------------------

**




**

**---------------------------------------------------------------------------*/

struct stats *timeSummary;

/*****************************************************************************

* Starts save control information, selects 80200 and 80312 modes and

* starts timers (See 80312_timer.h for document references)

*****************************************************************************/

struct stats * timerStart_80200_80312(int currentExp,



int mode_80312){

unsigned int set_pmnc=0x0;

unsigned int temp=0x0;

timeSummary= malloc(sizeof(struct stats));

/* Record control information*/

timeSummary->runNumber=0;

timeSummary->currentExp=currentExp;

timeSummary->event0_80200=event0_80200;

timeSummary->event1_80200=event1_80200;

timeSummary->mode_80312=mode_80312;

set_pmnc= ( PMCR_CLOCK_RESET_80200|

PMCR_CNTRS_ENABLE_ALL_80200|

PMCR_INTR_ENABLE_80200|

PMCR_OVRFLW_FLAG_80200 );

/* Set event0 */

switch(event0_80200){

case 0x0:set_pmnc = set_pmnc | ((temp = 0x00)<< 20);break;












case 0xa:set_pmnc = set_pmnc | ((temp = 0x0a)<< 20);break;

case 0xb:set_pmnc = set_pmnc | ((temp = 0x0b)<< 20);break;

case 0xc:set_pmnc = set_pmnc | ((temp = 0x0c)<< 20);break;

case 0xd:set_pmnc = set_pmnc | ((temp = 0x0d)<< 20);break;








default:

}

/* Set event1 */

switch(event1_80200){











case 0xa:set_pmnc = set_pmnc | ((temp = 0x0a)<< 12);break;

case 0xb:set_pmnc = set_pmnc | ((temp = 0x0b)<< 12);break;

case 0xc:set_pmnc = set_pmnc | ((temp = 0x0c)<< 12);break;

case 0xd:set_pmnc = set_pmnc | ((temp = 0x0d)<< 12);break;










default:

}

/****************************************************/

/* 80312: Set Mode */

/****************************************************/

/* Set Event Select Register (ESR)*/

switch(mode_80312){

case 1: temp=ESR_MODE_1_80312; break;







default:

}

/* Set interrupt enable */

temp = temp | 0x00010000;

/* Record Value*/

*ESR_80312=temp;

/****************************************************/

/* 80200: Data + Bus Request Full*/

/****************************************************/

_Write_PMNC( set_pmnc | 0x07 ); /*Set 80200 PMNC*/

/****************************************************/

/* Record clocks */

/****************************************************/

timeSummary->c.coy.ccnt_start = _Read_CCNT; /* 80200 clock*/

timeSummary->c.yav.gtsr_start = *GTSR_80312; /* 80312 clock*/

return timeSummary;



}

/*****************************************************************************

* Stops 80200 and 80312 PMU and records outputs

*****************************************************************************/

struct stats *timerFinish_80200_80312(unsigned int event0_80200,


int mode_80312){

/****************************************************/

/* Record results */

/****************************************************/

/* Record clocks */

timeSummary->c.yav.gtsr_end = *GTSR_80312; /*Global Time Stamp*/

timeSummary->c.coy.ccnt_end = _Read_CCNT; /* */

/* 80312 */

timeSummary->c.yav.esr= *ESR_80312 ; /* Event Mode*/

timeSummary->c.yav.emisr= *EMISR_80312; /* Interrupts*/

timeSummary->c.yav.pecr1= *PECR1_80312;

timeSummary->c.yav.pecr2=*PECR2_80312;




timeSummary->c.yav.pecr6= *PECR6_80312;









/* 80200 */

timeSummary->c.coy.pmnc=_Read_PMNC;/* PMNC */



timeSummary->c.coy.pmn0=_Read_PMN0;/* PMN0 */

timeSummary->c.coy.pmn1=_Read_PMN1;/* PMN1 */

return timeSummary;

}

/*****************************************************************************

* Prints out 80200 and 80312 timer information. **NOTE** Descriptions

* printed change based on modes.

*****************************************************************************/

void print_80200_80312(struct stats * timeSummary, int currentExp){

printf("*****************************************************\n");

printf("** Exp Input **\n");

printf("*****************************************************\n");

printf(" Exp DMAExecuted...........exp_dma.......(0x%08X)\n",Experiments[currentExp].exp_dma);

printf(" Exp QueueNumber...........exp_q_num.....(0x%08X)\n",Experiments[currentExp].channel);

printf("--------------- Chain Descriptors ------------------\n");

printf(" Exp PCI[31:00]............exp_pad.......(0x%08X)\n",Experiments[currentExp].exp_pad);

printf(" Exp PCI[64:32]............exp_puad......(0x%08X)\n",Experiments[currentExp].exp_puad);

printf(" Exp LocalAddress..........exp_lad.......(0x%08X)\n",Experiments[currentExp].exp_lad);

printf(" Exp ByteCount.............exp_bc........(0x%08X)\n",Experiments[currentExp].exp_bc);

printf(" Exp PCICommand............exp_dc........(0x%08X)\n",Experiments[currentExp].exp_dc);

printf("----------------- OS Specific -----------------------\n");

printf(" ExpPID....................exp_pid.......(0x%08X)\n",Experiments[currentExp].exp_pid);

printf(" ExpTID....................exp_tid.......(0x%08X)\n",Experiments[currentExp].exp_tid);

printf("----------- Testset Characteristics------------------\n");

printf(" Exp.............exp_total_dmas..........(0x%08X)\n",Experiments[currentExp].exp_total_DMAs);

printf(" Exp.............exp_chain_size..........(0x%08X)\n",Experiments[currentExp].exp_chain_size);

printf(" Exp



.............exp_buffer_size.........(0x%08X)\n",Experiments[currentExp].exp_buffer_size);

printf("-------------------- PMUs ---------------------------\n");

printf(" Exp.............exp_monitor_mode........(0x%08X)\n",Experiments[currentExp].exp_monitor_mode);

printf(" Exp.............exp_event_pmn0..........(0x%08X)\n",Experiments[currentExp].exp_event_pmn0);

printf(" Exp.............exp_event_pmn1..........(0x%08X)\n",Experiments[currentExp].exp_event_pmn1);

printf("------------- Architecture Switches------------------\n");

printf(" Exp CachePolicy.exp_cache_policy........(0x%08X)\n",Experiments[currentExp].exp_cache_policy);

printf("*****************************************************\n");

printf("*****************************************************\n");

printf(" \n");

printf("Run.Number...............................(0x%08X)\n",timeSummary->runNumber);

printf("Experiment.Number........................(0x%08X)\n",timeSummary->currentExp);

printf(" \n");

printf("****80200********************************************\n");

printf(" 80200 ControlRegister....................(0x%08X)\n",timeSummary->c.coy.pmnc);

printf(" 80200 EventCounter1......................(0x%08X)\n",timeSummary->c.coy.pmnc &~PMCR_EVENTCOUNT1_MSK_80200);

printf(" 80200 EventCounter2......................(0x%08X)\n",timeSummary->c.coy.pmnc &~PMCR_EVENTCOUNT2_MSK_80200);

printf(" 80200 Overflow/InterruptFlags............(0x%08X)\n",timeSummary->c.coy.pmnc &~PMCR_OVRFLWINT_FLAGS_MSK_80200);

printf(" 80200 InterruptEnable....................(0x%08X)\n",timeSummary->c.coy.pmnc &~PMCR_INT_ENABLE_MSK_80200);

printf(" 80200 Clock CounterDivider...............(0x%08X)\n",timeSummary->c.coy.pmnc &~PMCR_CC_DIV_MSK_80200);

printf(" 80200 Clock CounterReset.................(0x%08X)\n",timeSummary->c.coy.pmnc &~PMCR_CC_RESET_MSK_80200);

printf(" 80200 Performance CounterReset...........(0x%08X)\n",timeSummary->c.coy.pmnc & ~PMCR_PC_RESET_MSK_80200);



printf(" 80200 CounterEnable......................(0x%08X)\n",timeSummary->c.coy.pmnc &~PMCR_CNTR_ENABLE_MSK_80200);

printf(" 80200 StartCount.........................(0x%08X)\n",timeSummary->c.coy.ccnt_start);

printf(" 80200 Endcount...........................(0x%08X)\n",timeSummary->c.coy.ccnt_end);

printf(" 80200PMN0................................(0x%08X)\n",timeSummary->c.coy.pmn0);

printf(" 80200PMN1................................(0x%08X)\n",timeSummary->c.coy.pmn1);

printf("-----------------------------------------------------\n");

printf("****80312********************************************\n");

printf("-----------------------------------------------------\n");

printf(" 80312 Event SelectRegister........ESR....(0x%08X)\n",timeSummary->c.yav.esr);

printf(" 80312Mode.........................ESR....(0x%08X)\n",timeSummary->c.yav.esr &0x00000003);

printf(" 80312 InterruptEnable.............ESR....(0x%08X)\n",timeSummary->c.yav.esr & 0x00010000);

printf(" 80312 InterruptStatus.............EMISR..(0x%08X)\n",timeSummary->c.yav.emisr);

printf(" 80312 Start Global TimeStamp......GTSR...(0x%08X)\n",timeSummary->c.yav.gtsr_start);

printf(" 80312 End Global TimeStamp......GTSR...(0x%08X)\n",timeSummary->c.yav.gtsr_end);

if(timeSummary->mode_80312 == 1){

printf(" 80312M1_PPCIBus_idle..............PECR1..(0x%08X)\n",timeSummary->c.yav.pecr1);

printf(" 80312M1_PPCIBus_busy..............PECR2..(0x%08X)\n",timeSummary->c.yav.pecr2);

printf(" 80312M1_bridge_acq................PECR3..(0x%08X)\n",timeSummary->c.yav.pecr3);

printf(" 80312M1_bridge_own................PECR4..(0x%08X)\n",timeSummary->c.yav.pecr4);

printf(" 80312M1_DMA0_acq..................PECR5..(0x%08X)\n",timeSummary->c.yav.pecr5);

printf(" 80312M1_DMA0_own..................PECR6..(0x%08X)\n",timeSummary->c.yav.pecr6);


printf(" 80312



M1_DMA1_own..................PECR8..(0x%08X)\n",timeSummary->c.yav.pecr8);

printf(" 80312M1_PATU_acq..................PECR9..(0x%08X)\n",timeSummary->c.yav.pecr9);

printf(" 80312M1_PATU_own..................PECR10.(0x%08X)\n",timeSummary->c.yav.pecr10);

printf(" 80312M1_DMA0_gnt..................PECR11.(0x%08X)\n",timeSummary->c.yav.pecr11);


printf(" 80312M1_PATU_gnt..................PECR13.(0x%08X)\n",timeSummary->c.yav.pecr13);

printf(" 80312M1_bridge_gnt................PECR14.(0x%08X)\n",timeSummary->c.yav.pecr14);

}

else if(timeSummary->mode_80312 == 2){

printf(" 80312M2_SPCIBus_idle..............PECR1..(0x%08X)\n",timeSummary->c.yav.pecr1);

printf(" 80312M2_SPCIBus_busy..............PECR2..(0x%08X)\n",timeSummary->c.yav.pecr2);

printf(" 80312M2_SATU_acq..................PECR3..(0x%08X)\n",timeSummary->c.yav.pecr3);

printf(" 80312M2_SATU_own..................PECR4..(0x%08X)\n",timeSummary->c.yav.pecr4);

printf(" 80312M2_bridge_acq................PECR5..(0x%08X)\n",timeSummary->c.yav.pecr5);

printf(" 80312M2_bridge_own................PECR6..(0x%08X)\n",timeSummary->c.yav.pecr6);



printf(" 80312M2_bridge_gnt................PECR9..(0x%08X)\n",timeSummary->c.yav.pecr9);

printf(" 80312M2_SATU_gnt..................PECR10.(0x%08X)\n",timeSummary->c.yav.pecr10);


printf(" 80312M2_PPCIBus_idle..............PECR12.(0x%08X)\n",timeSummary->c.yav.pecr12);

printf(" 80312M2_PPCIBus_busy..............PECR13.(0x%08X)\n",timeSummary->c.yav.pecr13);

printf(" 80312M2_IBus_busy.................PECR14.(0x%08X)\n",timeSummary->c.yav.pecr14);

}




printf(" 80312M3_SPCIbus_idle..............PECR1..(0x%08X)\n",timeSummary->c.yav.pecr1);

printf(" 80312M3_SPCIbus_busy..............PECR2..(0x%08X)\n",timeSummary->c.yav.pecr2);

printf(" 80312M3_SPCI_IOP_acq..............PECR3..(0x%08X)\n",timeSummary->c.yav.pecr3);

printf(" 80312M3_SPCI_IOP_own..............PECR4..(0x%08X)\n",timeSummary->c.yav.pecr4);

printf(" 80312M3_D0_acq....................PECR5..(0x%08X)\n",timeSummary->c.yav.pecr5);

printf(" 80312M3_D0_own....................PECR6..(0x%08X)\n",timeSummary->c.yav.pecr6);




printf(" 80312M3_D2_own....................PECR10.(0x%08X)\n",timeSummary->c.yav.pecr10);

printf(" 80312M3_SPCI_IOP_gnt..............PECR11.(0x%08X)\n",timeSummary->c.yav.pecr11);

printf(" 80312M3_D0_gnt....................PECR12.(0x%08X)\n",timeSummary->c.yav.pecr12);



}












printf(" 80312M4_D3_gnt....................PECR9..(0x%08X)\n",timeSummary->c.yav.pecr9);



printf(" 80312M4_SPCI_IOP_gnt..............PECR12.(0x%08X)\n",timeSummary->c.yav.pecr12);

printf(" 80312M4_SPCI_IOP_own..............PECR13.(0x%08X)\n",timeSummary->c.yav.pecr13);

printf(" 80312M4_SPCI_IOP_own..............PECR14.(0x%08X)\n",timeSummary->c.yav.pecr14);

}


printf(" 80312M5_IBus_idle.................PECR1..(0x%08X)\n",timeSummary->c.yav.pecr1);

printf(" 80312M5_IBus_busy.................PECR2..(0x%08X)\n",timeSummary->c.yav.pecr2);

printf(" 80312M5_AA_acq....................PECR3..(0x%08X)\n",timeSummary->c.yav.pecr3);

printf(" 80312M5_AA_own....................PECR4..(0x%08X)\n",timeSummary->c.yav.pecr4);






printf(" 80312M5_DMA2_own..................PECR10.(0x%08X)\n",timeSummary->c.yav.pecr10);

printf(" 80312M5_AA_gnt....................PECR11.(0x%08X)\n",timeSummary->c.yav.pecr11);




}


printf(" 80312



M6_core_acq..................PECR1..(0x%08X)\n",timeSummary->c.yav.pecr1);

printf(" 80312M6_core_own..................PECR2..(0x%08X)\n",timeSummary->c.yav.pecr2);

printf(" 80312M6_PATU_acq..................PECR3..(0x%08X)\n",timeSummary->c.yav.pecr3);

printf(" 80312M6_PATU_own..................PECR4..(0x%08X)\n",timeSummary->c.yav.pecr4);

printf(" 80312M6_SATU_acq..................PECR5..(0x%08X)\n",timeSummary->c.yav.pecr5);

printf(" 80312M6_SATU_own..................PECR6..(0x%08X)\n",timeSummary->c.yav.pecr6);

printf(" 80312M6_PBOFF_time................PECR7..(0x%08X)\n",timeSummary->c.yav.pecr7);

printf(" 80312M6_PBOFF_cnt.................PECR8..(0x%08X)\n",timeSummary->c.yav.pecr8);

printf(" 80312M6_SBOFF_time................PECR9..(0x%08X)\n",timeSummary->c.yav.pecr9);

printf(" 80312M6_SBOFF_cnt.................PECR10.(0x%08X)\n",timeSummary->c.yav.pecr10);

printf(" 80312M6_PATU_gnt..................PECR11.(0x%08X)\n",timeSummary->c.yav.pecr11);

printf(" 80312M6_SATU_gnt..................PECR12.(0x%08X)\n",timeSummary->c.yav.pecr12);

printf(" 80312M6_core_gnt..................PECR13.(0x%08X)\n",timeSummary->c.yav.pecr13);

printf(" 80312M6_ATU_retry.................PECR14.(0x%08X)\n",timeSummary->c.yav.pecr14);

}


printf(" 80312M7_IBus_idle.................PECR1..(0x%08X)\n",timeSummary->c.yav.pecr1);

printf(" 80312M7_IBus_busy.................PECR2..(0x%08X)\n",timeSummary->c.yav.pecr2);



printf(" 80312M7_SPCI_IOP_own..............PECR5..(0x%08X)\n",timeSummary->c.yav.pecr5);









printf(" 80312M7_PPCI_IOP_own..............PECR12.(0x%08X)\n",timeSummary->c.yav.pecr12);

printf(" 80312M7_PPCIbus_idle..............PECR13.(0x%08X)\n",timeSummary->c.yav.pecr13);

printf(" 80312M7_PPCIbus_busy..............PECR14.(0x%08X)\n",timeSummary->c.yav.pecr14);

}

else{

printf("Error in mode.\n");

}

}

/*****************************************************************************

* Working implementation not provided this release

* This file print the header for Excel or Access data sheets.

*

*****************************************************************************/

void printHeader_80200_80312(){

printf("XXEXP1XX");

dprintf37( "exp_dma","exp_channel",

"exp_pad","exp_puad","exp_lad","exp_bc","exp_dc",

"exp_pid","exp_tid",

"exp_total_DMAs","exp_chain_size","exp_buffer_size",

"exp_monitor_mode",

"exp_event_pmn0","exp_event_pmn1",

"exp_cache_policy",

"runNumber","currentExp",

"Control_reg","Evnt_Counter1","Evnt_Counter2","Ovrflow_Intr","Intr_Enable","Clock_Divider","Clock_Reset","Perf_Counter_Reset",

"Counter_Enable","Start_Counter","End_Count","PMN0","PMN1",

"esr","esr_mode","esr_int_enable","emisr","Start_GTSR","End_GTSR")

dprintf14("perc01","perc02","perc03","perc04","perc05","perc06","perc07","perc08","perc09","



perc10","perc11","perc12","perc13","perc14")

printf( "\n ");

}

void printData_80200_80312(struct stats * timeSummary, int currentExp){

printf("XXEXP1XX");

printf("%02d,",Experiments[currentExp].exp_dma); /* int*/

/* Chain Descriptor Values*/

printf("0x%08X,",Experiments[currentExp].channel);

printf("0x%08X,",Experiments[currentExp].exp_pad); /* string */

printf("0x%08X,",Experiments[currentExp].exp_puad); /* string*/

printf("0x%08X,",Experiments[currentExp].exp_lad); /* string*/

printf("%08d,",Experiments[currentExp].exp_bc);

printf("0x%08X,",Experiments[currentExp].exp_dc); /* string*/

/* OS Specific */

printf("0x%08X,",Experiments[currentExp].exp_pid); /* string*/

printf("0x%08X,",Experiments[currentExp].exp_tid); /* string*/

/* Testset Characteristics*/

printf("%08d,",Experiments[currentExp].exp_total_DMAs); /* int*/

printf("%08d,",Experiments[currentExp].exp_chain_size); /* int*/

printf("%08d,",Experiments[currentExp].exp_buffer_size); /* int*/

/* 80312 PMU */

printf("%08d,",Experiments[currentExp].exp_monitor_mode); /* int*/

/* 80200 PMU */

printf("%08d,",Experiments[currentExp].exp_event_pmn0); /* int*/

printf("%08d,",Experiments[currentExp].exp_event_pmn1); /* int*/

/* Achitectural Switches*/

printf("0x%08X,",Experiments[currentExp].exp_cache_policy); /* string*/

/* Run Information*/

printf("%08d,",timeSummary->runNumber); /* int*/

printf("%08d,",timeSummary->currentExp); /* int*/

/* ****80200******************************************** */

printf("0x%08X,",timeSummary->c.coy.pmnc); /* string*/

printf("0x%08X,",timeSummary->c.coy.pmnc & ~PMCR_EVENTCOUNT1_MSK_80200);



/* string*/

printf("0x%08X,",timeSummary->c.coy.pmnc & ~PMCR_EVENTCOUNT2_MSK_80200);/* string*/

printf("0x%08X,",timeSummary->c.coy.pmnc &~PMCR_OVRFLWINT_FLAGS_MSK_80200); /* string*/

printf("0x%08X,",timeSummary->c.coy.pmnc & ~PMCR_INT_ENABLE_MSK_80200); /*string*/

printf("0x%08X,",timeSummary->c.coy.pmnc & ~PMCR_CC_DIV_MSK_80200); /*string */

printf("0x%08X,",timeSummary->c.coy.pmnc & ~PMCR_CC_RESET_MSK_80200); /*string*/

printf("0x%08X,",timeSummary->c.coy.pmnc & ~PMCR_PC_RESET_MSK_80200); /*string*/

printf("0x%08X,",timeSummary->c.coy.pmnc & ~PMCR_CNTR_ENABLE_MSK_80200);/* string*/

printf("%08d,",timeSummary->c.coy.ccnt_start); /* int*/

printf("%08d,",timeSummary->c.coy.ccnt_end); /* int*/

printf("%08d,",timeSummary->c.coy.pmn0); /* int*/

printf("%08d,",timeSummary->c.coy.pmn1); /* int*/

/* ****80312******************************************** */

printf("0x%08X,",timeSummary->c.yav.esr); /* string*/

printf("0x%08X,",timeSummary->c.yav.esr & 0x00000003); /* string*/

printf("0x%08X,",timeSummary->c.yav.esr & 0x00010000); /* string*/

printf("0x%08X,",timeSummary->c.yav.emisr); /* string*/

printf("%08d,",timeSummary->c.yav.gtsr_start); /* int*/

printf("%08d,",timeSummary->c.yav.gtsr_end); /* int */

printf("%08d,",timeSummary->c.yav.pecr1); /* int*/















printf("%08d",timeSummary->c.yav.pecr14); /* int*/

printf("\n");

}



D.10 80310_ATU.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _80312ATU_H

#define _80312ATU_H




/*****************************************************************************

* ATU related memory map and literals

*****************************************************************************/

/*Memory map */

/* 5-63 Primary ATU Command Register*/

#define PATUCMD_ADDR (volatile unsigned int *) 0x00001204

/* 5-71Primary Inbound ATU Base Address Register*/

#define PIABAR_ADDR (volatile unsigned int *) 0x00001210

/* 5-81 Primary Inbound ATU Limit Register */

#define PIALR_ADDR (volatile unsigned int *) 0x00001240

/* 5-82 Primary Inbound ATU Translate Value Register*/

#define PIATVR_ADDR (volatile unsigned int *) 0x00001244

/* 5-86 Primary Outbound Memory Window Value Register*/

#define POMWVR_ADDR (volatile unsigned int *) 0x00001254

/* 5-98 ATU Configuration Register*/

#define ATUCR_ADDR (volatile unsigned int *) 0x00001288

/* Write to on Master */

#define WRITE_TOO_ADDR (volatile unsigned int *) 0x80100000

/* Read value from Slave */

#define READ_TEST_ADDR (volatile unsigned int *) 0xa1100000

/*Bit definitions************************************************/

/* Cards contain 32M of memory starting from 0xa000 0000*/

/* Base: 0xa000 0000, End: 0xa200 0000, Size: 0x0200 0000*/

/****************************************************************/

/* Master */

#define MASTER_PIABAR_VAL /* Base Address */0x2a000000

#define MASTER_POMWVR_VAL /* Window Value */0x4a000000

/* Slave*/

#define SLAVE_POMWVR_VAL /* Window Value*/ 0x2a000000

#define SLAVE_PIABAR_VAL /* Base Address*/ 0x4a000000

/* Both */

#define PIALR_VAL /* Limit */ 0xff800000



#define PIATVR_VAL /* Translate Value*/ 0xa1000000

#define ATUCR_VAL /* Configuration*/ 0x00000082

#define TEST_VAL 0xf0f0f0f0

#define ATUCLSR (volatile unsigned int * ) 0x120c

#define PATUCMD (volatile unsigned int * ) 0x1204

#define SATUCMD (volatile unsigned int * ) 0x1298


#define MEMORY_WRITE_AND_INVALIDATE_ENABLE 0x10

void SetupSlave_ATU_80312();

void SetupMaster_ATU_80312();

#endif



D.11 80310_ATU.c

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#include "80312_ATU.h"

/*****************************************************************************

* Setup ATU for slave



*****************************************************************************/

void SetupSlave_ATU_80312(){

unsigned int temp;

/* Set ATU Configuration Register (ATUCR) (5-98)-set bit:1*/

temp = 0x0;

temp = *ATUCR_ADDR;

temp = temp | ATUCR_VAL;

*ATUCR_ADDR= temp;

/* Set Window Value Register (POMWVR) (p 5-86)*/

temp = 0x0;

temp = *POMWVR_ADDR;

temp = temp & 0x0000000f;

temp = temp | SLAVE_POMWVR_VAL;

*POMWVR_ADDR= temp;

/* Set Base Register (PIABAR) (5-71)*/

temp = 0x0;

temp = *PIABAR_ADDR;


temp = temp | SLAVE_PIABAR_VAL;

*PIABAR_ADDR = temp;

/* Set Limit Register (PIALR) (5-81)*/

*PIALR_ADDR= PIALR_VAL;

/* Set Value Register (PIATVR) (5-82)*/

*PIATVR_ADDR= PIATVR_VAL;

*ATUCLSR = ATU_CACHELINE_SIZE_16DWORDS;



}

/*****************************************************************************

* Setup ATU for Master



*****************************************************************************/

void SetupMaster_ATU_80312(){

unsigned int temp;

/* Set ATU Configuration Register (ATUCR) (5-98)-set bit:1*/

temp = 0x0;

temp = *ATUCR_ADDR;

temp = temp | ATUCR_VAL;

*ATUCR_ADDR= temp;

/* Set Window Value Register (POMWVR) (p 5-86)*/

temp = 0x0;

temp = *POMWVR_ADDR;


temp = temp | MASTER_POMWVR_VAL;

*POMWVR_ADDR= temp;

/* Set Base Register (PIABAR) (5-71)*/

temp = 0x0;

temp = *PIABAR_ADDR;

temp = temp & 0x00000fff;

temp = temp | MASTER_PIABAR_VAL;

*PIABAR_ADDR = temp;

/* Set Limit Register (PIALR) (5-81)*/

*PIALR_ADDR= PIALR_VAL;

/* Set Value Register (PIATVR) (5-82)*/

*PIATVR_ADDR= PIATVR_VAL;

}



D.12 benchHeaders.h

/******************************************************************************

*


*

*










* permission.

*







*

**************************************************************************/

/* */

/* History: */


/* */

/****************************************************************************/

#ifndef _BENCHHEADERS_H

#define _BENCHHEADERS_H

#include <stdlib.h>



#include <stdio.h>

#include <stdarg.h>

#include "core.h"

#include "datatypesDMALib.h"

#include "userDefsDMA_TestBench.h"

#include "80312_ATU.h"

#include "80310_TestBench.h"

#include "80310_timer.h"

#include "80310_PMUs.h"

#endif