programming, intel performance, & efficiency architecture · 2018-01-29 · optimization notice...

IntelArchitecture

1

Rama MalladiIntel, Bangalore

Programming,Performance,& Efficiency

Copyright © 2014, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others.Optimization Notice

Legal Disclaimer & Optimization Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED “AS IS”. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO THIS INFORMATION INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.

Copyright © 2014, Intel Corporation. All rights reserved. Intel, Pentium, Xeon, Xeon Phi, Core, VTune, Cilk, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

Optimization Notice

Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

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Intel Technical Computing & HPC Solutions Portfolio

Intel®ClusterReady

Network& Fabric

Software& Services

ComputeProcessing

Systems& Boards

I/O & Storage

2015

SiPh

Intel®Omni-PathArchitecture

Intel®True ScaleFabric

NVM

Intel®EthernetNetworking

3


• The problem statement!

• Intel® Xeon® Processor Architecture Basics

• Intel® Xeon Phi™ (Knights Landing)

• Software Tools for Developers

• Summary

6

Agenda


Problem:Economical operation frequency of (CMOS) transistors is limited. No free lunch anymore!

Solution:More transistors allow more gates/logic on the same die space and power envelop, improving parallelism:

Thread level parallelism (TLP):Multi- and many-core

Data level parallelism (DLP):Wider vectors (SIMD)

Instruction level parallelism (ILP):Microarchitecture improvements, e.g.threading, superscalarity, …

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Parallel & Vector Execution


8


9

recap


How to determine if we got the best / peak performance?

• Run GEMM?

• LINPACK?

• STREAM bandwidth tests?

• Latency benchmarks?

• …

• Get theoretical peak possible for the code?

10

Roofline Analysis?


11

Roofline Analysis“paper-pen” exercise

float *A, *B, *C, d;

for(i=0; i<n; i++)

{

A[i] = B[i] + d * C[i];

}

The above code on Intel Xeon Phi is bound by:

• Compute?

• Bandwidth?






• Summary

12

Agenda


• 1978: 8086 and 8088 processors• 1982: Intel® 286 processor • 1985: Intel386™ processor• 1989: Intel486™ processor• 1993: Intel® Pentium®• 1995-1999: P6 family:

Intel Pentium Pro processor Intel Pentium II [Xeon] processor Intel Pentium III [Xeon] processor Intel Celeron® processor

• 2000-2006: Intel® Pentium® 4 processor• 2005: Intel® Pentium® processor Extreme Edition• 2001-2007: Intel® Xeon® processor• 2003-2006: Intel® Pentium® M processor• 2006/2007: Intel® Core™ Duo and Intel® Core™ Solo processors• 2006/2007: Intel® Core™2 processor• 2008: Intel® Atom™ processor and Intel® Core™ i7 processor family• 2010: Intel® Core™ processor family• 2011: Second generation Intel® Core™ processor family• 2012: Third generation Intel® Core™ processor family• 2013: Fourth generation Intel® Core™ processor family• 2013: Intel® Atom™ processor family based on Silvermont microarchitecture

13

HistoryIntel® 64 and IA-32 Architecture


Computation of instructions requires several stages:

1. Fetch:Read instruction (bytes) from memory

2. Decode:Translate instruction (bytes) to microarchitecture

3. Execute:Perform the operation with a functional unit

4. Memory:Load (read) or store (write) data, if required

5. Commit:Retire instruction and update micro-architectural state

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Processor Architecture BasicsPipeline

Front End Back End

Fetch Decode Execute CommitLoad or

Store

Instructions

MemoryRegisters


Impact of pipeline stalls can be reduced by:• Branch prediction• Superscalarity + multiple issue fetch & decode• Out of Order execution• Cache• Non-temporal stores• Prefetching• Line fill buffers• Load/Store buffers• Alignment• Simultaneous Multithreading (SMT)

Characteristics of the architecture that might require user action!

15

Processor Architecture BasicsReducing Impact of Pipeline Stalls


Cache-hierarchy:• For data and instructions• Usually inclusive caches• Races for resources• Can improve access speed• Cache-misses & cache-hits

Cache-line:• Always full 64 byte block• Minimal granularity of every load/store• Modifications invalidate entire cache-line (dirty bit)

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Processor Architecture BasicsCache-Hierarchy & Cache-Line

L2 Cache

L3 Cache

I DL1 Caches

Memory

Fe

tch

Lo

ad

or

Sto

re

De

cod

e

Ex

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Co

mm

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0x12340x5678

Instructions

…

Instructions

Instructions

Instructions

1: mov 0x1234, %rbx

2: mov 0x5678, %rcx

3: mov %rcx, 0x1234

4: …

5: …

6: …Instructions

65432

1

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0x1234

0x5678

0x5678

0x12340x5678

0x1234

0x1234

Cache-miss

Cache-miss

Cache-miss

Cache-miss

Cache-miss

Cache-miss

Cache-miss

Cache-miss

Cache-miss

Cache-miss

Cache-miss

Cache-hit

65432

1


From Intel® 64 and IA-32 Architectures Optimization Reference Manual:

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Processor Architecture BasicsExample: 4th Generation Intel® Core™

Fetch(Pre-Decode)I I-Queue

Decode & Dispatch

BPU

BTB

ROB, L/S

Exe[Int][FP]

DL2 Cache

Exe[Int]

Exe[Int][FP]

Exe[Int][FP] S

tore

Sto

re A

dd

ress

Lo

ad

&S

tore

Ad

dre

ss

Lo

ad

&S

tore

Ad

dre

s

LFB

SchedulePort 0 Port 1 Port 5 Port 6 Port 4 Port 2 Port 3 Port 7

https://www-ssl.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html


• Core:Processor core’s logic: Execution units Core caches (L1/L2) Buffers & registers …

• Uncore:All outside a processor core: Memory controller/channels (MC) and Intel® QuickPath Interconnect (QPI) L3 cache shared by all cores Type of memory Power management and clocking Optionally: Integrated graphics

Only uncore is differentiation within same processor family!18

Processor Architecture BasicsCore vs. Uncore

Processor

Co

re 1

Co

re2

Co

re n

QPIMCClock

&Power

L3 Cache

Gra

ph

ics

Core

Uncore

DDR3or

DDR4






• Summary

19

Agenda


21


Random Access Latency


AVX-512 Designed for HPC

Quadwordinteger

arithmetic

Including gather/scatter with D/Qword

indices

Math support

IEEE division and square root

DP transcendental

primitives

New transcendental

support instructions

New permutation primitives

Two source shuffles

Compress & Expand

Bit manipulation

Vector rotate

Universal ternary logical operation

New mask instructions

• Promotions of many AVX and AVX2 instructions to AVX-512

− 32-bit and 64-bit floating-point instructions from AVX

− Scalar and 512-bit

− 32-bit and 64-bit integer instructions from AVX2

• Many new instructions to speedup HPC workloads


Gather & Scatter

VMOVDQU64 zmm1, Q[rsi]

VMOVDQU64 zmm2, R[rsi]

VGATHERQQ zmm0 {k2}, [rax+zmm1*8]

VSCATTERQQ [rax+zmm2*8] {k3}, zmm0

D/Q/SP/DP element typesD/Q indicesInstruction can partially execute

k-reg Mask used as completion mask

for(j=0, i=0; i<N; i++)

{

B[R[i]] = A[Q[i]];

}

Q RA B






• Summary

35

Agenda


Petascale Today

Intel® Cluster Studio XE

36


Intel® Cluster Studio XE 2018

37


38

Leading Supporter of

Industry StandardsC++, C, Fortran, OpenMP,

MPI, TBB

More Efficient

Software Development

Programmer Productivity

Preservation of Investment

Intel

Common model method

Scaling Consistency Multicore to Many-core

same programming models, programming languages, tools

Intel® Parallel Studio XE

Tools to CreateHighly optimizing Compilers,

High Performance Libraries,Designed for Performance and Analysis

Intel® Parallel Studio XE

Tools for AnalysisThreading Analysis & Debug

MPI Analysis & Debug

Vector Analysis & Debug


39

Compiler Support

Intel Compilers

GNU Compilers

http://www.prace-ri.eu/best-practice-guide-knights-landing-january-2017


40

Intel MKL library

Intel Math Kernel Library



41

Small Code Example – Writing Code



42

MPI Library…



43

Scaling tests of NPB – Pure MPI



44

Scaling tests of NPB – OpenMP



45

Scaling of HYDRO Code



Scaling of GROMACS



47

Compiler, Runtime Flags: GROMACS

Compiler Flags

Runtime Settings



48


49

Over 40 applications optimized for Intel® Xeon Phi™ processor family are available, with up to 6.48X (1.99X average) performance improvement1

Intel® Xeon Phi™ processor 7250 relative performance normalized to baseline (1) of a 2 socket Intel® Xeon® processor E5-2697 v4)

Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components,

software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the

performance of that product when combined with other products. For more complete information visit: http://www.intel.com/performance

UPDATED

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Benchmarks Life Science

Weather and Climate Physics / Geophysics / Energy

Manufacturing

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Trinity Benchmarks

1 – As demonstrated by respective proof points in this presentation

http://www.intel.com/performance


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Thank you!

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programming, intel performance, & efficiency architecture · 2018-01-29 · optimization notice...

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