progress on sts csa chip development e. atkin department of electronics, mephi a.voronin sinp, msu

Progress on STS CSA chip Progress on STS CSA chip developmentdevelopment

E. AtkinE. AtkinDepartment of Electronics, MEPhIDepartment of Electronics, MEPhI

A.VoroninA.Voronin SINP, MSUSINP, MSU

Feb 28 - Mar 3, 2006 Feb 28 - Mar 3, 2006 CBM meeting at GSI CBM meeting at GSI

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Main research goalsMain research goals

Design and production (via MPW) of a Design and production (via MPW) of a test purpose chip for SST prototyping test purpose chip for SST prototyping

Lab tests of ICs manufactured. Study Lab tests of ICs manufactured. Study of 0.18of 0.18µµ UMC process features UMC process features

Study of a face-to-face interface to Si Study of a face-to-face interface to Si strip prototypestrip prototype

IC radiation hardness tests technique IC radiation hardness tests technique developmentdevelopment


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CSA schematicCSA schematic

CSA is based on CSA is based on folded cascodefolded cascode architecture architecture DC and ACDC and AC input coupling are available input coupling are available Two mirrored versions of CSA has been studied. These are:Two mirrored versions of CSA has been studied. These are:

1) version with PMOS input transistor and1) version with PMOS input transistor and2) one with NMOS transistor.2) one with NMOS transistor. In accordance to the foundary Design Kit models at reasonable In accordance to the foundary Design Kit models at reasonable shaping the PMOS version showed a greater noise performance shaping the PMOS version showed a greater noise performance and was selected for the input device of CSAand was selected for the input device of CSA

Input PMOSInput PMOS: 0.5 mA (half power budget), 1.2mm*0.18um: 0.5 mA (half power budget), 1.2mm*0.18um Feedback cap 2pF sets the gain to Feedback cap 2pF sets the gain to 0.5 mV/fC0.5 mV/fC. Feedback is . Feedback is

optimized for up to 100pF capacitive detectors (pads, strips and optimized for up to 100pF capacitive detectors (pads, strips and so on) so on)

Noise at CSA output (wide bandwidth) at 100 pF of Cdet: Noise at CSA output (wide bandwidth) at 100 pF of Cdet: 200 uV 200 uV rmsrms for CSA core only, 350 uV rms for CSA with active feedback for CSA core only, 350 uV rms for CSA with active feedback

Maximal signal at 5% non-linearity – Maximal signal at 5% non-linearity – 0.5 V0.5 V (at ±1V supply and (at ±1V supply and Cdet up to 100 pF) Cdet up to 100 pF)

Supply voltages: 1) 0 and +1.8V or 2) -0.9 and +0.9 VSupply voltages: 1) 0 and +1.8V or 2) -0.9 and +0.9 V 1.0 mW/channel1.0 mW/channel


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CSA coreCSA core

1.2

1.2m

m*0

.18µ

m

mm

*0.1

8µm

0.5

mA

0.5

mA


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CSA simplified structureCSA simplified structure

Non-linear active feedback (leakage current compensation) – 1.0 uA max

CSA core

Biasing block


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Channel pins for CSAChannel pins for CSA

InputInput OutputOutput Monitoring of leakage currentMonitoring of leakage current Vdd, Vss + input transistor reference Vdd, Vss + input transistor reference

(AGND)(AGND)


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Rail-to-rail Op ampRail-to-rail Op amp

Features:

Universal block for shapers, buffer stages

Fast (few ns rise time) and low power (less than 1 mW)


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LayoutLayout

To be realized in a 0.18 um, single poly, six metal, salicide CMOS process from UMC, Taiwan.

That is a mini-ASIC run, scheduled via Europractice

8 CSAs

test CSA core

opampcomp

(Pad restrictive design)(Pad restrictive design)

60 pads, 1.5*1.5 sq.mm

2 full-time engineers + 4 diploma students, half a

year for

design

Structure blocks: 8 CSAs, test purpose CSA core, ra

il-to-rail

opamp, clocked comparator


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Development of building blocks for data-driven architecture, Development of building blocks for data-driven architecture, according to UMC CMOS 0.18 according to UMC CMOS 0.18 µµm. These blocks are:m. These blocks are: PreampPreamp Amplitude (slow) antialiasing and dynamic range saving shaperAmplitude (slow) antialiasing and dynamic range saving shaper Timing (fast), hit defining shaperTiming (fast), hit defining shaper Low offset high-speed comparatorLow offset high-speed comparator both for hit finder both for hit finder

and ADC. and ADC. StudyingStudying both both clockedclocked and non-clocked options and non-clocked options Threshold DAC (6-8 bit)Threshold DAC (6-8 bit) Fast low-bit (4…6 or 8 bit ?) ADCFast low-bit (4…6 or 8 bit ?) ADC Analog Derandomizer (deadtime free analog unit with n-inputs Analog Derandomizer (deadtime free analog unit with n-inputs

and m-outputs, n>m)and m-outputs, n>m) Rail-to-rail op amp (high speed buffer)Rail-to-rail op amp (high speed buffer)Common issues are: low power consumption, reasonable speed & Common issues are: low power consumption, reasonable speed &

chip areachip area

This talk covers partially the efforts on …


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RemarksRemarks This prototype ASIC blocks focus on study of This prototype ASIC blocks focus on study of

possibilities and merits of UMC 0.18um possibilities and merits of UMC 0.18um processprocess

All 8 CSAs are different each other. It is All 8 CSAs are different each other. It is needed to optimize the structure and biasing needed to optimize the structure and biasing of CSAof CSA

Additional information is in:Additional information is in:CBM-STS-note-internal-2006-001CBM-STS-note-internal-2006-001 of of 10 Jan 10 Jan 20062006The The mmetadata URL is etadata URL is httphttp://://www.gsi.dewww.gsi.de//documentsdocuments/DOC-2006-Jan-20_e.html/DOC-2006-Jan-20_e.html

http://www.gsi.de/documents/DOC-2006-Jan-20_e.html







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Participants:Participants:

MSU – schematics, board designs, test stations, MSU – schematics, board designs, test stations, testingtesting

MEPhI – schematics, layout, verification, GDSII files, MEPhI – schematics, layout, verification, GDSII files, ASIC test station, ASIC testingASIC test station, ASIC testing


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TestTest boardboard


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Test Test boardboard features features

• Adjustable voltage regulators 0.9V and 3.3V• Calibration capacitors• Detector capacitor equivalents• Line driver Cin = 2 pF• Voltage and current bias components• Offset regulators• Output loads• Low level clock drivers• All components are installed onto sockets


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Powerless DC tests for shorts, Powerless DC tests for shorts, openings and passive resistivity openings and passive resistivity OKOK

DC tests at nominal bias conditions DC tests at nominal bias conditions not passed not passed

Dynamic tests Dynamic tests not performednot performed

Test statusTest status(the main CSAs in one chip have been checked (the main CSAs in one chip have been checked

only!)only!)


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Chip interconnectionChip interconnection

• Full height is 1.6 mm

• Microconnector pitch 0.3 mm

• Chip VA-1, 128 channels, 50 µm input pitch, 6*4 mm

• Flexible interconnection PCB, 70 µm

• Chip connection type – bonding


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SummarySummary

•Presented are the main simulation results of CSA chip design, given as a part of the CBM MPW join run (UMC 0.18 um CMOS, June 2005, mini-ASIC conditions)

•Tests for 8-ch CSA appear to be more negative than positive, but should be continued with more than one chip sample

•Tests of the rest blocks in chip (ver.2 CSA, opamp, comp) should be performed too

progress on sts csa chip development e. atkin department of electronics, mephi a.voronin sinp, msu

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