projec report.doc

8/18/2019 projec report.doc

1/67

AUTOMATIC CIRCUIT GENERATOR

A

MAJOR PROJECT

Submitted for the partial fulfillment of the requirement for the aard of !e"ree of

#AC$E%OR O& ENGINEERING

IN

COMPUTER SCIENCE ' ENGINEERING

Submitted b() Guided #()

*+$ariom !e,ar Mr-+ An,ana !een

.+Murlidhar !aharal

/+Sa0hin

!EPARTMENT O& COMPUTER SCIENCE ' ENGINEERING

UNI1ERSIT2 INSTITUTE O& TEC$NO%OG2

RAJI1 GAN!$I PROU!2OGI3I 1IS$4A1I!A%A2A

BHOPAL-462036

MA2 .5*5

1


2/67

UNI1ERSIT2 INSTITUTE O& TEC$NO%OG2

RAJIV GANDHI PROUDYOGIKI VISHWAVIDALAYA, BHOPAL

!EPARTMENT O& COMPUTER SCIENCE ' ENGINEERING

CERTIFICATE

This is to certify that $ariom !e,ar6Murlidhar !aharal ' Sa0hin of B.E final year ,

Computer science & Engg. has completed his major project “AUTOMATIC CIRCUIT

GENERATOR7 during the academic year 2009!0 under my guidance and super"ision.

# appro"e the project for the su$mission for the partial fulfillment of the re%uirement for

the aard of degree in Computer 'cience & Engineering.

Name of GUI!E Prof+1+3 Sethi Prof+San,a( Sila8ari

Prof+ An,ana !een !ire0tor $ead of !epartment

Prof+ Pi(u-h Shu8la UIT 6 RGP1

CSE

2


3/67


4/67

C345(6E/E*E4T

B'TCT

Table of Content-

'.45 T5#C age 4o.

!. #ntroduction 07

2. 6iterature 'ur"ey and related or) !2

8. ro$lem escription !7

. roposed or) 29

:. esign nd e"elopment 82

;. #mplementation !


5/67

A08noled"ement

(e ould li)e to e>press our deepest appreciation to our ad"isor, Mr-+ An,ana!een and *r. iyush 'hu)la for her constant guidance, encouragement andsupport in helping us to complete this or). (e ill cherish the e>periencelearning and or)ing ith her fore"er.

#n addition, (e ould li)e to than) Prof+ Sana,a( Sila8ari 9$ead of !epartmentCSE: and Mr+ Mani-h Ahirar9fa0ult(60omputer -0ien0e department: for their help and guidance on our project.

(e ould also li)e to than) our la$ assisstant, *r. 'u$odh 'ri"asta"a, for pro"iding us all necessary la$ e%uipment.(e ould li)e to than) our friends hoha"e made us stay at graduate school enjoya$le and ho ha"e made e"ery aspectof project e>citing and interesting to us.(e ould also li)e to than) our familymem$er for supporting us.

5


6/67

Ab-tra0t

(ith e"er shrin)ing geometries, groing metal density and increasing cloc) rate on chips, delaytesting is $ecoming a necessity in industry to maintain test %uality for speedrelated failures. The purpose of delay testing is to "erify that the circuit operates correctly at the rated speed.?oe"er, functional tests for delay defects are usually unaccepta$le for large scale designs dueto the prohi$iti"e cost of functional test patterns and the difficulty in achie"ing "ery high faultco"erage. 'can $ased delay testing, hich could ensure a high delay fault co"erage at reasona$lede"elopment cost, pro"ides a good alternati"e to the atspeed functional test. This dissertationaddresses se"eral )ey challenges in scan$ased delay testing and de"elops efficient utomaticTest attern /eneration @T/A and esign for testa$ility @=TA algorithms for delay testing. #nthe dissertation, to algorithms are first proposed for computing and applying transition test patterns using stuc)at test "ectors, thus a"oiding the need for a transition fault test generator.The e>perimental results sho that e can impro"e $oth test data "olume and test applicationtime $y ;.: o"er a commercial transition T/ tool. 'econdly, e propose a hy$rid scan $ased delay testing techni%ue for compact and high fault co"erage test set, hich com$ines thead"antages of $oth the s)eedload and $roadside test application methods. 5n an a"erage,a$out .: impro"ement in fault co"erage is o$tained $y the hy$rid approach o"er the $roadside approach, ith "ery little hardare o"erhead. Thirdly, e propose and de"elop a constrainedT/ algorithm for scan$ased delay testing, hich addresses the o"ertesting pro$lem due to the possi$le detection of functionally untesta$le faults in scan$ased testing. The e>perimentalresults sho that our method efficiently generates a test set for functionally testa$le transitionfaults and reduces the yield loss due to o"ertesting of functionally untesta$le transition faults.=inally, a ne approach on identifying functionally untesta$le transition faults in nonscanse%uential circuits is presented. (e formulate a ne dominance relationship for transition faultsand use it to help identify more untesta$le transition faults on top of a faultindependent method $ased on static implications. The e>perimental results for #'C'79 se%uential $enchmar) circuits sho that our approach can identify many more functionally untesta$le transition faultsthan pre"iously reported.

6


7/67

A08noled"ement

(e ould li)e to e>press our deepest appreciation to our ad"isor, Mr-+ An,ana!ean, for her constant guidance, encouragement and support in helping us tocomplete this or). (e ill cherish the e>perience learning and or)ing ith her fore"er.

#n addition, (e ould li)e to than) Prof+ Sana,a( Sila8ari 9$ead of !epartmentCSE: and Mr+ Mani-h Ahirar for their help and guidance on our project.(e ould li)e to than) our friends ho ha"e made us stay at graduate schoolenjoya$le and ho ha"e made e"ery aspect of project e>citing and interesting tous.

7


8/67

Introdu0tion

8


9/67

Introdu0tion

The main o$jecti"e of traditional test de"elopment has $een the attainment of high stuc)at faultco"erage. ?oe"er, the presence of some random defects does not affect a circuits operation atlo speed hile it may cause circuit malfunction at rated speed. This )ind of defect is called thedelay defect. (ith e"er shrin)ing geometries, groing metal density and increasing cloc) rate of chips, delay testing is gaining more and more industry attention to maintain test %uality for speedrelated failures. The purpose of a delay test is to "erify that the circuit operates correctly ata desired cloc) speed. lthough application of stuc)at fault tests can detect some delay defects,it is no longer sufficient to test the circuit for the stuc)at faults alone. Therefore, delay testing is $ecoming a necessity for todays #C manufacturing test. #n the past, testing a circuits performance as typically accomplished ith functional test patterns. ?oe"er, de"eloping

functional test patterns that attain satisfactory fault co"erage is unaccepta$le for large scaledesigns due to the prohi$iti"e de"elopment cost. E"en if functional test patterns that can achie"ehigh fault co"erage are a"aila$le, applying these test patterns atspeed for high speed chipsre%uires "ery stringent timing accuracy, hich must $e pro"ided $y "ery e>pensi"e automatictest e%uipment @TEsA. The scan$ased delay testing here test patterns are generated $y anautomatic test pattern generator @T/A on designs that in"ol"e scan chains is increasingly usedas a cost efficient alternati"e to the at speed functional pattern approach to test large scale chipsfor performancerelated failures.esignfortesta$ility @=TAfocused TEs, hich are designedand de"eloped to loer TE cost $y considering idely used =T features of circuits under test@C-TsA such as full and partial scan are emerging as a strong trend in the test industry. 'e"eraldelay fault models ha"e $een de"eloped, such as transition delay fault, gate delay fault path

delay ,and segment delay fault models. transition fault at node D

assumes a large delay at D

suchthat the transition at Dill not reach the latch or primary output ithin the cloc) period. The pathdelay fault model assumes a small delay at each gate. #t models cumulati"e effect of gate delaysalong a specific path, from a primary input to a primary output. #f the cumulati"e delay e>ceedsthe slac) for the path, then the chip fails. 'egment delay fault targets path segments instead of complete paths. mong these fault models, the transition delay fault model is most idely usedin industry for its simplicity. T/s and fault simulators that are de"eloped for stuc)at faultscan $e reused for transition delay faults ith minor modifications. -nli)e the path delay faultmodel here the num$er of target faults is often e>ponential, the num$er of transition delayfaults is linear ith the num$er of circuit lines. This eliminates the need for critical path analysisand identification procedures, hich are necessary for the path delay fault model. The gate delay

model is similar to the transition delay fault model in that the delay fault is lumped at one gate inthe C-T. ?oe"er, unli)e the transition delay model hich does not ta)e into account faultsies, the gate delay model 2 ta)es into account fault sies. The segment delay fault model is atradeoff $eteen the path delay fault and transition delay fault models. etection of a delayfault normally re%uires the application of a pair of test "ectorsF the first "ector, calledinitialization vector , initialies the targeted faulty circuit line to a desired "alue and the second"ector, called launch vector , launches a transition at the circuit line and propagates the faulteffect to primary output@sA andGor scan flipflop@sA.

9


10/67

#n order to impro"e the %uality of microprocessor tests, the use of instructional sets for

testing is indespensa$le. #n this paperF e ill present a ne method consisting of the automatic

generation of a functional test pattern, formed $y a com$ination of instruction sets and ena$ling

the efficient impro"ement of the fault co"erage. (ith this method, a test pattern is first generated

to test all of an ' num$er of instruction mnemonics. Then, for the faults that ere undetected $y

that test pattern, an 6 num$er of sets of 3 num$der of instructions are dran from the ' num$er

of instructions, and the set ena$ling the efficient impro"ement of the fault co"erage is selected.

By repeating this procedure, a high fault co"erage can $e o$tained ith a short test pattern. The

effecti"eness of our method as pro"ed $y the results of e>periments o$tained ith the softare

that as created $ased on this method.

ifferent techni%ues for sol"ing the pro$lem of generating tests for structural faults in

e%uential circuits ha"e $een proposed o"er the years. 5n the gatele"el, deterministic and

simulation $ased algorithms ha"e $een proposed. ?oe"er, the e>ecution times are e>tremely

long and for medium and large circuits mostly rather lo fault co"erages ha"e $een achie"ed.

ecently, promising results $ased on softare testing techni%ues com$ined ith lo le"el test

ha"e $een pu$lished in The approach offers high fault co"erages for medium sied $enchmar)

circuits $ut the test generation still ta)es relati"ely much time. =urthermore, the authors ha"e not

de"eloped any formalied method for generating the highle"el test frames and the time needed

to generate the frames has not $een ta)en into account in the e>periments. Tri"ial finite state

machines containing only a single control state ha"e $een implemented for some of the larger

e>ample circuits. t present, hierarchical test generation is the fastest and most effecti"e means

for se%uential circuits testing ?ere, designs descri$ed on different a$straction le"els, usually on

architectural and gatele"el, are used. The method cannot $e applied to designs that do not ha"e

appropriate modularity, or here gatele"el implementation for the modules is not )non.

?oe"er, as a num$er of commercial highle"el synthesis tools ha"e emerged, the input

description should not $e a major issue.re"ious or)s in the area of hierarchical testing ha"e

the folloing main shortcomingsH

!. 5nly the faults in the datapath =unctional -nits @=-A are targeted.This usually results in lo

fault co"erages for the control part as ell as for multiple>ers, registers and fanout $uses of the

datapath.

2. comple> set of sym$ols and constraints is used during highle"el path acti"ation.This feature

ma)es the sym$olic path acti"ation process "ery computeintensi"e. =or more comple> circuits it

can also cause highle"el tests for many =-s to fail due to the strict conditions.

The aim of the approach proposed in current paper is too"ercome the a$o"e mentionedshortcomings. ifferently from )non methods, $oth, control unit and datapath are handled in auniform manner. restricted set of sym$ols is used during the path acti"ation. This allos tosimplify the test generation algorithm hile still maintaining a good correspondence $eteenhighle"el assessments and gatele"el fault co"erage. The paper is organied as follos. 'ection 2

10


11/67

gi"es a short o"er"ie of representing circuit architecture $y ecision iagram @A models.'ection 8 introduces the test generation algorithm. =inally, e>perimental results and conclusions are presented.

11


12/67

%iterature Sur;e( ' Related 4or8

12


13/67

%iterature Sur;e( ' Related 4or8

'e"eral delay fault models ha"e $een de"eloped for delay defectsH transition delay fault,gate delay fault , path delay fault, and segment delay fault models. transition fault at node D assumes a large delay at D such that the transition at D ill not reach the latch or primary outputithin the cloc) period. The path delay fault model assumes a small delay at each gate. #t modelscumulati"e effect of gate delays along a specific path, from a primary input to a primary output.#f the cumulati"e delay e>ceeds the slac) for the path, then the chip fails. 'egment delay faulttargets path segments instead of complete paths. mong these fault models, the transition delayfault model is most idely used in industry for its simplicity. T/s and fault simulators that arede"eloped for stuc)at faults can $e reused for transition delay faults ith minor modifications.-nli)e the path delay fault model here the num$er of target faults is often e>ponential, thenum$er of transition delay faults is linear to the num$er of circuit lines. This eliminates the needfor critical path analysis and identification procedures, hich are necessary for the path delayfault model.

/ate delay model is similar to transition delay fault model in that the delay fault is lumped at onegate in the C-T. ?oe"er, unli)e transition delay model hich does not ta)e into account faultsies, gate delay model ta)es into account fault sies. 'egment delay fault model is a tradeoff $eteen path delay fault and transition delay fault models.

&un0tional !ela( Te-tin"#n the past, testing circuits performance as typically accomplished ith functional test [email protected]. testing a microprocessor ith instruction se%uencesA, in hich the input signals tothe C-T are determined $y its functionality. This result in a much smaller set of "ector pairs

applica$le for delay testing. lso, after the application of certain test sets, someregistersGflipflops may not $e ena$led in the immediate ne>t cycle, and thus delay fault effects propagated to them can not $e latched and ill $e lost. Therefore, de"eloping functional test patterns that attain satisfactory fault co"erage is unaccepta$le for large scale designs due to the prohi$iti"e de"elopment cost. E"en if functional test patterns that can achie"e high faultco"erage are a"aila$le, applying these test patterns atspeed for high speed chips re%uires "erystringent timing accuracy, hich can $e pro"ided $y "ery e>pensi"e automatic test e%uipments@TEsA. The scan$ased delay testing here test patterns are generated $y an automatic test pattern generator @T/A on designs that in"ol"e scan chains is increasingly used as a costefficient alternati"e to the atspeed functional pattern approach to test large scale chips for performancerelated failures. esignfortesta$ility @=TA focused TEs hich are designed

and de"eloped to loer TE cost $y considering idely used =T features of circuits under test@C-TsA such as full and partial scan are emerging as a strong trend in test industry.

13


14/67

S0ant, 12 is scanned in, folloed $y an apply and su$se%uently a capture of theresponse. uring shifting in of 12 it is assumed that the initialiation of 1! is not destroyed.Therefore enhancedscan transition testing assumes a holdscan design. Enhanced scan transitiontest has to primary ad"antagesH co"erage and test data "olume. 'ince enhanced scan testing

allos the application of any ar$itrary "ector pair to the com$inational part of a se%uentialcircuit. ?ence, complete fault co"erage can $e attained. Tester memory re%uirement is alsoimportant, and considera$le attention is $eing paid to reduce the tester memory re%uirement for sI tests. The pro$lemis far orse for transition tests as the folloing data shos. #n it asreported that for s)eed load transition tests for an '#C, the sI "ector memory re%uirementas 7.:!* "ersus :0.2* for transition test. This implies an increase of a factor of :.9. Thedonside of using enhancedscan transition test is that special scan design, "i. holdscan thatcan hold to $its, is re%uired. This may leads to higher area o"erhead, hich may pre"ent it fromusing idely in '#C area. ?oe"er,in microprocessors and other high performance circuits thatre%uire custom design, such cells are used for other reasons. #n custom designs, the circuit oftenis not fully decoded, hold scan cells are used to pre"ent contention in the data $eing shifted, as

ell as pre"enting e>cessi"e poer dissipation in the circuit during the scan shift phase.=urthermore, if holdscan cells are used, the failing parts in hich only the scan logic failed canoften $e retrie"edF thus enhancing, to some e>tent, the diagnostic capa$ility associated ith scan=T. Therefore, for such designs enhancedscan transition tests is preferred. This is our moti"ation for in"estigating good T/ techni%ues for enhancedscan transition tests. Therefore,e can see that the to "ectors @1!,12A are independent to each other. ?oe"er, in the ne>t toapproaches @s)eedload and $roadsideA, the second "ector is deri"ed from the first "ector.

S8eed


15/67

$y one more scan flipflop and scanning in a ne "alue into the scan chain input. 4ote that thescan ena$le signal stays at logic high during the launch cycle. t the ne>t cloc) cycle @capturecycleA, the scan ena$le signal sitches to logic lo and the scan flipflops in the scan chain areconfigured in their normal mode to capture the response to the scanned in test "ector. 'ince thecapture cloc) is applied at full system cloc) speed after the launch cloc), the scan ena$le signal,

hich typically dri"es all scan flipflops in the C-T, should also sitch ithin the full systemcloc) cycle. This re%uires the scan ena$le signal to $e dri"en $y a sophisticated $uffer tree or strong cloc) $uffer. 'uch design re%uirement is often too costly to meet. =urthermore, meetingsuch a strict timing re%uired for the scan ena$le signal may result in longer design time. 'ince thesecond "ector of each "ector pair is o$tained $y shifting in the first "ector $y one more scan flipflop, gi"en a first "ector, there are only to possi$le "ectors for the second "ector that differsonly at the "alue for the first scan flipflop hose scan input is connected to the scan chain input.This shift dependency restricts the num$er of com$inations of test "ector pairs to in standardscan en"ironment, here is the num$er of scan flipflops in the scan chain. #f there is atransition delay fault that re%uires a ! at state input in an initialiation "ector and re%uires a 0 atstate input in the corresponding launch "ector to $e detected, then that fault is untreata$le $y the

s)eedload approach @assume that the scan chain is constructed $y using only nonin"ertingoutputs of scan flipflopsA.

#road-ide

#n the third approach, referred to as the $roadside or launchfrom capture, 'imilar to thes)eedload approach, the initialiation "ector of a test "ector pair is first loaded into scan chain

$y consecuti"e scan shift operations, here is the num$er of scan flipflops in the scan chain, inthe same fashion as a stuc)attest "ector is loaded into the scan chain. Then, the second "ector iso$tained from the circuit response to the first "ector. ?ence, the scan flipflops are configuredinto the normal mode $y loering the ena$le signal $efore e"ery launch. 'ince the launch cloc) folloing an initialiation cloc) need not $e an atspeed cloc), the scan ena$le signal does notha"e to sitch to logic lo at full system cloc) speed $eteen the initialiation cloc) and thelaunch cloc). 4ote that in $roadside approach, launch "ectors are applied hen scan flipflopsare in their normal mode. #n other ords, the atspeed cloc)s, the capture cloc) after the launch,is applied to scan flipflops hile the scan flipflops stays in their normal mode. ?ence, the scanena$le signal does not ha"e to sitch $eteen the launch cycle and the capture cycle hencloc)s are applied at full system cloc) speed. ?ence, the $roadside approach does not re%uire atspeed transition of the scan ena$le signal and can $e implemented ith lo hardare o"erhead.E"en though the $roadside approach is cheaper to implement than the s)eed load approach,fault co"erage achie"ed $y test pattern sets generated $y the $roadside approach is typicallyloer than that achie"ed $y test pattern sets generated $y the s)eedload approach .Test patternsets generated $y the $roadside approach are typically larger than those generated $y the s)eedload approach. #n order to generate to "ector tests for the $roadside approach, an T/ ithse%uential property that considers to full time frames is re%uired. 5n the other hand, test patterns for the s)eedload approach can $e gene acted $ay com$inational T/ ith little

15


16/67

modification. ?ence, higher test generation cost @longer test generation timeA should $e paid for the $roadside approach. 'ince in the $roadside approach, the second "ector is gi"en $y thecircuit response to the first "ector, unless the circuit can transition to all DD states, here is thenum$er of scan flipflops, the num$er of possi$le "ector that can $e applied as second "ectors of test "ector pairs is limited. ?ence, if a state re%uired to acti"ate and propagate a fault is an

in"alid state, i.e., the state cannot $e functionally justified, then the transition delay fault isuntreata$le. Typically, in large circuits that ha"e a large num$er of flipflops, the num$er of reacha$le states is only a small fraction of Dstates. ue to this reason, transition fault co"erage for standard scan designs is often su$stantially loer than stuc)at fault co"erage.

mong the three approaches for applying delay tests, $roadside suffers from poor fault co"erage.'ince there is no dependency $eteen the to "ectors in Enhanced scan, it can gi"e $etter co"erage than s)eedload transition test. ')eedload transition tests also lead to larger testdata "olume. Compared to stuc)at tests, the increase in the num$er of "ectors re%uired for enhanced scan to get complete co"erage is a$out .=or s)eedload transition test,it has $een

o$ser"ed that the data "olume has an increase of :.9L.=or most circuits, test sets generated $ythe s)eedload approach achie"e higher fault co"erage than those generated $y the $roadsideapproach.'ies of test pattern sets generated $y the s)eedload approach are also typicallysmaller than those generated $y the $roadside approach ?oe"er, the s)eedload approachre%uires higher hardare o"erhead and may re%uire longer design times .

16


17/67

Time !ela(

fi>ed time delay is often useful. 5ne such application, a dead time generator, is useful hereto sitching transistors cannot $e simultaneously turned on. This could $e here, in a half

a"e $ridge type application, the turnon on one de"ice is delayed folloing the turn off of theother de"ice. nother use is in '*' models to delay sitching transistor turnon duringinter"als here sitching noise could $e present.

The pro$lem is that often other "aria$les may $e changing in the course of an analysis, and using pl de"ices, logical e%uations, or some circuit implementations might $e cum$ersome. #n thiscase a delay line is used. This as suggested $y Chris Basso and descri$ed in his $oo).

17


18/67

Problem !e-0ription

18


19/67

Problem !e-0ription

Inte"rated 0ir0uit

#n electronics, an integrated circuit @also )non as #C, microcircuit, microchip, silicon chip, or chipA is a miniaturied electronic circuit @consisting mainly of semiconductor de"ices, as ell as passi"e componentsA that has $een manufactured in the surface of a thin su$strate of semiconductor material. #ntegrated circuits are used in almost all electronic e%uipment in usetoday and ha"e re"olutionied the orld of electronics.

hy$rid integrated circuit is a miniaturied electronic circuit constructed of indi"idualsemiconductor de"ices, as ell as passi"e components, $onded to a su$strate or circuit $oard.

#ntegrated circuits ere made possi$le $y e>perimental disco"eries hich shoed thatsemiconductor de"ices could perform the functions of "acuum tu$es, and $y mid20thcenturytechnology ad"ancements in semiconductor de"ice fa$rication. The integration of large num$ersof tiny transistors into a small chip as an enormous impro"ement o"er the manual assem$ly of circuits using electronic components. The integrated circuitMs mass production capa$ility,relia$ility, and $uilding$loc) approach to circuit design ensured the rapid adoption of standardied #Cs in place of designs using discrete transistors.

There are to main ad"antages of #Cs o"er discrete circuitsH cost and performance. Cost is lo $ecause the chips, ith all their components, are printed as a unit $y photolithography and notconstructed as one transistor at a time. =urthermore, much less material is used to construct a

circuit as a pac)aged #C die than as a discrete circuit. erformance is high since the componentssitch %uic)ly and consume little poer @compared to their discrete counterpartsA $ecause thecomponents are small and close together. s of 200;, chip areas range from a fe s%uaremillimeters to around 8:0 mm, ith up to ! million transistors per mm.

19

http://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Electronic_circuithttp://en.wikipedia.org/wiki/Semiconductor_devicehttp://en.wikipedia.org/wiki/Passive_componenthttp://en.wikipedia.org/wiki/Wafer_(electronics)http://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Hybrid_circuithttp://en.wikipedia.org/wiki/Semiconductor_devicehttp://en.wikipedia.org/wiki/Vacuum_tubehttp://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Electronic_componenthttp://en.wikipedia.org/wiki/Mass_productionhttp://en.wikipedia.org/wiki/Discrete_circuithttp://en.wikipedia.org/wiki/Photolithographyhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Electronicshttp://en.wikipedia.org/wiki/Electronic_circuithttp://en.wikipedia.org/wiki/Semiconductor_devicehttp://en.wikipedia.org/wiki/Passive_componenthttp://en.wikipedia.org/wiki/Wafer_(electronics)http://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Hybrid_circuithttp://en.wikipedia.org/wiki/Semiconductor_devicehttp://en.wikipedia.org/wiki/Vacuum_tubehttp://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Electronic_componenthttp://en.wikipedia.org/wiki/Mass_productionhttp://en.wikipedia.org/wiki/Discrete_circuithttp://en.wikipedia.org/wiki/Photolithographyhttp://en.wikipedia.org/wiki/Transistor


20/67

In!n"#$n

The idea of integrated circuit as concei"ed $y a radar scientist or)ing for the oyal adar Esta$lishment of the British *inistry of efence, /eoffrey (.. ummer @!9092002A, ho pu$lished it at the 'ymposium on rogress in Nuality Electronic Components in (ashington,.C. on *ay


21/67

G!n!%&"#$n'

SSI6 MSI and %SI

The first integrated circuits contained only a fe transistors. Called P'mall'cale #ntegrationP

@''#A, digital circuits containing transistors num$ering in the tens pro"ided a fe logic gates for e>ample, hile early linear #Cs such as the lessey '620! or the hilips T820 had as fe asto transistors. The term 6arge 'cale #ntegration as first used $y #B* scientist olf 6andauer hen descri$ing the theoretical concept, from there came the terms for ''#, *'#, 16'#, and-6'#.

''# circuits ere crucial to early aerospace projects, and "ice"ersa. Both the *inuteman missileand pollo program needed lighteight digital computers for their inertial guidance systemsF thepollo guidance computer led and moti"ated the integratedcircuit technologyJcitation needed K, hilethe *inuteman missile forced it into massproduction.

These programs purchased almost all of the a"aila$le integrated circuits from !9;0 through!9;8, and almost alone pro"ided the demand that funded the production impro"ements to get the production costs from Q!000Gcircuit @in !9;0 dollarsA to merely Q2:Gcircuit @in !9;8 dollarsA.They $egan to appear in consumer products at the turn of the decade, a typical application $eing=* intercarrier sound processing in tele"ision recei"ers.

The ne>t step in the de"elopment of integrated circuits, ta)en in the late !9;0s, introducedde"ices hich contained hundreds of transistors on each chip, called P*edium'cale #ntegrationP@*'#A.

They ere attracti"e economically $ecause hile they cost little more to produce than ''#

de"ices, they alloed more comple> systems to $e produced using smaller circuit $oards, lessassem$ly or) @$ecause of feer separate componentsA, and a num$er of other ad"antages.

=urther de"elopment, dri"en $y the same economic factors, led to P6arge'cale #ntegrationP@6'#A in the mid !9


22/67

There as no single $rea)through that alloed this increase in comple>ity, though many factorshelped. *anufacturers mo"ed to smaller rules and cleaner fa$s, so that they could ma)e chipsith more transistors and maintain ade%uate yield. The path of process impro"ements assummaried $y the #nternational Technology oadmap for 'emiconductors @#T'A. esign toolsimpro"ed enough to ma)e it practical to finish these designs in a reasona$le time. The more

energy efficient C*5' replaced 4*5' and *5', a"oiding a prohi$iti"e increase in poer consumption. Better te>ts such as the landmar) te>t$oo) $y *ead and Conay helped schoolseducate more designers, among other factors.

#n !97; the first one mega$it * chips ere introduced, hich contained more than onemillion transistors. *icroprocessor chips passed the million transistor mar) in !979 and the $illion transistor mar) in 200:. The trend continues largely una$ated, ith chips introduced in200< containing tens of $illions of memory transistors.

A(&n)!' #n #n"!*%&"!( )#%)+#"'

mong the most ad"anced integrated circuits are the microprocessors or P0ore-P, hich controle"erything from computers to cellular phones to digital microa"e o"ens. igital memory chipsand '#Cs are e>amples of other families of integrated circuits that are important to the moderninformation society. (hile the cost of designing and de"eloping a comple> integrated circuit is%uite high, hen spread across typically millions of production units the indi"idual #C cost isminimied. The performance of #Cs is high $ecause the small sie allos short traces hich inturn allos lo poer logic @such as C*5'A to $e used at fast sitching speeds.

#Cs ha"e consistently migrated to smaller feature sies o"er the years, alloing more circuitry to $e pac)ed on each chip. This increased capacity per unit area can $e used to decrease cost andGor increase functionalityRsee *ooreMs la hich, in its modern interpretation, states that thenum$er of transistors in an integrated circuit dou$les e"ery to years. #n general, as the featuresie shrin)s, almost e"erything impro"esRthe cost per unit and the sitching poer consumption go don, and the speed goes up. ?oe"er, #Cs ith nanometer scale de"ices arenot ithout their pro$lems, principal among hich is lea)age current @see su$threshold lea)age

22

http://en.wikipedia.org/wiki/International_Technology_Roadmap_for_Semiconductorshttp://en.wikipedia.org/wiki/Electronic_Design_Automationhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/NMOShttp://en.wikipedia.org/wiki/PMOShttp://en.wikipedia.org/wiki/Carver_Meadhttp://en.wikipedia.org/wiki/Lynn_Conwayhttp://en.wikipedia.org/wiki/Random_Access_Memoryhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Computerhttp://en.wikipedia.org/wiki/Cellular_phonehttp://en.wikipedia.org/wiki/Microwave_ovenhttp://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Information_societyhttp://en.wikipedia.org/wiki/Electric_powerhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Moore's_lawhttp://en.wikipedia.org/wiki/Nanometerhttp://en.wikipedia.org/wiki/Subthreshold_leakagehttp://en.wikipedia.org/wiki/File:153056995_5ef8b01016_o.jpghttp://en.wikipedia.org/wiki/File:153056995_5ef8b01016_o.jpghttp://en.wikipedia.org/wiki/International_Technology_Roadmap_for_Semiconductorshttp://en.wikipedia.org/wiki/Electronic_Design_Automationhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/NMOShttp://en.wikipedia.org/wiki/PMOShttp://en.wikipedia.org/wiki/Carver_Meadhttp://en.wikipedia.org/wiki/Lynn_Conwayhttp://en.wikipedia.org/wiki/Random_Access_Memoryhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Computerhttp://en.wikipedia.org/wiki/Cellular_phonehttp://en.wikipedia.org/wiki/Microwave_ovenhttp://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Information_societyhttp://en.wikipedia.org/wiki/Electric_powerhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Moore's_lawhttp://en.wikipedia.org/wiki/Nanometerhttp://en.wikipedia.org/wiki/Subthreshold_leakage


23/67


24/67

&n+/&)"+%#n*

&abri0ation

endering of a small standard cell ith three metal layers @dielectric has $een remo"edA. The sand

colored structures are metal interconnect, ith the "ertical pillars $eing contacts, typically plugs of

tungsten. The reddish structures are polysilicon gates, and the solid at the $ottom is the crystalline silicon

$ul).

'chematic structure of a C*5' chip, as $uilt in the early 2000s. The graphic shos 6*#'=ETMs on

an '5# su$strate ith fi"e metalliation layers and solder $ump for flipchip $onding. #t also shos the

section for =E56 @frontend of lineA, BE56 @$ac)end of lineA and first parts of $ac)end process.

24

http://en.wikipedia.org/wiki/Standard_cellhttp://en.wikipedia.org/wiki/Dielectrichttp://en.wikipedia.org/wiki/File:Cmos-chip_structure_in_2000s_%28en%29.svghttp://en.wikipedia.org/wiki/File:Cmos-chip_structure_in_2000s_%28en%29.svghttp://en.wikipedia.org/wiki/File:Silicon_chip_3d.pnghttp://en.wikipedia.org/wiki/File:Silicon_chip_3d.pnghttp://en.wikipedia.org/wiki/Standard_cellhttp://en.wikipedia.org/wiki/Dielectric


25/67

The semiconductors of the periodic ta$le of the chemical elements ere identified as the mostli)ely materials for a solid state vacuum tube $y researchers li)e (illiam 'hoc)ley at Bell6a$oratories starting in the !980s. 'tarting ith copper o>ide, proceeding to germanium, thensilicon, the materials ere systematically studied in the !90s and !9:0s. Today, siliconmonocrystals are the main su$strate used for integrated circuits (ICs) although some ###1

compounds of the periodic ta$le such as gallium arsenide are used for specialied applicationsli)e 6Es, lasers, solar cells and the highestspeed integrated circuits. #t too) decades to perfectmethods of creating crystals ithout defects in the crystalline structure of the semiconductingmaterial.

'emiconductor #Cs are fa$ricated in a layer process hich includes these )ey process stepsH

• #maging

• eposition

• Etching

The main process steps are supplemented $y doping and cleaning.

*onocrystal silicon afers @or for special applications, silicon on sapphire or gallium arsenideafersA are used as the substrate. hotolithography is used to mar) different areas of thesu$strate to $e doped or to ha"e polysilicon, insulators or metal @typically aluminiumA trac)sdeposited on them.

• #ntegrated circuits are composed of many o"erlapping layers, each defined $y photolithography,

and normally shon in different colors. 'ome layers mar) here "arious dopants are diffusedinto the su$strate @called diffusion layersA, some define here additional ions are implanted@implant layersA, some define the conductors @polysilicon or metal layersA, and some define the

connections $eteen the conducting layers @"ia or contact layersA. ll components areconstructed from a specific com$ination of these layers.

• #n a selfaligned C*5' process, a transistor is formed here"er the gate layer @polysilicon or

metalA crosses a diffusion layer.

• Capaciti"e structures, in form "ery much li)e the parallel conducting plates of a traditional

electrical capacitor, are formed according to the area of the PplatesP, ith insulating material $eteen the plates. Capacitors of a ide range of sies are common on #Cs.

• *eandering stripes of "arying lengths are sometimes used to form onchip resistors, though most

logic circuits do not need any resistors. The ratio of the length of the resisti"e structure to its

idth, com$ined ith its sheet resisti"ity, determines the resistance.

• *ore rarely, inducti"e structures can $e $uilt as tiny onchip coils, or simulated $y gyrators.

'ince a C*5' de"ice only dras current on the transition $eteen logic states, C*5' de"icesconsume much less current than $ipolar de"ices.

25

http://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Periodic_tablehttp://en.wikipedia.org/wiki/Chemical_elementhttp://en.wikipedia.org/wiki/Solid_state_(electronics)http://en.wikipedia.org/wiki/Vacuum_tubehttp://en.wikipedia.org/wiki/Vacuum_tubehttp://en.wikipedia.org/wiki/William_Shockleyhttp://en.wikipedia.org/wiki/Bell_Laboratorieshttp://en.wikipedia.org/wiki/Bell_Laboratorieshttp://en.wikipedia.org/wiki/Copper_oxidehttp://en.wikipedia.org/wiki/Germaniumhttp://en.wikipedia.org/wiki/Siliconhttp://en.wikipedia.org/wiki/Monocrystalhttp://en.wikipedia.org/wiki/Substrate_(printing)http://en.wikipedia.org/wiki/Gallium_arsenidehttp://en.wikipedia.org/wiki/LEDshttp://en.wikipedia.org/wiki/Lasershttp://en.wikipedia.org/wiki/Solar_cellshttp://en.wikipedia.org/wiki/Crystalhttp://en.wikipedia.org/wiki/Crystalline_structurehttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Siliconhttp://en.wikipedia.org/wiki/Wafer_(electronics)http://en.wikipedia.org/wiki/Silicon_on_sapphirehttp://en.wikipedia.org/wiki/Gallium_arsenidehttp://en.wikipedia.org/wiki/Photolithographyhttp://en.wikipedia.org/wiki/Doping_(Semiconductors)http://en.wikipedia.org/wiki/Aluminiumhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Resistorhttp://en.wikipedia.org/wiki/Inductorhttp://en.wikipedia.org/wiki/Gyratorhttp://en.wikipedia.org/wiki/Boolean_algebra_(logic)http://en.wikipedia.org/wiki/State_(computer_science)http://en.wikipedia.org/wiki/Bipolar_transistorhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Periodic_tablehttp://en.wikipedia.org/wiki/Chemical_elementhttp://en.wikipedia.org/wiki/Solid_state_(electronics)http://en.wikipedia.org/wiki/Vacuum_tubehttp://en.wikipedia.org/wiki/William_Shockleyhttp://en.wikipedia.org/wiki/Bell_Laboratorieshttp://en.wikipedia.org/wiki/Bell_Laboratorieshttp://en.wikipedia.org/wiki/Copper_oxidehttp://en.wikipedia.org/wiki/Germaniumhttp://en.wikipedia.org/wiki/Siliconhttp://en.wikipedia.org/wiki/Monocrystalhttp://en.wikipedia.org/wiki/Substrate_(printing)http://en.wikipedia.org/wiki/Gallium_arsenidehttp://en.wikipedia.org/wiki/LEDshttp://en.wikipedia.org/wiki/Lasershttp://en.wikipedia.org/wiki/Solar_cellshttp://en.wikipedia.org/wiki/Crystalhttp://en.wikipedia.org/wiki/Crystalline_structurehttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Siliconhttp://en.wikipedia.org/wiki/Wafer_(electronics)http://en.wikipedia.org/wiki/Silicon_on_sapphirehttp://en.wikipedia.org/wiki/Gallium_arsenidehttp://en.wikipedia.org/wiki/Photolithographyhttp://en.wikipedia.org/wiki/Doping_(Semiconductors)http://en.wikipedia.org/wiki/Aluminiumhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Resistorhttp://en.wikipedia.org/wiki/Inductorhttp://en.wikipedia.org/wiki/Gyratorhttp://en.wikipedia.org/wiki/Boolean_algebra_(logic)http://en.wikipedia.org/wiki/State_(computer_science)http://en.wikipedia.org/wiki/Bipolar_transistor


26/67

random access memory is the most regular type of integrated circuitF the highest densityde"ices are thus memoriesF $ut e"en a microprocessor ill ha"e memory on the chip. @'ee theregular array structure at the $ottom of the first image.A lthough the structures are intricate S ith idths hich ha"e $een shrin)ing for decades S the layers remain much thinner than thede"ice idths. The layers of material are fa$ricated much li)e a photographic process, although

light a"es in the "isi$le spectrum cannot $e used to Pe>poseP a layer of material, as they ould $e too large for the features. Thus photons of higher fre%uencies @typically ultra"ioletA are usedto create the patterns for each layer. Because each feature is so small, electron microscopes areessential tools for a process engineer ho might $e de$ugging a fa$rication process.

Each de"ice is tested $efore pac)aging using automated test e%uipment @TEA, in a process)non as afer testing, or afer pro$ing. The afer is then cut into rectangular $loc)s, each of hich is called a die. Each good die @plural dice, dies, or dieA is then connected into a pac)ageusing aluminium @or goldA $ond ires hich are elded andGor Thermosonic Bonded to pads,usually found around the edge of the die. fter pac)aging, the de"ices go through final testing onthe same or similar TE used during afer pro$ing. Test cost can account for o"er 2: of the

cost of fa$rication on loer cost products, $ut can $e negligi$le on lo yielding, larger, andGor higher cost de"ices.

Pa08a"in"

The earliest integrated circuits ere pac)aged in ceramic flat pac)s, hich continued to $e used $y the military for their relia$ility and small sie for many years. Commercial circuit pac)aging%uic)ly mo"ed to the dual inline pac)age @#A, first in ceramic and later in plastic. #n the !970s pin counts of 16'# circuits e>ceeded the practical limit for # pac)aging, leading to pin gridarray @/A and leadless chip carrier @6CCA pac)ages. 'urface mount pac)aging appeared in theearly !970s and $ecame popular in the late !970s, using finer lead pitch ith leads formed aseither gulling or Olead, as e>emplified $y smalloutline integrated circuit a carrier hichoccupies an area a$out 80 S :0 less than an e%ui"alent #, ith a typical thic)ness that is

26

http://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Lighthttp://en.wikipedia.org/wiki/Wavehttp://en.wikipedia.org/wiki/Visible_spectrumhttp://en.wikipedia.org/wiki/Photonhttp://en.wikipedia.org/wiki/Ultraviolethttp://en.wikipedia.org/wiki/Electron_microscopehttp://en.wikipedia.org/wiki/Industrial_processhttp://en.wikipedia.org/wiki/Engineerhttp://en.wikipedia.org/wiki/Debugginghttp://en.wikipedia.org/wiki/Wafer_testinghttp://en.wikipedia.org/wiki/Die_(integrated_circuit)http://en.wikipedia.org/wiki/Goldhttp://en.wikipedia.org/wiki/Bond_wirehttp://en.wikipedia.org/wiki/Weldinghttp://en.wikipedia.org/wiki/Thermosonic_Bondinghttp://en.wikipedia.org/wiki/Dual_in-line_packagehttp://en.wikipedia.org/wiki/Pin_grid_arrayhttp://en.wikipedia.org/wiki/Pin_grid_arrayhttp://en.wikipedia.org/wiki/Leadless_chip_carrierhttp://en.wikipedia.org/wiki/Surface_mounthttp://en.wikipedia.org/wiki/Small-outline_integrated_circuithttp://en.wikipedia.org/wiki/Dual_in-line_packagehttp://en.wikipedia.org/wiki/File:RUS-IC.JPGhttp://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Lighthttp://en.wikipedia.org/wiki/Wavehttp://en.wikipedia.org/wiki/Visible_spectrumhttp://en.wikipedia.org/wiki/Photonhttp://en.wikipedia.org/wiki/Ultraviolethttp://en.wikipedia.org/wiki/Electron_microscopehttp://en.wikipedia.org/wiki/Industrial_processhttp://en.wikipedia.org/wiki/Engineerhttp://en.wikipedia.org/wiki/Debugginghttp://en.wikipedia.org/wiki/Wafer_testinghttp://en.wikipedia.org/wiki/Die_(integrated_circuit)http://en.wikipedia.org/wiki/Goldhttp://en.wikipedia.org/wiki/Bond_wirehttp://en.wikipedia.org/wiki/Weldinghttp://en.wikipedia.org/wiki/Thermosonic_Bondinghttp://en.wikipedia.org/wiki/Dual_in-line_packagehttp://en.wikipedia.org/wiki/Pin_grid_arrayhttp://en.wikipedia.org/wiki/Pin_grid_arrayhttp://en.wikipedia.org/wiki/Leadless_chip_carrierhttp://en.wikipedia.org/wiki/Surface_mounthttp://en.wikipedia.org/wiki/Small-outline_integrated_circuithttp://en.wikipedia.org/wiki/Dual_in-line_package


27/67

plained, patent and copyright protection for chip layouts, or topographies, ere largelyuna"aila$le. This led to considera$le complaint $y -.'. chip manufacturersRnota$ly, #ntel,hich too) the lead in see)ing legislation, along ith the 'emiconductor #ndustry ssociation@'#Aagainst hat they termed Pchip piracy.P

27

http://en.wikipedia.org/wiki/PQFPhttp://en.wikipedia.org/wiki/Thin_small-outline_packagehttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Land_grid_arrayhttp://en.wikipedia.org/wiki/Ball_grid_arrayhttp://en.wikipedia.org/w/index.php?title=Flip-chip_Ball_Grid_Array&action=edit&redlink=1http://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/System_In_Packagehttp://en.wikipedia.org/wiki/Multi-Chip_Modulehttp://en.wikipedia.org/wiki/Multi-Chip_Modulehttp://en.wikipedia.org/wiki/Surface_mount_technologyhttp://en.wikipedia.org/wiki/Semiconductor_Chip_Protection_Act_of_1984http://en.wikipedia.org/wiki/PQFPhttp://en.wikipedia.org/wiki/Thin_small-outline_packagehttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Land_grid_arrayhttp://en.wikipedia.org/wiki/Ball_grid_arrayhttp://en.wikipedia.org/w/index.php?title=Flip-chip_Ball_Grid_Array&action=edit&redlink=1http://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/System_In_Packagehttp://en.wikipedia.org/wiki/Multi-Chip_Modulehttp://en.wikipedia.org/wiki/Multi-Chip_Modulehttp://en.wikipedia.org/wiki/Surface_mount_technologyhttp://en.wikipedia.org/wiki/Semiconductor_Chip_Protection_Act_of_1984


28/67

!97 addition to -' la, the 'C, made all socalled mas) or)s @i.e., chip topographiesA protecta$le if registered ith the -.'. Copyright 5ffice. 'imilar rules apply in most other countries that manufacture #Cs. @This is a simplified e>planation see 'C for legal details.A

28

http://en.wikipedia.org/wiki/Mask_workhttp://en.wikipedia.org/wiki/Semiconductor_Chip_Protection_Act_of_1984http://en.wikipedia.org/wiki/Mask_workhttp://en.wikipedia.org/wiki/Semiconductor_Chip_Protection_Act_of_1984


29/67

Propo-ed 4or8

29


30/67

Propo-ed 4or8

#n the effort to in"estigate no"el and efficient delay fault testing algorithms and techni%ues,se"eral ideas on delay fault testing has $een e>plored. This dissertation addresses the folloing pro$lems on de"eloping no"el and efficient T/ and esignfortesta$ility @=TA algorithmsfor all three approaches for scan$ased delay testing.!. E>plosion in test data "olume and test application time2. 6oer fault delay fault co"erage8. ?igh comple>ity in delay fault T/. The o"ertesting pro$lem in scan$ased delay testing:. =unctional "s. scan$ased delay testing

(e first present to efficient transition fault T/ algorithms , in hich e computegood %uality transition test sets using stuc)at test "ectors. E>perimental results o$tained usingthe ne algorithms sho that there is a 20 reduction in test set sie compared to a stateoftheart nati"e transition test T/ tool, ithout losing fault co"erage. 5ther $enefits of our approach, "i. producti"ity impro"ement, constraint handling and design data compression arealso highlighted.

5ur second contri$ution is on the techni%ues to reduce data "olume and application timefor scan$ased transition test. (e propose a no"el notion of transition test chains to su$stitute thecon"entional transition pattern and com$ine this idea ith the TE repeat capa$ility to reducetest data "olume. Then a ne =T techni%ue for scan testing is presented to address the testapplication issue. 5ur e>perimental results sho that our techni%ue can impro"e $oth test data"olume and test application $y ;.: o"er a commercial T/ tool.

Thirdly, a no"el scan$ased delay test approach , referred to as the hy$rid delay scan, is proposed. The proposed scan$ased delay testing method com$ines ad"antages of the s)eedload and $roadside approaches. The hy$rid approach can achie"e higher delay fault co"eragethan the $roadside approach. -nli)e the s)eedload approach hose design re%uirement isoften too costly to meet due to the fast scan ena$le signal that must sitch in a full system cloc) cycle, the hy$rid delay scan does not re%uire a strong $uffer or $uffer tree to dri"e the fast scanena$le signal. ?ardare o"erhead added to standard scan designs to implement the hy$ridapproach is negligi$le. 'ince the fast scan ena$le signal is internally generated, no e>ternal pin isre%uired. Transition delay fault co"erage achie"ed $y the hy$rid approach transition as e%ual toor higher than that achie"ed $y the $roadside for all $enchmar) circuits. 5n an a"erage, ; a$out.: impro"ement in fault co"erage as o$tained $y the hy$rid approach o"er the $roadsideapproach.4e>t, e propose a ne concept of testing only functionally testa$le transition faults inBroadside Transition testing "ia a no"el constrained T/. #llegal @unreacha$leA states thatena$le detection of functionally untesta$le faults are first identified, and this set of undesira$le

illegal states is efficiently represented as a Boolean formula. 5ur constrained T/ then usesthis constraint formula to generate Broadside "ectors that a"oid those undesira$le states. #n doingso, our method efficiently generates a test set for functionally testa$le transition faults andminimies detection of functionally untesta$le transition faults. Because e ant to a"oidlaunching and propagating transitions in the circuit that are not possi$le in the functional mode, adirect $enefit of our method is the reduction of yield loss due to o"ertesting of these functionallyuntesta$le transitions.=inally, e proposed a ne approach on identifying functionally untesta$le

30


31/67

transition faults in nonscan se%uential circuits. ne dominance relationship for transitionfaults is formulated and used to identify more se%uentially untesta$le transition faults. The proposed method consists of to phasesH first, a large num$er of functionally untesta$letransition faults is identified $y a faultindependent se%uential logic implications implicitlycrossing multiple timeframes, and the identified untesta$le faults are classified into three

conflict categories. 'econd, additional functionally untesta$le transition faults are identified $ydominance relationships from the pre"ious identified untesta$le transition faults. Thee>perimental results for se%uential $enchmar) circuits shoed that our approach can %uic)lyidentify many more functionally untesta$le transition faults than pre"iously reported.#n short, the topics e ha"e in"estigated includeH!. Transition =ault T/ Based on 'tuc)at Test 1ectors2. Efficient Transition Testing using Test Chains and E>change 'can8. ?y$rid 'can$ased elay Testing. Constrained T/ for Broadside Transition Testing:. =unctional -ntesta$le Transition =aults #dentification

The rest of the dissertation is organied as follos. =irst, e gi"e a $rief re"ie of the

preliminaries on delay fault testing in Chapter 2. Then, a no"el transition fault T/ $ased onstuc)at test "ectors is discussed in Chapter 8. Chapter presents to techni%ues to further reduce the test data "olume and test application time for scan$ased transition test. #n Chapter :,a no"el scan$ased delay test approach, referred to as the hy$rid delay scan, is proposed.Then,e proposed a ne concept of testing only functionally testa$le transition faults inBroadside Transition testing "ia a no"el constrained T/ in Chapter ;. Chapter < presents ano"el approach to identify functional untesta$le transition faults using implication andtransitiondominance relationship. =inally, Chapter 7 concludes the dissertation.

31


32/67

!e-i"n ' !e;elopment

32


33/67

!e-i"n ' !e;elopment

4hat i- 1$!%=

1?6 is the 1?'#C ?ardare escription 6anguage. 1?'#C is an a$$re"iation for 1ery ?igh'peed #ntegrated Circuit. #t can descri$e the $eha"iour and structure of electronic systems, $ut is particularly suited as a language to descri$e the structure and $eha"iour of digital electronichardare designs, such as '#Cs and =/s as ell as con"entional digital circuits.

1?6 is a notation, and is precisely and completely defined $y the 6anguage eference *anual@ 6* A. This sets 1?6 apart from other hardare description languages, hich are to somee>tent defined in an ad hoc ay $y the $eha"iour of tools that use them. 1?6 is aninternational standard, regulated $y the #EEE. The definition of the language is nonproprietary.

1?6 is not an information model, a data$ase schema, a simulator, a toolset or a methodology?oe"er, a methodology and a toolset are essential for the effecti"e use of 1?6.

'imulation and synthesis are the to main )inds of tools hich operate on the 1?6 language.The 6anguage eference *anual does not define a simulator, $ut unam$iguously defines hateach simulator must do ith each part of the language.

1?6 does not constrain the user to one style of description. 1?6 allos designs to $edescri$ed using any methodology top don, $ottom up or middle out 1?6 can $e used todescri$e hardare at the gate le"el or in a more a$stract ay. 'uccessful high le"el designre%uires a language, a tool set and a suita$le methodology. 1?6 is the language, you choosethe tools, and the methodology... ell, # guess thatMs here oulos come in to the e%uation

33


34/67

The Requirement

The de"elopment of 1?6 as initiated in !97! $y the -nited 'tates epartment of efence to

address the hardare life cycle crisis. The cost of reprocuring electronic hardare astechnologies $ecame o$solete as reaching crisis point, $ecause the function of the parts as notade%uately documented, and the "arious components ma)ing up a system ere indi"idually"erified using a ide range of different and incompati$le simulation languages and tools. There%uirement as for a language ith a ide range of descripti"e capa$ility that ould work the same on any simulator and as independent of technology or design methodology.

Standardi>ation

The standardiation process for 1?6 as uni%ue in that the participation and feed$ac) fromindustry as sought at an early stage. $aseline language @"ersion


35/67

#enefit- of u-in" 1$!%

E@e0utable -pe0ifi0ation

#t is often reported that a large num$er of '#C designs meet their specifications first time, $utfail to or) hen plugged into a system. 1?6 allos this issue to $e addressed in to aysH 1?6 specification can $e e>ecuted in order to achie"e a high le"el of confidence in itscorrectness $efore commencing design, and may simulate one to to orders of magnitude faster than a gate le"el description. 1?6 specification for a part can form the $asis for a simulationmodel to "erify the operation of the part in the ider system conte>t @eg. printed circuit $oardsimulationA. This depends on ho accurately the specification handles aspects such as timing andinitialiation.

Beha"ioural simulation can reduce design time $y alloing design pro$lems to $e detected earlyon, a"oiding the need to reor) designs at gate le"el. Beha"ioural simulation also permits designoptimiation $y e>ploring alternati"e architectures, resulting in $etter designs.

Tool-

1?6 descriptions of hardare design and test $enches are porta$le $eteen design tools, and porta$le $eteen design centres and project partners. Uou can safely in"est in 1?6 modellingeffort and training, )noing that you ill not $e tied in to a single tool "endor, $ut ill $e free to preser"e your in"estment across tools and platforms. lso, the design automation tool "endorsare themsel"es ma)ing a large in"estment in 1?6, ensuring a continuing supply of stateoftheart 1?6 tools.

Te0hnolo"(

1?6 permits technology independent design through support for top don design and logicsynthesis. To mo"e a design to a ne technology you need not start from scratch or re"erseengineer a specification instead you go $ac) up the design tree to a $eha"ioural 1?6description, then implement that in the ne technology )noing that the correct functionalityill $e preser"ed.

#enefit-

• E>ecuta$le specification

• 1alidate spec in system conte>t @'u$contractA

• =unctionality separated from implementation

• 'imulate early and fast @*anage comple>ityA

• E>plore design alternati"es

• /et feed$ac) @roduce $etter designsA

35


36/67

• utomatic synthesis and test generation @T/ for '#CsA

• #ncrease producti"ity @'horten timetomar)etA

• Technology and tool independence @though =/ features may $e une>ploitedA

•

orta$le design data @rotect in"estmentA

!e-i"n &lo u-in" 1$!%

The diagram $elo summaries the high le"el design flo for an '#C @ie. gate array, standardcellA or =/. #n a practical design situation, each step descri$ed in the folloing sections may $e split into se"eral smaller steps, and parts of the design flo ill $e iterated as errors areunco"ered.

S(-tem


37/67

%oo8ploratory synthesis ill $e done early on in the design process, to pro"ideaccurate speed and area data to aid in the e"aluation of architectural decisions and to chec) theengineerMs understanding of ho the 1?6 ill $e synthesied, the main synthesis production

run is deferred until functional simulation is complete. #t is pointless to in"est a lot of time andeffort in synthesis until the functionality of the design is "alidated.

5B of de-i"n time at RT%

4hat i- the differen0e beteen 1$!% and 1erilo"=

=undamentally spea)ing, not a lot. Uou can produce ro$ust designs and comprehensi"e testen"ironments ith $oth langauges, for $oth '#C and =/. ?oe"er, the to langaugesapproach the tas) from different directionsF 1?6, intended as a specification langauge, is "erye>act in its nature and hence "ery "er$ose. 1erilog, intended as a simulation langauge, it muchcloser to C in style, in that it is terse and elegant to rite $ut re%uires much more care to a"oidnasty $ugs. 1?6 doesnMt let you get aay ith muchF 1erilog assumes that hate"er you roteas e>actly hat you intended to rite. #f you get a 1?6 architecture to compile, itMs pro$a$lygoing to appro>imate to the function you anted. =or 1erilog, successful compilation merelyindicates that the synta> rules ere met, nothing more. 1?6 has some features that ma)e it

good for systemle"el modelling, hereas 1erilog is much $etter than 1?6 at gatele"elsimulation. To confuse the situation more, see 'ystem1erilog...

O;er;ie of ISE

37


38/67

#'E controls all aspects of the design flo. Through the roject 4a"igator interface, you canaccess all of the design entry and design implementation tools. Uou can also access the files anddocuments associated ith your project. roject 4a"igator #nterface The roject 4a"igator #nterface, $y default, is di"ided into four panel su$indos, as seen 5n the top left is the

esign, =iles and 6i$raries panels hich include display and access to the source files in the project, as ell as access to running processes for the currently selected source. t the $ottom of the roject 4a"igator is the Console, Errors and (arnings panels hich display status messages,errors, and arnings. To the right is a multidocument interface @*#A indo referred to as the(or)space. #t ena$les you to "ie design reports, te>t files, schematics, and simulationa"eforms. Each indo may $e resied, undoc)ed from roject 4a"igator, mo"ed to a nelocation ithin the main roject 4a"igator indo, tiled, layered, or closed. anels may $eopened or closed $y using the 1ie


39/67

39


40/67

40


41/67

Implementation

Implementation41


42/67

1$!% PROGRAMS &OR 1ARIOUS %OGIC CIRCUITS

4 gate to descriptions pro"ided

li$rary ieeeFuse ieee.stdDlogicD!!;.allF

entity 4Dent is port@ >H in stdDlogicF

yH in stdDlogicF=H out stdDlogic

AFend 4DentF

architecture $eha"! of 4Dent is $egin

process@>, yA $egin compare to truth ta$le if @@>VM!MA and @yVM!MAA then

= WV M!MFelse = WV M0MFend ifF

end processF

end $eha"!F

architecture $eha"2 of 4Dent is $egin

= WV > and yF

end $eha"2F

5 gate

42


43/67

to descriptions pro"ided




AFend 5DentF

architecture 5Darch of 5Dent is $egin

process@>, yA

$egin compare to truth ta$le if @@>VM0MA and @yVM0MAA then

= WV M0MFelse = WV M!MFend ifF

end processF

end 5DarchF

architecture 5D$eh of 5Dent is $egin

= WV > or yF

end 5D$ehF

43


44/67





AFend 44DentF

architecture $eh"! of 44Dent is

$egin

process@>, yA $egin compare to truth ta$le if @>VM!M and yVM!MA then


end processF

end $eh"!F

architecture $eh"2 of 44Dent is $egin

= WV > nand yF

end $eh"2F

44


45/67





AFend 45DentF

architecture $eh"! of 45Dent is

$egin

process@>, yA $egin compare to truth ta$le

if @>VM0M and yVM0MA then = WV M!MF

else = WV M0MFend ifF

end processF

end $eh"!F

architecture $eh"2 of 45Dent is $egin

= WV > nor yF

end $eh"2F

5 gate

45


46/67

to descriptions pro"ided




AFend 5DentF

architecture 5Darch of 5Dent is $egin

process@>, yA

$egin compare to truth ta$le if @@>VM0MA and @yVM0MAA then


end processF

end 5DarchF

architecture 5D$eh of 5Dent is $egin

= WV > or yF

end 5D$ehF

46


47/67

L5 gate to descriptions pro"ided

li$rary ieeeF

use ieee.stdDlogicD!!;.allF

entity L5Dent is port@ >H in stdDlogicF


AFend L5DentF

architecture $eh"! of L5Dent is $egin

process@>, yA $egin compare to truth ta$le

if @>GVyA then = WV M!MF

else = WV M0MFend ifF

end processF

end $eh"!F

architecture $eh"2 of L5Dent is $egin

= WV > >or yF

end $eh"2F

47


48/67


49/67

Com$inational 6ogic esign simple e>ample of 1?6 'tructure *odeling e might define to components in to separate files, in main file, e use port map statement to instantiate the mapping relationship $eteen each components and the entire circuit.

li$rary ieeeF component X!use ieee.stdDlogicD!!;.allF

entity 5D/TE is port@ LH in stdDlogicF

UH in stdDlogicF=2H out stdDlogic

AF

end 5D/TEF

architecture $eh" of 5D/TE is $egin process@L,UA $egin

=2 WV L or UF $eha"ior des.end processFend $eh"F

li$rary ieeeF component X2

use ieee.stdDlogicD!!;.allF

entity 4D/TE is port@ H in stdDlogicF

BH in stdDlogicF=!H out stdDlogic

AFend 4D/TEF

architecture $eh" of 4D/TE is $egin process@,BA $egin

=! WV and BF $eha"ior des.end processFend $eh"F

li$rary ieeeF top le"el circuituse ieee.stdDlogicD!!;.allF

49


50/67

use or).allF

entity com$Dc)t is port@ input!H in stdDlogicF

input2H in stdDlogicFinput8H in stdDlogicF

outputH out stdDlogicAFend com$Dc)tF

architecture struct of com$Dc)t is

component 4D/TE is as entity of 4D/TE port@ H in stdDlogicF BH in stdDlogicF =!H out stdDlogic AF end componentF

component 5D/TE is as entity of 5D/TE port@ LH in stdDlogicF UH in stdDlogicF =2H out stdDlogic AF end componentF

signal ireH stdDlogicF signal just li)e ire

$egin

use sign PVYP to clarify the pin mapping

/ate!H 4D/TE port map @VYinput!, BVYinput2, =!VYireAF /ate2H 5D/TE port map @LVYire, UVYinput8, =2VYoutputAF

end structF

50


51/67


52/67

=ig. ! S$asic gates for half adder

52


53/67

=ig.2 logic circuit for half adder

53


54/67

=ig. 8 initial timing and cloc) iard

54


55/67

=ig. schematic editor for half adder

55


56/67


57/67

!etailed Report- st 6.88 @ntACopyright @cA !99:2009 Lilin>, #nc. ll rights reser"ed.Y arameter T*# set to >stGprojna".tmp

Total E6 time to Lst completionH 0.00 secsTotal C- time to Lst completionH 0.88 secsY arameter >sthdpdir set to >stTotal E6 time to Lst completionH 0.00 secsTotal C- time to Lst completionH 0.88 secsY eading designH 4Dent.prjTB6E 5= C54TE4T'!A 'ynthesis 5ptions 'ummary2A ?6 Compilation8A esign ?ierarchy nalysisA ?6 nalysis

:A ?6 'ynthesis:.!A ?6 'ynthesis eport;A d"anced ?6 'ynthesis;.!A d"anced ?6 'ynthesis eport


58/67

9.2A artition esource 'ummary9.8A T#*#4/ E5TVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ 'ynthesis 5ptions 'ummary Z

VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV 'ource arameters#nput =ile 4ame H P4Dent.prjP#nput =ormat H mi>ed#gnore 'ynthesis Constraint =ile H 45 Target arameters5utput =ile 4ame H P4DentP5utput =ormat H 4/CTarget e"ice H >c"l>!:!2sf8;8 'ource 5ptions

Top *odule 4ame H 4Dentutomatic ='* E>traction H UE'='* Encoding lgorithm H uto'afe #mplementation H 4o='* 'tyle H lut* E>traction H Ues* 'tyle H uto5* E>traction H Ues*u> 'tyle H utoecoder E>traction H UE'riority Encoder E>traction H UE''hift egister E>traction H UE'6ogical 'hifter E>traction H UE'L5 Collapsing H UE'5* 'tyle H uto*u> E>traction H UE'esource 'haring H UE'synchronous To 'ynchronous H 45-se ' Bloc) H autoutomatic egister Balancing H 4o Target 5ptionsdd #5 Buffers H UE'dd /eneric Cloc) Buffer@B-=/A H 82 4um$er of egional Cloc) Buffers H !;egister uplication H UE''lice ac)ing H UE'5ptimie #nstantiated rimiti"es H 45-se Cloc) Ena$le H uto-se 'ynchronous 'et H uto-se 'ynchronous eset H uto

58


59/67

ac) #5 egisters into #5Bs H autoE%ui"alent register emo"al H UE' /eneral 5ptions5ptimiation /oal H 'peed5ptimiation Effort H !

oer eduction H 456i$rary 'earch 5rder H 4Dent.lso3eep ?ierarchy H 45 4etlist ?ierarchy H asDoptimiedT6 5utput H Ues/lo$al 5ptimiation H llCloc)4etsead Cores H UE'(rite Timing Constraints H 45Cross Cloc) nalysis H 45?ierarchy 'eparator H GBus elimiter H WY

Case 'pecifier H maintain'lice -tiliation atio H !00B* -tiliation atio H !00'7 -tiliation atio H !001erilog 200! H UE'uto B* ac)ing H 45'lice -tiliation atio elta H :VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ ?6 Compilation ZVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVCompiling "hdl file P?HG4e =olderG4Dgate."hdP in 6i$rary or).Entity W4DentY compiled.Entity W4DentY @rchitecture W$eha"!YA compiled.Entity W4DentY @rchitecture W$eha"2YA compiled.VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ esign ?ierarchy nalysis ZVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVnalying hierarchy for entity W4DentY in li$rary Wor)Y @architecture W$eha"2YA.VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ ?6 nalysis ZVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVnalying Entity W4DentY in li$rary Wor)Y @rchitecture W$eha"2YA.

59


60/67

Entity W4DentY analyed. -nit W4DentY generated.VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ ?6 'ynthesis ZVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV

VVVVerforming $idirectional port resolution...'ynthesiing -nit W4DentY.elated source file is P?HG4e =olderG4Dgate."hdP.-nit W4DentY synthesied.VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV?6 'ynthesis eport=ound no macroVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV

VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ d"anced ?6 'ynthesis ZVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVd"anced ?6 'ynthesis eport=ound no macroVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ 6o 6e"el 'ynthesis ZVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV5ptimiing unit W4DentY ...*apping all e%uations...Building and optimiing final netlist ...=ound area constraint ratio of !00 @[ :A on $loc) 4Dent, actual ratio is 0.=inal *acro rocessing ...VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV=inal egister eport=ound no macroVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ artition eport Z

60


61/67

VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVartition #mplementation 'tatus 4o artitions ere found in this design.

VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVZ =inal eport ZVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV=inal esultsT6 Top 6e"el 5utput =ile 4ame H 4Dent.ngr Top 6e"el 5utput =ile 4ame H 4Dent5utput =ormat H 4/C5ptimiation /oal H 'peed

3eep ?ierarchy H 45esign 'tatisticsX #5s H 8Cell -sage HX BE6' H !X 6-T2 H !X #5 Buffers H 8X #B-= H 2X 5B-= H !VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVe"ice utiliation summaryH'elected e"ice H "l>!:sf8;8!2 4um$er of 'licesH ! out of ;! 0 4um$er of input 6-TsH ! out of !2277 0 4um$er of #5sH 8 4um$er of $onded #5BsH 8 out of 20 !artition esource 'ummaryH 4o artitions ere found in this design.VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVT#*#4/ E5T 45TEH T?E'E T#*#4/ 4-*BE' E 546U 'U4T?E'#' E'T#*TE.=5 CC-TE T#*#4/ #4=5*T#54 6E'E E=E T5 T?E TCE E5T/E4ETE =TE 6CEand5-TE.Cloc) #nformationH

61


62/67

4o cloc) signals found in this designsynchronous Control 'ignals #nformationH 4o asynchronous control signals found in this design

Timing 'ummaryH'peed /radeH !2*inimum periodH 4o path found*inimum input arri"al time $efore cloc)H 4o path found*a>imum output re%uired time after cloc)H 4o path found*a>imum com$inational path delayH .7:7nsTiming etailHll "alues displayed in nanoseconds @nsAVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV

VVVVTiming constraintH efault path analysisTotal num$er of paths G destination portsH 2 G !elayH .7:7ns @6e"els of 6ogic V 8A'ourceH > @AestinationH = @Aata athH > to =/ate 4etCellHinYout fanout elay elay 6ogical 4ame @4et 4ameA #B-=H#Y5 ! 0.D#B-= @>D#B-=A6-T2H#0Y5 ! 0.!< 0.2;; =! @=D5B-=A5B-=H#Y5 8.2:: =D5B-= @=ATotal .7:7ns @.!:;ns logic, 0.


63/67

elease !!.! ngd$uild 6.88 @ntACopyright @cA !99:2009 Lilin>, #nc. ll rights reser"ed.Command 6ineH CH\Lilin>\!!.!\#'E\$in\nt\unrapped\ngd$uild.e>e ise and.iseintstyle ise dd Dngo nt timestamp i p >c"l>!:sf8;8!2 4Dent.ngc4Dent.ngd

eading 4/5 file PCHGLilin>G!!.!G#'EGandG4Dent.ngcP .../athering constraint information from source properties...one.esol"ing constraint associations...Chec)ing Constraint ssociations...one...Chec)ing artitions ...Chec)ing e>panded design ...artition #mplementation 'tatus 4o artitions ere found in this design.

4/B-#6 esign esults 'ummaryH 4um$er of errorsH 0 4um$er of arningsH 0Total memory usage is 9::77 )ilo$ytes(riting 4/ file P4Dent.ngdP ...Total E6 time to 4/B-#6 completionH 9 secTotal C- time to 4/B-#6 completionH 7 sec(riting 4/B-#6 log file P4Dent.$ldP...

63


64/67

Con0lu-ion ' &uture 4or8

Con0lu-ion ' &uture 4or8

(ith the rapid ad"ances in integrated circuit technology, it is possi$le to fa$ricate digital circuitith large no. of de"ices in a single "lsi chip. The increase in sie and comple>ity of circuit

64


65/67

placed on a chip, ith little or no increase in no. of #G5 pins, drastically reduces thecontrolla$ility and o$ser"a$illity of logic on chip. 'ince 16'# engineering has $een used in iderange of application, the need for testing is $ecoming more and more important.The test generation for se%uential circuit has $een recognied as a difficult pro$lem. differentapproaches ha"e $een used to deal ith the testing the testing pro$lem, either $y randomly

generating test se%uences or $y using deterministic test generation methods.The e>isting test generating algorithms for se%uential circuit can generate test se%uences for large se%uential circuits. ?oe"er, ith increasing circuit comple>ity, either test generation timeincreases e>ponentially, either test generation time increases e>ponentially or it cannot producetest se%uences due to the e>ponential increase of reacha$le states.#n this dissertation, e propose a ne approach for designing test generation algorithms ith $etter time comple>ity and fault co"erage. glo$al search approach has $een de"eloped for thetest generation of large se%uential circuits. The approach justifies a fault at a primary output or ne>t state line order to trace different sensiti"e paths from the primary inputs and present statelines to the primary output or ne>t state line. uring the glo$al test generation process. *anyfaults are considered as candidates to $e tested simultaneously.

65


66/67

#iblio"raph(

#iblio"raph(

66


67/67

M !"#!M$%ICI& M ! "#''#& and ! *#I'M!+ igital

Systems ,esting and ,estable esign Computer Science '-press&

.//0

% !1#!2!3 and S , C4!5#!4!# Combinational !,P1

,heorems for Identifying untestable faults in synchronous Se6uential Circuits I''' ,rans on Computer7!ided esign of Integrated Circuit

and System& %ol .8(/)9..::;..!+& and 5 5$=MI+S5I Combinational Profiles

of Se6uential "enchmark Circuits In Proceedings I''' International

Symposium on Circuits and Systems& ./?/

"#!+ and % S I>'+1!# Identification of #edundant elay

*aults I''' ,rans on Computer7!ided esign of Integrated Circuit

and System& %ol .@(:)9::@;: .//8

"'3','& ! #!=!+& 2 SC42!#=& # #!I+!&C 4!25I+S& and A M$#'4'! se of *, ,echni6ues

In Speed 1rading a .14zB Microprocessor In Proceedings I'''

International ,est Conference& pages ....;.../& 00

S , C4!5#!4!# and % !1#!2!3 ! transitive closure

algorithm for test generation I''' ,rans on Computer7!ided esignof Integrated Circuit and System& %ol .(D)9.0.:;.0?& A3> .//@

! C4!+#! and 5 C4!5#!"!#,> *re6uency irected #un 3ength(*#) Codes with !pplication to System on a Chip ata Compression

In Proceedings %3SI ,esting Symposium& pages 8;8D&

00.

57, C4'+1 ,ransition *ault ,esting for Se6uential Circuits I'''

,rans on Computer7!ided esign of Integrated Circuit and System&

projec report.doc

Documents