Project 1

Part 1a Design a 4-to-1 multiplexor that uses 8-bit buses on the inputs (instead of single bits). The output will be a single 8-bit bus.

Design:To design my 8 bit 4-to-1 mux I used

- 2to4 decoder- 4x2 AND-OR- 4to1 mux

The schematics to these are below.2-to-4 DECODERI used 2 inversters, and 4 “2AND”gates.Inputs - a0,a1Outpiuts – D0,D1,D2,D3

4 x 2 AND-ORI used 4 “2AND” and 1 “4OR” gate. Inputs are a0, a1, a2, a3, b0, b1, b2, b3. And the only output is c.

Using these parts I can construct a 4-to-1 multiplexor that uses 8-bit buses.8 bit 4x2 AND-OR

The above circuit consists of 8 “4-to-2 AND-ORs”. The input is 4 8bit values and a, b, c, d selectors. The output is an 8 bit value. I used 8bit expanders to take the input and traverse through the circuit. While on the other end I used a merger of 8 bit to output the 8 bit value.

Using a decoder I can have 2 select bits which is needed for my 4-to-1 multiplexer. 2^n = 4, n = 2. So we need 2 selectors.Implementing the decoder and my 8 4x2 AND-OR I get my mux.Part 1a (8 bit 4-to-1 multiplexer)Gates: Previous 8bit 4 x 2 AND-OR also the 2-4 decoder from the previous page.You input s0, s1 and 4 8bit values in i0-i3. Output is an 8bit value.This confirms the gates in the circuit are indeed working and the 8 bit inputs are passing through correctly.

To verify I use the waveform and vary the inputs to ensure that all of the signals of the 8 bit inputs have passed all the way through the 4 x2 AND-OR gates, this is successful making my multiplexer valid.

Part 1bBuild an 8 bit adder.

Design: To create this adder I first created a full adder using 2 half adders. Full adders do bit/binary addition, so the output is the sum well as a carry bit. Details schematics are on the next page.

HALF ADDER; simply put this uses a 2XOR gate and a 2AND gate with the inputs x,y and outputs the sum s and carry bit c.

FULL ADDER; just 2 half adders, all to a 2OR.Inputs are x,y,z outputs are just the same sum and carry bit.

This circuit will be used multiple times for my 8 bit adder. To verify this circuit works when x = 1, y=0, z=0; s should be 1 and c shoul Part 1d (8-bit adder) d be 0 on the ouput. As you can see in the diagram above this is successful. WAVEFORMS BELOW> To test the funcationality of this full adder we can simply let bit x be 1. And to test the carry bit one of the half adders have to produce a carry. Or 2 of the inputs have to be 1.When x = 1. (n0) n2 which is sum bit is 1.

2 inputs 1. In this n3 and n0 are my inputs and n7 is my carry.

Part 1b (8-bit adder)Finally, my 8 bit adder, using 8 full adders, 2 vertical expanders 1 merger.Therefore the inputs are 2 8 bit buses essentially and output is just one 8 bit bus and the carry.

To verify that this adder is indded functional I use three simple test cases. When both bytes are 0, and when both bytes add up to a number less then 255, and finally when they exceed the 255 limit and give a carry output. This is shown below using a waveform.N27 IS CARRY BITN35 IS SUM BITN1 and N4 are 8 bit inputs.When both are 0 n35(sum) is 0

When both are 126 and 129 the sum bit is 255.

When both add up to 255 or greater. You see when I change n4 to 127 the sum becomes 255 which makes n27 1 which is the carry bit and the sum bit is 0.

ReferenceMano, M. M., & Kime, C. R. (2004). Logic Computer Design Fundamentals. New Jersey:Pearson Prentice Hall.Project 1Part 1

Part 1A: To create an 8 bit 4-to-1 multiplexerA 8 bit 4-to-1 multiplexer is useful passing values through using 2 select bits. To make a 8 bit 4-to-1 multiplexer I used a 2-4 decoder and an 8 4x2 AND-OR. The decoder takes in the 2 select bits and gives out 4. Those 4 bits are used to AND each 8 bit buffer.

1AI: 2-4 decoderGates used: 2 INV, 4 2ANDInputs: i1, i0Outputs: a, b, c, d

Tested on all inputs(4)i1 (n0) i0(n1) a(n4) b(n5) c(n6) d(n7)

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

The values obtained in the waveform match the truth table, so this means that the circuit is working correctly.

1AII: 4x2 AND-ORGates used: 4 2AND, 1 4ORInputs: a0, a1, a2, a3, b0, b1, b2, b3Outputs: Z

1AIII: 8 4x2 AND-ORGates used: 8 4x2 AND-ORsInputs: A, B, C, D,

8 bit buffers I0, I1, I2, I3

Outputs: 8 bit buffer Z

1AIV: 8 bit 4-to-1 multiplexerGates used: 2-4 decoder, 8 4x2 AND-ORInputs: s0, s1

8 bit buffers i0, i1, i2, i3Outputs: 8 bit buffer Z

Part 1B: To create an 8 bit adderAn 8 bit adder adds two 8 bits buffers. It adds the two corresponding bits of each buffer. Such as 00000001+00000010. Which is 00000011. As you can see it adds by separating the buffer into every bit, and then does the same for the other buffer and adds the two bits which are of the same 2n place. If the sum is greater than 255, then the carry bit is flipped. An 8 bit adder can be created using 8 full adders.

1BI: Full adderGates used: 2 2XOR, 4 2AND, 1 2ORInputs: X,Y,ZOutputs: S, C

1BII: 8 bit AdderGates used: 8 full addersInputs: 8 bit Buffers A and B, VCCOutputs: 8 bit buffer S, C

CS 266 Part 2

Part 2: An 8 bit ALU is used to perform a set of basic arithmetic and logic micro operations. It does this by using a 3 bit bus as selection bits to choose the appropriate operation. It decodes the selection bits making it possible to do 8 different tasks. The ALU is composed of two primary parts. The Arithmetic circuit and the Logic circuit. Each take inputs A, B, alu_sel. The Arithmetic circuit also takes in c_in. The Following table shows the actions of the ALU.

Part 1: The Logic CircuitThe Logic circuit will be used to perform the tasks based on the alu_sel. Because alu_sel1 is always 0 when the Logic Circuit is needed, we can disregard the bit and only use alu_sel0 and alu_sel2 to choose

the desired operation.The Logic Circuit will be able to perform 4 different logic operations. NOT, OR, XOR, and AND.

Part a: 8bit-ORinputs: Two 8 bit buses A and Boutput: 8 bit bus Ycomposed of 8 OR's, two expanders, and a merger

To test the 8bit-OR we see the wave form.

Part b: 8bit-invinputs: One 8bit bus Aoutputs: Ycomposed of 8 inv, one expanders, and a merger

The wave form shows that it works properly

This is because when A is 255 Y is 0, meaning that every bit was negates. The same is true forwhen A is 0 since Y now becomes 255.

Part c: 8bit XORinputs: Two 8 bit buses A and Boutput: 8 bit bus Ycomposed of 8 XORs, two expanders, and a merger

The wave forms show that this circuit works because when both A and B are the same the out put is zero, the same way a XOR works.

part d: 8bit-ANDinputs: Two 8 bit buses A and Boutput: 8 bit bus Ycomposed of 8 ANDS, two expanders, and a merger

The following waves show that the AND works.

part e: 8bit-4-1muxThis is the same mux from part 1

To make the Logic circuit we simply pass the values of the logic gates to the mux. The select bits for

the mux are just alu_sel0 and alu_sel2. This is because the Logic circuit performs four tasks, and only 2 bits are needed to select the tasks from the mux, also aul_sel0 is always 0 when the Logic circuit is outputted.

Since we know that the 8bit logic gates that we made work as desired, to check if the Logic circuit works, we just have to check to see if the aul_sel bits are selecting the correct operation to pass to the out put of the Logic circuit.

A B aul_sel ORy INVy XORy ANDy Y

3 5 0 0 0 7 252 6 1 7

3 5 0 0 1 7 252 6 1 252

3 5 0 1 0 7 252 6 1 7

3 5 0 1 1 7 252 6 1 252

3 5 1 0 0 7 252 6 1 6

3 5 1 0 1 7 252 6 1 1

3 5 1 1 0 7 252 6 1 6

3 5 1 1 1 7 252 6 1 7The table shows how when alu_sel is set for the Logic circuit, the Y is the output corresponding to the operations in the ALU action table, there fore it works correctly.

Part 2: The Arithmetic CircuitThe Arithmetic Circuit is used to do various arithmetic operations to A and B. Depending on the

selection bits alu_sel, the Arithmetic Circuit will do a different task. Because alu_sel1 is always 1 when the circuit is needed, we can disregard the bit and only use alu_sel0 and alu_sel2 to choose the desired operation. Using 2 bits will only give us 4 possible operations, but the use of c_in as a carry bit input allows us to be able to do 8 different operations for the circuit. The Arithmetic Circuit takes in A, B, aul_sel, and c_in.

To design my circuit I used

8bit 4to1 MUX, design is above, (part 1a, Amar Patel)

8bit INV

4, 8-bit adders with carry, overflow, sum outputs (description above, Patel)

2 1-bit 4to1 mux’s

To account for the new parameter that checks overflow I edited my (Patel) 8bit full adder to output v, the overflow bit. You can view previous adder from submission 1.

Here is my new full adder; I used an XOR on the carry bit outputs of the last 2 full-adders.

The ALU:Now that both components of the ALU are made we can combine both to form a working ALU. To do this we used the Logic Circuit, the Arithmetic Circuit and used other gates to output the sign bit if the operation uses a signed number. We also used other gates to choose whether the output should be that of the Logic Circuit or of the Arithmetic Circuit.

Parts: Logic Circuit, Arithmetic Circuit, 8bit 4-1 mux, one 3AND gates, one 2OR gate, three 2AND gate, 1 3 bit expander, 1 8 bit expander , and one 8 bit merger

This table shows the inputs of the ALU

As you can see from the design, we AND the enable with all the single bit out puts. Although this means that the ALU still does computations, putting the enable at the end causes no problems with any of the parts. To determine which output(either the out put of the Logic Circuit or the Arithmetic Circuit) will pass to M we used an 8bit 4-1 mux. We use alu_sel1 to select between the two by using it as the s1 select bit of the mux. When it is 1, the output of the Arithmetic Circuit passes through. When it is 0, the value of the Logic Circuit passes through. The last two inputs of the mux(i2 and i3) are connected to ground, this with the enable bit connected to the s0 select bit of the mux makes it possible to pass zero

when enable is not selected. The m7 or the sign bit if the operation calls for sign numbers is produced by using the alu_sel,

according to the different selects when alu_sel is 2 or 6, we have a signed number as our output, so m7 will just be the most significant bit, when alu_sel is 2 OR 6. Which is exactly what I implemented to account for this. I OR both when alu_sel is 2,6 then use that to AND both the most significant bit. The carry bit is produced using the adders, explained above and in the part1 of project, this AND the enable would simply produce the carry bit.

Using the waveform, we constructed the table to show that our ALU does in fact work according to the specified operations requested.

A B alu_sel enable c_in M v m7 c_out

151 162 0 0 0 183 0 0 0

151 162 1 0 0 104 0 0 1

151 162 2 0 0 244 1 1 0

151 162 2 0 1 245 0 1 0

151 162 3 0 0 58 0 0 1

151 162 3 0 1 57 1 0 1

151 162 4 0 0 53 1 0 1

151 162 5 0 0 130 0 0 0

151 162 6 0 0 150 0 1 1

151 162 6 0 1 151 0 1 1

151 162 7 0 1 152 0 0 0

151 162 7 0 0 151 0 0 0

151 162 7 1 0 0 0 0 0