project phase 1 done – thanks for the timely response...

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EE141 EECS141 1 Lecture #16


  Project Phase 1 Done – Thanks for the timely response.

  Phase 2 to be announced We – Launched on Fr.

  Hw 6 due on Fr.

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 Last lecture   Pass transistor logic  CMOS Layout

 Today’s lecture  Ratioed Logic  Dynamic Logic

 Reading (Ch 6)


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Goal: build gates faster/smaller than static complementary CMOS

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  Rising and falling delays aren’t the same   Calculate LE for the two edges separately

  For tpLH:   Cgate = WCG Cinv = (3/2)WCG LELH =


  What is LE for tpHL?   Switch model would predict Reff = Rn||Rp

  Would that give the right answer for LE?

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  Time constant is smaller, but it takes more time to complete 50% VDD transient (arguably)   Rp actually takes some current away from

discharging C

vo(t)/VDD

t

Rp=Rn

Rp=2Rn

Rp=4Rn

Rp=∞


  Think in terms of the current driving Cload

  When you have a conflict between currents   Available current is the difference between the two

  In pseudo-nMOS case:

  (Works because Rp >> Rn for good noise margin)

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  For tpHL (assuming Rsqp = 2Rsqn):   Rgate = Rn/(1-Rn/Rp) = 2Rn Rinv = Rn

  Cgate = WCG Cinv = 3WCG

  LEHL =   LE is lower than an inverter!

  But have static power dissipation…


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Differential Cascode Voltage Switch Logic (DCVSL)


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XOR/XNOR gate

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  In static circuits, at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.   fan-in of n requires 2n (n N-type + n P-type)

devices

  Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.   only requires n + 2 (n+1 N-type + 1 P-type)

transistors

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In1

In2 PDN

In3

Me

Mp

Clk

Clk

Out CL

Out

Clk

Clk

A

B

C

Mp

Me

Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

on

off

1

off

on

((AB)+C)


  Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.

  Inputs to the gate can make at most one transition during evaluation.

  Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

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  Logic function is implemented by the PDN only   number of transistors is N + 2 (versus 2N for static complementary

CMOS)

  Full swing outputs (VOL = GND and VOH = VDD)   Non-ratioed - sizing of the devices does not affect

the logic levels   Faster switching speeds

  reduced capacitance due to lower input capacitance (Cin)   no Isc, so all the current provided by PDN goes into discharging CL


In

Clk

Clk

Out CL

Cgate = LE =

A

Clk

Clk

Out CL

B

Cgate = LE =

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  Overall power dissipation usually higher than static CMOS   no static current path ever exists between VDD and GND

(including Psc)   no glitching   higher transition probabilities   extra load on Clk

  PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn   low noise margin (NML)

  Needs a precharge/evaluate clock


CL

Clk

Clk

Out

A

Mp

Me

Leakage sources

CLK

VOut

Precharge

Evaluate

Dominant component is subthreshold current

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CL

Clk

Clk

Me

Mp

A

B

Out

Mkp

Same approach as level restorer for pass-transistor logic

Keeper


CL

Clk

Clk

Me

Mp

A Out

Mkp

Out

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CL

Clk

Clk

CA

CB

B=0

A

Out Mp

Me

  Charge initially stored on CL   CA previously discharged

  When A rises, this charge is redistributed (shared) between CL and CA

  Makes Out drop below VDD


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B = 0

Clk

X

C L

C a

C b

A

Out M p

M a

V DD

M b

Clk M e

•  Two cases: •  Ma stays on – complete charge share •  Ma turns off – incomplete charge share

• Complete charge share: •  QCa = VOutCa

ΔQCL = -VOutCa

ΔVOut = -VDDCa/(Ca+CL)

• Incomplete charge share: •  QCa = (VDD-VTN*)Ca ΔQCL = -(VDD-VTN*)Ca

ΔVOut = -(VDD-VTN*)Ca/CL


Clk

Clk

Me

Mp

A

B

Out Mkp

Clk

•  Keeper helps a lot •  Can still get failures if Out drops below inverter Vsw

•  Another option: precharge internal nodes •  Increases power and area

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CL

Clk

Clk

B

A

Out Mp

Me

Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.


Clk

Clk

In1

In2

In3

In4

Out

In & Clk

Out

Time, ns

Volta

ge

Clock feedthrough

Clock feedthrough

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CL1

Clk

Clk

B=0

A=0

Out1 Mp

Me

Out2

CL2 In

Dynamic NAND Static NAND

=1 =0


Volta

ge

Time, ns

Clk

In

Out1

Out2

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 Capacitive coupling  Substrate coupling  Minority charge injection  Supply noise (ground bounce)


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Clk

Clk

Out1

In

Mp

Me

Mp

Me

Clk

Clk

Out2

V

t

Clk

In

Out1

Out2 ΔV

VTn

Only 0 → 1 transitions allowed at inputs!


In1

In2 PDN

In3

Me

Mp

Clk

Clk Out1

In4 PDN

In5

Me

Mp

Clk

Clk Out2

Mkp

1 → 1 1 → 0

0 → 0 0 → 1

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Clk

Clk

Ini PDN Inj

Ini Inj

PDN Ini PDN Inj

Ini PDN Inj

Like falling dominos!


  Only non-inverting logic can be implemented   Very high speed

  static inverter can be skewed, only L-H transition critical

  Input capacitance reduced – smaller logical effort

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Designing with Domino Logic

project phase 1 done – thanks for the timely response...

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