project poster: sdr platform elements

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Page 1: Project poster: SDR platform elements

www.www.sagaxsagax..huhuSagaxSagax,, Ltd Ltd..

HallerHaller u. 11-13. u. 11-13.1096 Budapest, HUNGARY1096 Budapest, HUNGARY

Software Defined Radio Software Defined Radio Platform ElementsPlatform Elements

This integrated digital modulator board is the first step towardsthe universal SDR platform elements contains technologyenhancements including:•FPGA firmware update trough the serial control interface•On-board power regulator and clock oscillator•Universal, programmable output cross-connects•Interleaving modulation for wideband applications•Board stacking (mezzanine) capability to DSP board

Universal digital modulator card with Xilinx XC2S50 FPGA,AD6622 digital up-converter, XC95144XL CPLD based cross-

connects and AD9772A interpolating DACs

Integrated digital modulator for multichannel andphased array applications:

14-BitDAC

(AD9772)

14-BitDAC

(AD9772)

14-BitDAC

(AD9772)

14-BitDAC

(AD9772)

CrossConnectSwitch(CPLD)

CrossConnectSwitch(CPLD)

CrossConnectSwitch(CPLD)

CrossConnectSwitch(CPLD)

DigitalTransmitProcessor(AD6622)

DigitalTransmitProcessor(AD6622)

DigitalTransmitProcessor(AD6622)

DigitalTransmitProcessor(AD6622)

Programmable output cross-connect implemented in CPLD

The modulator could be used asmezzanine card on DSP board

PCIHOST

Interface

PCIBUS

FPGALOGIC and DSP

resource

MCUConfig

EEPROM

ControlEEPROM

PROM JTAG

FPGA JTAG

Dedicateddata

connection

RS-232serial control

interface

Front-endBUS

ControlBUS

CLK DRV/2, /4X2, X4SCLK

OSC

ExternalCLK in/out

LCLK OSC

SamplingCLK

LocalCLK

I2C

FPGA CFG

Clocklines

Differentfront-end

configurations

ExternalTRG in/out

Desktop PCI based universal AD and DA converter card

The development of universal converter desktop PCIcard family continued on this architecture

The first PCI based IO card (DCU-202) with oneinput and one output channels using up to 80MHzsampling clock and slave mode PCI interface

Technology enhancements include:•FPGA firmware booting from EEPROM•Using slave mode PCI interface chip•Local bus logic implementation in FPGA•Deep FIFO memory for samples•External bus connection capability•External triggering and clocking

Dynamic range performance ADC:40MHz sampling clock, 8192points FFT

Internally generated spurious signalsare below -90dBFS

Universal digital modulator for multichannel, wideband and phased array applications