Prototype CERN-option: simulation results

Maria Elena Martin Albarran UCL

et al

Simulations- RFN stabilizationInitial values obtained, show that Voltage control, was stable, using a current bias for the clock very high

Simulation show that the current has to be lower, and that the whole system behaves as expected with Iclk=50uA-70uA

Experimental measurements Simulation 320MHz & Iclk=50uA

Simulations- RFN stabilization

Experimental measurements Simulation 320MHz & Iclk=50uA

Simulations- RFN stabilizationInitial values obtained, show that Voltage control, was stable, using a current bias for the clock very high

Simulation show that the current has to be lower, and that the whole system behaves as expected with Iclk=50uA-70uA

RFN (control voltage) can not be monitored usign the oscilloscope, because it affects the measurements (signal not buffered), and simulations will not reproduce the signal

• VDD=1.41V, ICLK_BIAS=50uA, RFN~0.65V• DELAY =

– NO EXTRACTION DELAY=41.50us– EXTRACTION DELAY=65.00us

Simulations- Parasitic Extraction

Delay found with no extraction at all cells

Delay found with extraction at all cells

• VDD=1.41V, ICLK_BIAS=50uA, RFN~0.65V• DELAY =

– NO EXTRACTION DELAY=41.50us– EXTRACTION DELAY=65.00us

Simulations- Parasitic Extraction

Delay found with no extraction at all cells

Delay found with extraction at all cells

• VDD=1.41V, ICLK_BIAS=50uA, RFN~0.65V• DELAY =

– NO EXTRACTION DELAY=41.50us– EXTRACTION DELAY=65.00us

Simulations- Parasitic Extraction

Delay found with no extraction at all cells

Delay found with extraction at all cells

• VDD=1.41V, ICLK_BIAS=50uA, RFN~0.65V• DELAY =

– NO EXTRACTION DELAY=41.50us– EXTRACTION DELAY=65.00us

Simulations- Parasitic Extraction

Simulations- Non CMOS Levels at DLL

Test signals not valid range (after diff buff)-> VCDLOUT is non cmos levels

VCDLOUT is readout using lvds transmitter pad, no signal there

• This shows heating at registers and dll, the non-uniformity is produced by presence of top metal layers -> – Is reasonable?

Simulations- Power Consumption

• Simulation Conditions: – Vdd=1.41V, Irclk_bias=50uA, RFN~550mV– Delay/cell(at Tap)=59.6ps– Total Current (through resistor 10mOhm tied to VSS!)

• Differential Clock Driver (single to diff Converter) = 112.65uA• Delay Element= 36 x (Diff Buff + Diff Clk + SE Diff Clk)= 36 x (153.87 + 107.06

+75.87) = 36 x 336.80 uA = 12 mA• Resistor String= 47uA

Simulations- Power Consumption

• Simulation Conditions: – Vdd=1.41V, Irclk_bias=50uA, RFN~550mV– Register :

• write (rms value):– 3.14mA x 1 CHANNEL -> 28.26mA for 9 channels

• write & read (rms value):– 3.54mA x 1 CHANNEL -> 31.86mA x for 9 channels

Simulations- Power Consumption

results comparable with reality and with previous implementations

Summary

• Simulation is following hardware testing

• Several other simulations will need to be performed

• Power consumption understood

• Start-up simulation coherent