Pulse Pulse GeneratorGenerator

High Speed Digital Systems LabHigh Speed Digital Systems LabWinter 2007/08Winter 2007/08

Design Presentation Design Presentation (Midterm )(Midterm )

Instructor: Instructor: Yossi HipshYossi Hipsh

Students: Students: Lior Shkolnitsky, Lior Shkolnitsky, Yevgeniy LobanovYevgeniy Lobanov

2

TopicsTopics

ReviewReview Block DiagramBlock Diagram Bill Of MaterialsBill Of Materials Electrical SchemeElectrical Scheme Layout StackLayout Stack Future Plans – Time TableFuture Plans – Time Table

3

ReviewReview The main goal is to build a The main goal is to build a

Programmable Pulse Generator. Programmable Pulse Generator. The Generator will be integrated into The Generator will be integrated into

an existing lab experiment, that teaches an existing lab experiment, that teaches about High Speed Systems Phenomena: about High Speed Systems Phenomena: reflections, skew and jitter. reflections, skew and jitter.

The Generator will create a very short The Generator will create a very short (0.5-1 nsec) and a longer (10-13 nsec) (0.5-1 nsec) and a longer (10-13 nsec) pulse pulse signal into transmission line.signal into transmission line.

4

I/O schemeI/O scheme

Programmable

Pulse

Generator

Power supply

Pulse width selection

Short pulse

Long pulse

5

Detailed Block DiagramDetailed Block Diagram

SplitterOscillatorAND

Manual Selector

ProgrammableDelay

ProgrammableDelay

Voltage Regulator

FF

Voltage Regulator

Power Supply

9 V

Level Translator

TTL Diff LVPECL

5 V

3.3 V100 nsec

10 nsec

10 nsec

10 nsec

0.5-1 nsec

3.3 V

2.3 V

0.5-1 nsec

/ ( ) 135 sec

( ) 2.3RISE FALL

IH

T delay p

V and Volt

BOM Name Part

NumberQnt. Exist

s

1 Voltage Regulator

LM1085 – 5V

1 Yes

LM1085 – 3.3V

1 Yes

LM1085 – ADJ

1 Yes

2 10MHz Oscillator CO1025 1 Yes

3 Flip Flop MC74F74N 1 Yes

4 TTL to LV PECL Translator

MC100EPT20

1 No

5 Splitter (Fan Out Buffer)

MC100EP11 1 No

6 Programmable Delay MC10EP195 2 No

7 AND Gate MC10EP05 1 No

8 Manual Selector DIP 5 4 Yes

9 Resistors --- Yes

10

Capacitors --- Yes

Appendix 1(click to jump)

Vtt

R950

R1050

R11

50

Vtt

R12

50

High Speed Digital Systems Lab - Technion - Winter 2007/08

U1

CO1025

14VCC

8OUT

7GND

SW1

SW DIP-10

D0

D9

U6

MC100EP195

Q20Q21

VBB6

EN16

IN4

IN5

LEN10

SETMIN11

SETMAX12

CSCD15

CSCD14D0

23

D125

D226

D327

D429

D530

D631

D732

D81

D92

D103 Vef

7

Vcf8

N.C.17

U9

LM1895 IT-ADJ

3IN

2OUT

ADJ

1

U7

MC100EP05

17

6

2

34

Vcc_3.3v

U8

LM1895 IT-5.0

3IN

2OUT

GND

1

U4

MC100EP11

D7

Q01

Q02

Q13

Q14

D6

C310u

R8

50

Vcc_5v

R7

50

U2A

74F74

D2

CLK3

Q5

Q6

PRE4 CLR1

R25

Vtt

C110u

R1121

C210u

Vtt

Vcc_5v

Vtt

Vtt

R450

9v

U5

MC100EP195

Q20Q21

VBB6

EN16

IN4

IN5

LEN10

SETMIN11

SETMAX12

CSCD15

CSCD14D0

23

D125

D226

D327

D429

D530

D631

D732

D81

D92

D103 Vef

7

Vcf8

N.C.17

Vcc_5v

R1350

U3

MC100EPT20

D7

Q2

Q3

R350

Differential Pulse

Title

Size Document Number Rev

Date: Sheet of

Designed by: Lior Shkolnitsky , Yevgeniy Lobanov 5

Pulse Generator

A

1 1Wednesday, January 16, 2008

9v

Output

R650

C410u

R550

R1450

Vtt = Vcc_3.3v-2v = 1.3v

R151k

D'7

D'1

D'5

D'8

D'6

D'4

D'9

D'0

SW2

SW DIP-10

D'3D'2

D'[0:9]

Vcc_3.3v = Pin 8GND = Pin 5

Vcc_3.3v = Pin 13, 18, 19, 22GND = Pin 9, 24, 28

50 ohm

50 ohm

Vcc_3.3v

C510u

9v

C610u

Vcc_5v = Pin 14GND = Pin 7

Vcc_3.3v = Pin 8GND = Pin 5

50 ohm

U10

LM1895 IT-3.3

3IN

2OUT

GND

1

50 ohm

50 ohm

50 ohm

Vcc_3.3v = Pin 8GND = Pin 5

Vcc_3.3v

R161k

D[0:9]

D1

D6D5

D8

D4D3

D7

D2

Electrical Scheme

Layout Stack

SIGNAL

FR 4

GND

Vcc (ECL) = 3.3 V

Vtt = 1.3 V

Vcc (TTL) = 5 V

FR 4

FR 4

FR 4

each metal layer - 1oz Copper

each dielectric layer - TBD

Future Plans – Time Future Plans – Time TableTable

End date 24/1 31/1 7/2 14/2 23/2

Making the board Making the board        

Building the prototype Building the prototype        

The test setup – The test setup – designing, debuggingdesigning, debugging        

Writing the report Writing the report        

Final PresentationFinal Presentation        

10

Questions / AnswersQuestions / Answers

Thank you!Thank you!

11

Appendix 1Appendix 1

Resistance [Ω]

quantity

1 50 14

2 5 1

3 121 1

4 1000 2

ResistorsResistors CapacitorsCapacitors

Capacitance [μF]

quantity

1 10 6

Go back…

Electrical Scheme (Signal Path Only)

Select 2

Select 1

Vtt

R1550

R1650

Vtt

R17

50

R18

50

U11

CO1025

14VCC

8OUT

7GND

U12

MC100EP195

Q20Q21

VBB6

EN16

IN4

IN5

LEN10

SETMIN11

SETMAX12

CSCD15

CSCD14D0

23

D125

D226

D327

D429

D530

D631

D732

D81

D92

D103 Vef

7

Vcf8

N.C.17

U14

MC100EP05

17

6

2

34

U16

MC100EP11

D7

Q01

Q02

Q13

Q14

D6

R19

50

Vcc_5v

R20

50

U17A

74F74

D2

CLK3

Q5

Q6

PRE4 CLR1

Vtt

Vcc_5v

Vtt

Vtt

Vtt

R2350

U18

MC100EP195

Q20Q21

VBB6

EN16

IN4

IN5

LEN10

SETMIN11

SETMAX12

CSCD15

CSCD14D0

23

D125

D226

D327

D429

D530

D631

D732

D81

D92

D103 Vef

7

Vcf8

N.C.17

U19

MC100EPT20

D7

Q2

Q3

R2450R25

50

Positive Pulse

Negative Pulse

R2650

R2750

R2850

D'[0:9]

50 ohm

50 ohm

50 ohm

50 ohm

50 ohm50 ohm

D[0:9]

Time Table

Task \ WeekTask \ Week 11 22 33 44 55 66 77 88 99 1010 1111 1212 1313 1414

Exploring the problem Exploring the problem 22-10                          

Definition presentation Definition presentation        22-11                  

Block diagram Block diagram consolidation consolidation                            

Finding suitable Finding suitable components components                            

Designing the board Designing the board                            

Design presentation Design presentation                19-12          

Ordering components Ordering components and board and board                            

Writing the booklet Writing the booklet                            

Designing a test setup Designing a test setup                            

Building the project Building the project                    15-01      

Building the test setup Building the test setup                            

Test and Debug Test and Debug                            

Final presentationFinal presentation                          30-01

100 nsec

10 nsec

0.5-1 nsec

3.3 V

2.3 V

0.5-1 nsec

/ ( ) 135 sec

( ) 2.3RISE FALL

IH

T delay p

V and Volt