PUNE VIDYARTHI GRIHA'S COE

Id (Keep it

blank)

Unit

No. Question Option A Option B Option C Option D

Correct

OptionMarks

1 The Gray code for decimal number 6 is equivalent to 1100 1001 101 110 C 1

1The 2s compliment form (Use 6 bit word) of the number 1010 is 111100 110110 110111 1011 B 2

1 AB+(A+B)’ is equivalent to A Ex-Nor B A Ex OR B (A+B)A (A+B)B A 2

1 The hexadecimal number equivalent to (1762.46)8 is 3F2.89 3F2.98 2F3.89 2F3.98 B 1

1 A three input NOR gate gives logic high output only when One input is high One input is low Two input are All input are D 1

1The absorption law in Boolean algebra say that X + X = X X . Y = X x + x . y = x

None of the

aboveC 2

1 Logic X-OR operation of (4ACO)H & (B53F)H results AACB 0000 ABCD FFFF D 2

1 What is decimal equivalent of (11011.1000)2 ? 22 22.2 20.2 27.5 D 1

1The negative numbers in the binary system can be represented by Sign magnitude 2's complement 1's complement

All of the

above A 1

1

Negative numbers cannot be represented inSigned magnitude

form

1’s complement

form

2’s complement

form

None of the

aboveD 1

1The answer of the operation (10111)2*(1110)2 in hex equivalence is 150 241 142 101011110 C 2

1

The Hexadecimal number equivalent of (4057.06)8 is 82F.027 82F.014 82F.937 83F.014 B 1

1 The NAND gate output will be low if the two inputs are 00 01 10 11 D 1

1 A binary digit is called a Bit Character Number Byte A 1

1 What is the binary equivalent of the decimal number 368 101110000 110110000 111010000 111100000 A 1

1 What is the binary equivalent of the Octal number 367 11110111 011100111 110001101 101110111 A 1

1 What is the binary equivalent of the Hexadecimal number 368 1111101000 1101101000 1101111000 1110101000 B 1

1 What is the binary equivalent of the decimal number 1011 1111110111 1111000111 1111110011 1111100011 C 1

1 The gray code equivalent of (1011)2  is 1101 1010 1111 1110 D 1

1 The decimal equivalent of hex number 1A53 is 6793 6739 6973 6379 B 1

Pune Vidyarthi Griha's College Of Engineering, Nashik

Department of Computer Engineering

Class :- Second Year Computer Engineering Sem - 1

Subject :- Digital Electronics and logic design

Note:- Question for 1 , 2 , 4 Marks (More than 200 Ques on each unit with combination of 1,2,4 marks)

Unit No:-1 Number Systems and Logic Design Techniques

PREPARED BY PROF. GHARU A. N.

PUNE VIDYARTHI GRIHA'S COE

1 ( 734)8 =( )16 C 1 D D C 1 1 C D 1 D C D 1

1 The simplification of the Boolean expression (A'BC')'+ (AB'C)' is 0 1 A BC B 2

1 The hexadecimal number ‘A0’ has the decimal value equivalent to 80 256 100 160 D 1

1 The Gray code for decimal number 6 is equivalent to 1100 1001 0101 0110 C 1

1 The Boolean expression A.B+ A.B+ A.B is equivalent to A + B A'.B (A + B)' A.B A 2

1 The 2’s complement of the number 1101101 is 101110 111110 110010 10011 D 1

1 When simplified with Boolean Algebra (x + y)(x + z) simplifies to x x + x(y + z) x(1 + yz) x + yz D 2

1 The code where all successive numbers differ from their preceding number by

single bit isBinary code. BCD. Excess – 3. Gray. D 1

1 -8 is equal to signed binary number 10001000 OOOO1000 10000000 11000000 A 2

1DeMorgan’s first theorem shows the equivalence of

OR gate and

Exclusive OR gate.

NOR gate and

Bubbled AND gate.

NOR gate and

NAND gate.

NAND gate

and NOT gateB 1

1When signed numbers are used in binary arithmetic, then which one of the

following notations would have unique representation for zero.Sign-magnitude. 1’s complement.

2’s

complement.

9’s

complement.A 1

1 The decimal equivalent of Binary number 11010 is 26 36 16 23 A 1

11’s complement representation of decimal number of -17 by using 8 bit

representation is1110 1110 1101 1101 1100 1100 0001 0001 A 1

1 The excess 3 code of decimal number 26 is 0100 1001 01011001 1000 1001 01001101 B 1

1 How many AND gates are required to realize Y = CD+EF+G 4 5 3 2 D 1

1 The hexadecimal number for (95.5)10 is (5F.8) 16 (9A.B) 16 ( 2E.F) 16 ( 5A.4) 16 A 1

1 The octal equivalent of (247) 10 is ( 252) 8 (350) 8 ( 367) 8 ( 400) 8 C 1

1The number 140 in octal is equivalent to (96)10 . ( 86) 10 (90) 10 .

none of

these.A 1

1 The NOR gate output will be low if the two inputs are 11 01 10 All D 1

1Convert decimal 153 to octal. Equivalent in octal will be (231)8 ( 331) 8 ( 431) 8 .

none of

these.A 1

1 The decimal equivalent of ( 1100)2 is 12 16 18 20 A 1

1The binary equivalent of (FA)16 is 1010 1111 1111 1010 10110011

none of

theseB 1

1How many two-input AND and OR gates are required to realize Y=CD+EF+G 2,2 2,3 3,3

None of

theseA 1

1The excess-3 code of decimal 7 is represented by 1100 1001 1011 1010 D 1

1 When an input signal A=11001 is applied to a NOT gate serially, its output

signal is00111 00110 10101 11001 B 2

1 The result of adding hexadecimal number A6 to 3A is DD E0 F0 EF B 1

1 A universal logic gate is one, which can be used to generate any logic function.

Which of the following is a universal logic gate?OR AND XOR NAND D 1

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1

Karnaugh map is used for the purpose of

Reducing the

electronic circuits

used.

To map the given

Boolean logic

function.

To minimize

the terms in a

Boolean

expression.

To maximize

the terms of

a given a

Boolean

expression.

C 1

1 The 2’s complement of the number 1101110 is 0010001 0010001 0010010 None C 1

1 The decimal equivalent of Binary number 10101 is 21 31 26 28 A 1

1 How many two input AND gates and two input OR gates are required to

realize Y = BD+CE+AB1,1 4,2 3,2 2,3 A 1

1 Which of following are known as universal gates NAND & NOR AND & OR. XOR & OR. None. A 1

1 Convert the octal number 7401 to Binary. 1.111E+11 1.1111E+11 1.111E+11 1.1101E+11 A 1

1 Find the hex sum of (93)16 + (DE)16 . (171)16 (271)16 (179)16 (181)16 A 1

1Perform 2’s complement subtraction of (7)10 − (11)10 . 1100 (OR -4) 1101 (OR -5) 1011 (OR -3)

1110 (OR -

6)A 1

1 What is the Gray equivalent of (25)10 01101 110101 10110 10101 D 1

1

Simplify the Boolean expression F = C(B + C)(A + B +

C).C BC ABC A+BC A 2

1 Simplify the following expression into sum of products using Karnaugh map

F(A,B,C,D) = (1,3,4,5,6,7,9,12,13)

A'B+C' D+

A'D+BC'

A'B'+C' D'+

A'D'+B'C'

A'B'+C' D+

A'D+BC'

A'B+C' D'+

A'D'+BC'A 4

1Simplify F = (ABC)'+( AB)'C+ A'BC'+ A(BC)'+ AB'C. ( A' + B' +C' ) ( A' + B +C ) ( A + B +C )

( A + B' +C'

)A 4

1Determine the binary numbers represented by 25.5 11001.1 011011.101 10101.110 11001.0101 A 1

1 Conversion of decimal number 10.625 into binary number: 1010.101 1110.101 1001.11 1001.101 A 1

1Conversion of fractional number 0.6875 into its equivalent binary number: 0.1011 0.1111 0.10111 0.0101 A 1

1 Perform the following subtractions using 2’s complement method. 01000 –

0100100001 00010 00011 11110 A 3

1 Subtraction of 01100-00011 using 2’s complement method. : 1001 1000 1010 0110 A 3

1Minimize the logic functionY(A,B,C,D) = m(0,1,2,3,5,7,8,9,11,14) . Using

Karnaugh map.

ABC D' + A' B' +

B' C' + B' D+ A'D

ABC D + A B + B'

C' + B' D+ A'D

A' B' + B' C' +

B' D+ A'D

ABC D' + A'

B' + B' C' +

B' D

A 4

1 Simplify the given expression to its Sum of Products (SOP) form Y = (A +

B)(A + (AB)')C + A'(B+C')+ A'B+ ABC

AC+ BC+ A'B +

A' C'AC+ BC+ A'B

BC+ A'B + A'

C'

AC+ A'B +

A' C'A 4

1

Convert the decimal number 82.67 to its binary, hexadecimal and octal

equivalents

(1010010.1010101

1)2; (52.AB)16 ;

(122.526)8

(1010010.1010101

1)2; (52.AB)16 ;

(122.526)9

(1010010.1010

1011)2;

(52.AB)16 ;

(122.526)10

(1010010.10

101011)2;

(52.AB)16 ;

(122.526)11

A 1

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1Add 20 and (-15) using 2’s complement.

(100100 )2 OR

(+4)10

(000100 )2 OR (-

4)10

Both (A) and

(B)

None of the

aboveA 3

1 Add 648 and 487 in BCD code. 1135. 1136 1235 1138 A 3

1(23.6)10 = (X)2 FIND X (10111.1001100)2 (10101.1001100)2

(10001.100110

0)2

(10111.1000

011)2

A 1

1(65.535)10 =(X)16 FIND X (41.88F5C28)16. (42.88F5C28)16. (41.88F5C)16.

(42.88F5C)1

6.A 1

1 Convert the decimal number 430 to Excess-3 code: 110110001 110110000 110110011 110100001 A 1

1 Convert the binary number 10110 to Gray code: 11101. 11001. 10101. 11100 A 1

1 Minimize the following logic function using K-maps F(A,B,C,D) =

m(1,3,5,8,9,11,15) + d(2,13)

A B' C' + C' D +

B'D + ADC' D + B'D + AD

A B' C' + B'D +

AD

A B' C' + C'

D + B'D A 4

1 Convert (2222)10 in Hexadecimal number. 8AE 8BE 93C FFF A 1

1

Divide ( 101110) 2 by ( 101)2.Quotient -1001

Remainder -001

Quotient -1000

Remainder -001

Quotient -1001

Remainder -011

Quotient -

1001

Remainder -

000

A 3

1

Minimise the logic function (POS Form) F A,B,C,D) = PI M (1, 2, 3, 8, 9, 10,

11,14)× d (7, 15)

F=[(B+D’)+(B+C’

)’(A’+C’)+(A’+B)

]’

F=[(B+D’)+(B+C’)

’(‘A’+C’)+(A’+B)]

’

F=[(B+D’)+(B

+C’)’(‘A’+C’)+

(A’+B)]’

F=[(B+D’)+(

B+C’)’(‘A’+

C’)+(A’+B)]

’

A 4

1 Perform following subtraction (i) 11001-10110 using 1’s complement 00011 00111 00010 10011 A 3

1 Perform following subtraction(ii) 11011-11001 using 2’s complement 00010 00111 00011 10011 A 3

1 Reduce the following equation using k-map Y = (ABC)'+ A(CD)'+ AB'+

ABCD'+ (AB)'C B'+(AD)' B' (AD)' B'+AD A 4

1Write the expression for Boolean function F (A, B, C) = m (1,4,5,6,7) in

standard POS form.

= (A+B+C)(A+B'

+C)(A+B' +C' )

= (A+B' +C)(A+B'

+C' )

=

(A+B+C)(A+B'

+C)

=

(A+B+C)(A

+B' +C' )

A 4

1 Convert the decimal number 45678 to its hexadecimal equivalent number. (B26E)16 (A26E)16 (B26B)16 (B32E)16 A 1

1 Convert (177.25)10 to octal. (261.2)8 (260.2)8 (361.2)8 (251.2)8 A 1

1 Reduce the following equation using k-map Y = B C' D'+ A' B C' D+ A B C'

D+ A' B C D+ A B C DBC’ + BD BC’ + BD+A

BC’ + BD +

AC

BC’ + BD +

ADA 4

1 8-bit 1’s complement form of –77.25 is 1001101.01 10110010.1011 01001101.0010 10110010.1 B 2

1 In computers, subtraction is generally carried out by9’s complement 10’s complement 1’s complement

2’s

complementD 1

1 The 2s compliment form (Use 6 bit word) of the number 1010 is 111100 110110 110111 1011 B 1

1 The answer of the operation (10111)2*(1110)2 in hex equivalence is 150 241 142 101011110 C 2

1 The decimal number equivalent of (4057.06)8 is 2095.75 2095.075 2095.937 2095.0937 D 1

1 The gray code equivalent of (1011)2  is 1101 1010 1110 1111 D 1

112-bit 2’s complement of –73.75 is 01001001.1100 11001001.1100 10110110.0100

10110110.11

00C 2

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1 The 2’s complement of the number 1101101 is 101110 111110 110010 10011 D 1

1 The hexadecimal number equivalent to (1762.46)8 is 3F2.89 3F2.98 2F3.89 2F3.98 B 1

1 What is decimal equivalent of BCD 11011.1100 ? 22.0 22.2 20.2 21.2 B 2

1 What is the binary equivalent of the decimal number 368 101110000 110110000 111010000 111100000 A 1

1 The Gray code for decimal number 6 is equivalent to 1100 1001 0101 0110 C 2

1 The decimal equivalent of hex number 1A53 is 6793 6739 6973 6379 B 1

1(2FAOC)16 is equivalent to (195 084)10

(001011111010

0000 1100)2

Both (A) and

(B)

None of

theseB 1

1 The octal equivalent of hexadecimal (A.B)16 is 47.21 12.74 12.71 17.21 B 1

1 Logic X-OR operation of (4ACO)H & (B53F)H results AACB 0000 FFFF ABCD C 1

1 The simplified form of the Boolean expression (X+Y+XY)(X+Z) is X + Y + ZX + Y XY – YZ X + YZ XZ + Y C 2

1 The output of a logic gate is 1 when all its inputs are at logic 0. the gate is

either A NAND or an XOR An OR or an XNOR

An AND or

XOR

A NOR or

an XNOR D 1

1

2's complement of any binary number can be calculated by adding 1's

complement twice

adding 1 to 1's

complement

subtracting 1

from 1's

complement.

calculating

1's

complement

and inverting

Most

significant

bit

B 1

1

Sum-of-Weights method is used __________

to convert from

one number system

to other

to encode data to decode

data

to convert

from serial

to parralel

data

A 1

1 The complement of a variable is always 1 0 inverse None C 1

1 The difference of 111 - 001 equals 100 111 001 110 D 2

1 The Unsigned Binary representation can only represent positive binary

numbers TRUE FALSE

Both (A) and

(B)

None of

AboveA 1

1 which of the following rules states that if one input of an AND gate is always

1, the output is equal to the other input? A +1 =1 A +A =A A.A = A A.1= A C 1

1 Which of the number is not a representative of hexadecimal system 1234 ABCD 1001 DEFH D 1

1 Which one of the following is NOT a valid rule of Boolean algebra? A = A' AA = A A + 1 = 1 A + 0 = A A 1

1

In the binary number ' 10011 ' the weight of the most significant digit is ____ 2^4(2 raise to

power 4)

2^3 (2 raise to

power 3)

2^0 (2 raise

to power 0)

2^1 (2

raise to

power 1)

A 1

1 The binary value ' 1010110 ' is equivalent to decimal __________ 86 87 88 89 A 1

1 2's complement of hexadecimal number B70A is B70B B709 48F6 48F5 C 1

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1 2's complement of 5 is 1101 1011 1010 1100 B 1

1 The 4-bit 2's complement representation of ' -7 ' is _____________ 111 1111 1001 110 C 1

1 If we multiply ' 723 ' and ' 34 ' by representing them in floating point notation

i.e. By first, converting them in floating point representation and then

multiplying them, the value of mantissa of result will be ________

24.582 2.4582 24582 0.24582 A 2

1 The output of the expression F=A+B+C will be Logic ________ when A=0,

B=1, C=1. the symbol ' + ' here represents OR Gate. Undefined One Zero

10

(binary)B 2

1 A NAND gate's output is LOW if all inputs are LOW all inputs are HIGH

any input is

LOW

any input is

HIGHC 1

1

NOR gate is formed by connecting _________OR Gate and then

NOT Gate

NOT Gate and then

OR Gate

AND Gate and

then OR Gate

OR Gate and

then AND

Gate

C 1

1 The AND Gate performs a logical __________function Addition Subtraction Multiplication Division C 1

1 The Extended ASCII Code (American Standard Code for Information

Interchange) is a _____ code 2-bit 7-bit 8-bit 16-bit C 1

1 The OR gate performs Boolean ___________. multiplication subtraction division addition D 1

1

The output of an AND gate is one when _______ All of the

inputs are one

Any of the input

is one

Any of the

input is zero

All the

inputs are

zero

A 1

1 A NOR's gate output is HIGH if

all inputs are

HIGH

any input is

HIGH

any input is

LOW

all inputs

are LOWD 1

1

A logic circuit with an output X = A(Bar)BC+AB(Bar) consists of ________.

two AND gates,

two OR gates, two

inverters

three AND

gates, two OR

gates, one inverter

two AND

gates, one OR

gate, two

inverters

two AND

gates, one

OR gate

C 1

1 the boolean expression AB'CD'is a sumterm a product term a literal term always 1 B 1

1

The boolean expression X = AB + CD represents two ORs

ANDed together

a 4-input AND

gate

two ANDs

ORed together

an

exclusive-OrC 1

1 The expression _________ is an example of Commutative Law for

Multiplication. AB+C = A+BC

A(B+C) =

B(A+C) AB=BA A+B=B+A C 2

1 To implement the expression AB(bar)CD+ ABC(bar)D+ ABCD (bar), it takes

one OR gate and

three AND gates

and three inverters

three AND gates

and four inverters

three AND

gates

one AND

gateA 1

1 the boolean expression A + B' + C is a sum term a literal term a product

term

complement

ed termA 1

1

The minterm expansion for F(A,B,C) = (A + B + C)(A + B' + C')(A' + B +

C')(A' + B' + C) is

F (A,B,C) = Pi

M(0,3,5,6)

F(A,B,C) =

Summation

m(0,3,5,6)

F(A,B,C) =

Summation

m(0,3,5,6)

F(A,B,C) =

Summation

m(1,2,4,7)

A 2

1 (A+B).(A+C) = ___________ B+C A+BC AB+C AC+B B 1

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1 A'B +A'BC'+AC is an example of ________

Product of sum

form

Sum of product

form

Demorgans

law

Associative

law

B 1

1 An example of SOP expression is A + B(C + D)

A'B + AC' +

AB'C

(A' + B +

C)(A + B' + C)

both (a)

nad (b)B 1

1Determine the values of A, B, C, and D that make the sum term A(bar) +

B+C(bar)+D equal to zero.

A = 1, B = 0, C

= 0, D = 0

A = 1, B = 0, C

= 1, D = 0

A = 0, B = 1,

C = 0, D = 0

A = 1, B =

0, C = 1, D =

1

B 2

1The bolean expression A + BC equals

(A' + B)(A' +

C) (A + B)(A + C)

(A + B)(A' +

C)

none of

the aboveB 2

1

A.(B + C) = A.B + A.C is the expression of _________________ Demorgan's

Law Commutative Law

Distributive

Law

Associative

Law

C 1

1

A.(B.C) = (A.B).C is an expression of __________ Demorgan's Law Distributive Law Commutative

Law

Associative

Law

D 1

1 How many binary bits are necessary to represent 748 different numbers? 7 10 9 8 B 1

1 The correct binary equivalent for DFA16 is: 1111011001012 1101111010102 1110101110102 0110110110112 B 1

1 Which of the following Boolean expressions represents the DeMorganized

version of

the expression ((A + B′ ) + CD′ ) ′

(A′ +B + C + D) ′ (A′ +B) (C′ D) (A′ B). (C′ + D) A′ + B′ + C + D C 1

1 A Nibble consists of _____ bits 2 4 8 16 B 1

1 Excess-8 code assigns _______ to “-8” 1110 1100 1000 0000 D 1

1The three fundamental gates are ___________ AND, NAND, XOR OR, AND, NAND

NOT, NOR,

XOR

NOT, OR,

ANDD 1

1

The total amount of memory that is supported by any digital system depends

upon ______

The organization

of memory

The structure of

memory

The size of

decoding unit

The size of

the address

bus of the

microproces

sor

D 1

1 Addition of two octal numbers “36” and “71” results in ________ 213 123 127 345 C 3

1In which of the following base systems is 123 not a valid number?

Base 10Base 16 Base8 Base 3 D 1

1Storage of 1 KB means the following number of bytes

1000964 1024 1064. D 2

1 What is the octal equivalent of the binary number:

10111101 675 275 572 573. B 1

1The binary code of (21.125)10 is

10101.001 10100.001 10101.010 10100.111 A 1

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1

A NAND gate is called a universal logic element becauseit is used by

everybody

any logic function

can be realized by

NAND gates alone

all the

minization

techniques are

applicable for

optimum

NAND gate

realization

many digital

computers

use NAND

gates.

B 1

1

Digital computers are more widely used as compared to analog computers,

because they are

less expensive always more

accurate and faster

useful over

wider ranges of

problem types

easier to

maintain.C 1

1

Most of the digital computers do not have floating point hardware because

floating point

hardware is costlyit is slower than

software

it is not

possible to

perform

floating point

addition by

hardware

of no

specific

reason.

A 1

1 The number 1000 would appear just immediately afterFFFF (hex)

1111 (binary) 7777 (octal)All of the

above.D 1

1

(1(10101)2 is (37)10 ( 69)10 (41 )10 — (5)10 A 1

1 The number of Boolean functions that can be generated by n variables is equal

to2

n22

n2

n-1— 2

n B 1

1Consider the representation of six-bit numbers by two’s complement, one’s

complement, or by sign and magnitude: In which representation is there

overflow from

the addition of the integers 011000 and 011000?

Two’s

complement only

Sign and magnitude

and one’s

complement only

Two’s

complement

and one’s

complement

only

All three

representatio

ns.

D 2

1

Positive logic in a logic circuit is one in which

logic 0 and 1 are

represented by 0

and positive

voltage

respectively

logic 0 and, -1 are

represented by

negative and

positive voltages

respectively

logic 0 voltage

level is higher

than logic 1

voltage level

logic 0

voltage level

is lower than

logic 1

voltage

level.

D 1

1Which of the following gate is a two-level logic gate

OR gate NAND gate

EXCLUSIVE

OR gateNOT gate. C 1

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1

An AND gate will function as OR if

all the inputs to the

gates are “1” all the inputs are ‘0’either of the

inputs is “1”

all the inputs

and outputs

are

complement

ed.

D 1

1 An OR gate has 6 inputs. The number of input words in its truth table are 6 32 64 128 C 1

1

NAND. gates are preferred over others because these

have lower

fabrication area can be used to

make any gate

consume least

electronic

power

provide

maximum

density in a

chip.

B 1

1In case of OR gate, no matter what the number of inputs, a

1 at any input

causes the output

to be at logic 1

1 at any input

causes the output to

be at logic 0

0 any input

causes the

output to be at

0 at any

input causes

the output to

A 1

1

Excess-3 code is known as

Weighted code Cyclic redundancy Self- Algebraic C 1

1 Indicate which of the following three binary additions are correct?

1.1011 + 1010 = 10101

II. 1010 + 1101 = 10111

III. 1010 + 1101 = 11111I and II II and III III only II and I D 3

1X – = Y + 1 means

X = X – Y + 1 X = –X – Y – 1 X = –X + Y + 1 X= X – Y – 1 A 1

1 A binary digit is called a Bit Byte Number Character A 1

1What is decimal equivalent of BCD 11011.1100 ?

22.022.2 20.2 21.2 B 1

1 The ASCII code for letter A is 11000111111111 1000001 0010011 C 1

1The Gray code for decimal number 6 is equivalent to

11001001 0101 0110 C 1

1 The decimal equivalent of hex number 1A53 is 67936739 6973 6379 B 1

2 Transistor is a Current controlled

current device.

Current controlled

voltage device.

Voltage

controlled

current device.

Voltage

controlled

voltage

device.

A 1

Unit No:-2 Logic Families

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2 A digital logic device used as a buffer should have what input/output

characteristics? high input

impedance and

high output

impedance

low input

impedance and high

output impedance

low input

impedance and

low output

impedance

high input

impedance

and low

output

impedance

D 2

2 What is the standard TTL noise margin? 5.0 V 0.2 V 0.8 V 0.4 V D 2

2

The range of a valid LOW input is: 0.0 V to 0.4 V 0.4 V to 0.8 V 0.0 V to 1.8 V

0.0 V to 2.8

V

B 2

2 When an IC has two rows of parallel connecting pins, the device is referred to

as:

a QFP a DIP

a phase splitter

CMOS B 1

2 Which digital IC package type makes the most efficient use of printed circuit

board space?

SMT TO can flat pack DIP A 1

2 The digital logic family which has minimum power dissipation is TTL RTL DTL CMOS D 2

2 Which of the following is the fastest logic TTL ECL CMOS LSI B 2

2 The digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS A 2

2 Which TTL logic gate is used for wired ANDing Open collector

output

Totem Pole Tri state output ECL gates A 2

2 CMOS circuits consume power Equal to TTL Less than TTL Twice of TTL Thrice of

TTL

B 2

2 In a positive logic system, logic state 1 corresponds to positive voltage higher voltage level zero voltage

level

lower

voltage level

B 1

2 The commercially available 8-input multiplexer integrated circuit in the TTL

family is

7495 74153 74154 74151 B 2

2 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts 0volts 5volts C 2

2 Which ofthe following is a universal logic gate? OR XOR AND NAND D 1

2

How is the noise margin of a logic family

defi ned?

VOH – VOL greater of VDD –

VOH and VOL –

GND

smaller of VIL

– VOL and

VOH – VIH

VIH – VIL. C 2

2 What parameter causes the main limit

on fan-out of CMOS logic in high-speed

applications?

d.c. input current output current input

capacitance

power

supply

voltage.

A 2

2 The number of standard loads that the output of the gate can drive

with out impairment of its normal operation is

Fan-in Fan-Out noise-margin power-

dissipiation

B 2

2 A NAND gate is called a universal logic element because it is used by

everybody

any logic function

can be realized by

NAND gates alone

all the

minization

techniques are

applicable for

optimum

NAND gate

realization

many digital

computers

use NAND

gates.

B 2

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2 Measure of power consumed by the gate when fully driven by all

its inputs is

Fan-in Fan-Out noise-margin power-

dissipiation

D 2

2 Fan-out is specified in terms of voltage current watt unit load D 2

2 Which of the following logic family has highest fan-out DTL CMOS RTL TTL B 2

2 Which of following consume minimum power TTL RTL DTL CMOS D 1

2 Among the logic families, low power dissipation is in DTL CMOS RTL TTL B 1

2 The temperature in which the performance of the IC is effective Operating

Temprature

Fan-Out Normal

temrature

power-

dissipiation

A 1

2 The nominal value of the dc supply voltage for TTL (transistor-transistor logic)

devices is

0v 5v 10v 15v B 1

2 The average transition delay time for the signal to propagate from

input to output when the signals change in value. It is expressed in ns is

Propogation Delay Fan-Out noise-margin power-

dissipiation

A 2

2 the number of inputs connected to the gate without any degradation in the

voltage level.

Propogation Delay Fan-Out Fan- in power-

dissipiation

C 2

2 Which of the following logic gives the complementary outputs? ECL TTL CMOS PMOS A 2

2 The maximum noise voltage added to an input signal of a digital circuit that

does

Fan-in Fan-Out noise-margin power-

dissipiation

C 2

2 Among the logic families, Slowest logic family is TTL RTL DTL CMOS D 1

2 Operating temperature of the IC vary from 0 to70 celsius 0to35celsius 0to 50celsius 0to70celsius A 1

2 1. Open collector output 2. Totem-Pole Output 3. Tri-state output are the type

of

TTL LOGIC RTL LOGIC CMOS LOGIC None of this A 1

2 If the channel is initially doped lightly with p-type impurity a conducting

channel

Depletion mode

operation MOS

Enhancement mode

operation of MOS

Both Mode None of this A 1

2 If the region beneath the gate is left initially uncharged the gate field must

induce a

channel before current can flow. Thus the gate voltage enhances the channel

current and sucha device is said to operate in the

Depletion mode

operation MOS

Enhancement mode

operation of MOS

Both Mode None of this B 2

2 The n- channel MOS conducts when its gate- to- source

voltage is positive.

gate- to- source

voltage is negative

gate- to- source

voltage is zero.

None of this A 2

2 The p- channel MOS conducts when its gate- to- source

voltage is positive.

gate- to- source

voltage is zero.

gate- to- source

voltage is

None of this C 2

2 The fan-out of a MOS-logic gate is higher than that of TTL gates because of its low input

impedance

high input

impedance

low output

impedance

high output

impedance

D 2

2 Which factor does not affect CMOS loading? Charging time

associated with the

output resistance

Discharging time

associated with the

output resistance of

Output

capacitance of

the load gates

Input

capacitance

of the load

C 2

2 Logic gates are the basic elements that make a Analog system Basic System gating system digital

system

D 1

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2 Which of the following gate is a two-level logic gate OR gate NAND gate EXCLUSIVE

OR gate

NOT

C 1

2 Among the logic families, the family which can be used at very high frequency

greater than 100 MHz in a 4 bit

TTLAS CMOS ECL TTLLS C 1

2 NAND. gates are preferred over others because these have lower

fabrication area

can be used to

make any gate

consume least

electronic

power

provide

maximum

density in a

chip.

B 2

2 The fan Out of a 7400 NAND gate is 2TTL 5TTL 8TTL 10TTL D 2

2 Which transistor element is used in CMOS logic? FET MOSFET Bipolar Unijunction B 2

2 CMOS circuits are extensively used for ON-chip computers mainly because of

their extremely

low power

dissipation.

high noise

immunity.

large packing

density.

low cost. C 2

2 Which equation is correct? VNL = VIL(max)

+ VOL(max)

VNH = VOH(min)

+ VIH(min)

VNL =

VOH(min) –

VIH(min)

VNH =

VOH(min) –

VIH(min)

D 2

2 The greater the propagation delay, the lower the

maximum

frequency

higher the

maximum

frequency

maximum

frequency is

unaffected

minimum

frequency is

unaffected

A 2

2 For a CMOS gate, which is the best speed-power product? 1.4 Pj 1.6 pJ 2.4 pJ 3.3 pJ A 2

2 In a TTL circuit, if an excessive number of load gate inputs are connected, VOH(min) drops

below VOH

VOH drops below

VOH(min)

VOH exceeds

VOH(min)

VOH and

VOH(min)

are

unaffected

B 2

2 Which is not a MOSFET terminal? Gate Drain Source Base D 2

2 An open-drain gate is the CMOS counterpart of an open-collector

TTL gate

a tristate TTL gate a bipolar

junction

transistor

an emitter-

coupled

logic gate

A 2

2 The active switching element used in all TTL circuits is the bipolar junction

transistor (BJT

field-effect

transistor (FET

metal-oxide

semiconductor

field-effect

transistor

(MOSFET

unijunction

transistor

(UJ)

A 2

2 One output structure of a TTL gate is often referred to as a

diode

JBT arrangement totem-pole

arrangement

base, emitter,

collector

arrangement

C 2

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2 An open-collector output requires a pull-down

resistor

a pull-up resistor no output

resistor

an output

resistor

B 2

2 Which is not an output state for tristate logic? HIGH LOW High-Z Low-Z D 2

2 TTL is alive and well, particularly in industrial

applications

millitary

applications

educational

applications

commerciala

pplications

C 2

2 A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL

inputs. How much current does the drive output sink?

–12.8 Ma –8 mA –1.6 mA –25.6 mA A 4

2 A standard TTL circuit with a totem-pole output can sink, in the LOW state

(IOL(max)),

16 Ma 20 mA 24 Ma 28mA A 4

2 It is best not to leave unused TTL inputs unconnected (open) because of TTL's noise sensitivity low-current

requirement

open-collector

outputs

tristate

construction

A 2

2 Which logic family combines the advantages of CMOS and TTL? BiCMOS TTL/CMOS ECL TTL/MOS A 2

2 Which is not part of emitter-coupled logic (ECL)? Differential

amplifier

Bias circuit Emitter-

follower circuit

Totem-pole

circuit

D 2

2 PMOS and NMOS circuits are used largely in MSI functions LSI functions diode functions TTL

functions

B 2

2 The nominal value of the dc supply voltage for TTL and CMOS is 3 V 5 V 10 V 12 V B 2

2 If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static

(noncharging) HIGH output state, the power dissipation (PD) of the gate is

5.5 Mw 5mW 5.5 W 1.1mW A 4

2 The switching speed of CMOS is now competitive with

TTL

three times that of

TT

slower than

TTL

twice that of

TTL

A 2

2 One advantage TTL has over CMOS is that TTL is less expensive not sensitive to

electrostatic

discharge

faster more widely

available

B 2

2 TTL operates from a 9-volt suppl 3-volt supply 12-volt supply 5-volt supply D 1

2 A CMOS IC operating from a 3-volt supply will consume less power than a

TTL IC

more power than a

TTL IC

the same power

as a TTL IC

no power at

all

A 2

2 CMOS IC packages are available in DIP configuration SOIC configuration DIP and SOIC

configurations

None of this C 2

2 The terms "low speed" and "high speed," applied to logic circuits, refer to the rise time fall time propagation

delay time

clock speed C 2

2 The power dissipation, PD, of a logic gate is the product of the dc supply voltage

and the peak

current

dc supply voltage

and the average

supply current

ac supply

voltage and the

peak current

ac supply

voltage and

the average

B 2

2 How many different logic level ranges for TTL 1 2 3 4 D 1

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2 Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active

switching elements in

CMOS circuits TTL ECL circuits PMOS

circuits

A 2

2 ECL IC technology is……………….than TTL technology. faster slower equal none of this A 1

2 A major advantage of ECL logic over TTL and CMOS is low power

dissipation

high speed both low power

dissipation and

high speed

neither low

power

dissipation

nor high

speed

B 1

2 Digital technologies being used now-a-days are DTL and EMOS TTL, ECL, CMOS

and RTL

TTL, ECL,

CMOS and

DTL

TTL, ECL,

CMOS and

DTL

B 2

2 Which of the following is the fastest logic TTL ECL CMOS PMOS B 2

2 Which TTL logic gate is used for wired ANDing Open collector

output

Totem Pole Tri state output ECL gates A 2

2 CMOS circuits consume power Equal to TTL Less than TTL Twice of TTL Thrice of

TTL

B 1

2 CMOS circuits are extensively used for ON-chip computers mainly because of

their extremely

low power

dissipation

high noise

immunity

large packing

density

low cost. C 2

2 The MSI chip 7474 is Dual edge

triggered JK flip-

flop (TTL).

Dual edge triggered

D flip-flop

(CMOS).

Dual edge

triggered D flip-

flop (TTL).

Dual edge

triggered JK

flip-flop

(CMOS).

C 2

2 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts 5 volts 0 volts D 2

2

What is unique about TTL devices such as the 74SXX?

These devices use

Schottky

transistors and

diodes to prevent

them from going

into saturation; this

results in faster

turn-on and turn-

off times, which

translates into

higher frequency

operation.

The gate transistors

are silicon (S), and

the gates therefore

have lower values

of leakage current.

The S denotes

the fact that a

single gate is

present in the

IC rather than

the usual

package of 2–6

gates.

The S

denotes a

slow version

of the

device,

which is a

consequence

of its higher

power

rating.

A 4

2 Which of the following logic families has the shortest propagation delay? CMOS BiCMOS ECL 74SXX C 1

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2 Why must CMOS devices be handled with care? so they don’t get

dirty

because they break

easily

because they

can be damaged

by static

electricity

discharge

all of above C 2

2 What should be done to unused inputs on TTL gates? They should be left

disconnected so as

not to produce a

load on any of the

other circuits and

to minimize power

loading on the

voltage source.

All unused gates

should be

connected together

and tied to V

through a 1 k

resistor.

All unused

inputs should

be connected to

an unused

output; this will

ensure

compatible

loading on both

the unused

inputs and

unused outputs.

Unused

AND and

NAND

inputs

should be

tied to VCC

through a 1 k

resistor;

unused OR

and NOR

inputs

should be

grounded.

D 2

2 Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and

ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the

chip?

50 Mw 82.5 mW 115 mW 165 mW B 4

2 Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate? YES No A 1

2 What is the major advantage of ECL logic? very high speed wide range of

operating voltage

very low cost very high

power

A 2

2 As a general rule, the lower the value of the speed–power product, the better

the device because of its:

long propagation

delay and high

power

consumption

long propagation

delay and low

power consumption

Both none of

above

B 2

2 What is the difference between the 54XX and 74XX series of TTL logic gates? 54XX is faster. 54XX is slower. 54XX has a

wider power

supply and

expanded

temperature

range.

54XX has a

narrower

power

supply and

contracted

temperature

range.

C 2

2 What is the range of invalid TTL output voltage? 0.0–0.4 V 0.4–2.4 V 2.4–5.0 V 0.0–5.0 V B 2

2 An open collector output can ________ current, but it cannot ________. sink, source

current

source, sink current sink, source

voltage

source, sink

voltage

A 2

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2 Why is a decoupling capacitor needed for TTL ICs and where should it be

connected

to block dc,

connect to input

pins

to reduce noise,

connect to input

pins

to reduce the

effects of noise,

connect

between power

supply and

ground

NONE OF

ABOVE

C 2

2 Which of the following summarizes the important features of emitter-coupled

logic (ECL)?

low noise margin,

low output voltage

swing, negative

voltage operation,

fast, and high

power

consumption

good noise

immunity, negative

logic, high-

frequency

capability, low

power dissipation,

and short

propagation time

low

propagation

time, high-

frequency

response, low

power

consumption,

and high output

voltage swings

poor noise

immunity,

positive

supply

voltage

operation,

good low-

frequency

operation,

and low

power

A 2

2 Why is a pull-up resistor needed for an open collector gate? to provide Vcc for

the IC

to provide ground

for the IC

to provide the

HIGH voltage

to provide

the LOW

voltage

C 2

2 Why is a pull-up resistor needed when connecting TTL logic to CMOS logic? to increase the

output LOW

voltage

to decrease the

output LOW

voltage

to increase the

output HIGH

voltage

to decrease

the output

HIGH

voltage

C 2

2 The word "interfacing" as applied to digital electronics usually means: a conditioning

circuit connected

between a standard

TTL NAND gate

and a standard

TTL OR gate

a circuit connected

between the driver

and load to

condition a signal

so that it is

compatible with the

load

any gate that is

a TTL

operational

amplifier

designed to

condition

signals between

NMOS

transistors

any TTL

circuit that is

an input

buffer stage

B 2

2 The rise time (tr) is the time it takes for a pulse to rise from its ________ point

up to its ________ point. The fall time (tf) is the length of time it takes to fall

from the ________ to the ________ point.

10%, 90%, 90%,

10%

90%, 10%, 10%,

90%

20%, 80%,

80%, 20%

10%, 70.7%,

70.7%, 10%

A 4

2 The term buffer/driver signifies the ability to provide low output currents to

drive light loads.

TRUE FALSE B 2

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2 PMOS and NMOS ________. represent

MOSFET devices

utilizing either P-

channel or N-

channel devices

exclusively within

a given gate

are enhancement-

type CMOS devices

used to produce a

series of high-speed

logic known as

74HC

represent

positive and

negative MOS-

type devices,

which can be

operated from

differential

power supplies

and are

compatible with

operational

amplifiers

None of the

above

A 4

2 Why is the operating frequency for CMOS devices critical for determining

power dissipation?

At low

frequencies, At

low frequencies,

power dissipation

increases.

At high

frequencies, the

gate will only be

able to deliver 70.7

% of rated power.

At high

frequencies,

charging and

discharging the

gate

capacitance will

draw a heavy

current from the

power supply

and thus

increase power

dissipation.

At high

frequencies,

the gate will

only be able

to deliver

70.7 % of

rated power

and charging

and

discharging

the gate

capacitance

will draw a

heavy

current from

the power

supply and

thus increase

power

dissipation.

C 2

2 Ten TTL loads per TTL driver is known as: noise immunity fan-out power

dissipation

propagation

delay

B 2

2 The problem of different current requirements when CMOS logic circuits are

driving TTL logic circuits can usually be overcome by the addition of:

a CMOS

inverting bilateral

switch between the

stages

a TTL tristate

inverting buffer

between the stages

a CMOS

noninverting

bilateral switch

between the

stages

a CMOS

buffer or

inverting

buffer

D 4

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2

Totem-pole outputs ________ be connected ________ because ________.

can, in parallel,

sometimes higher

current is required

cannot, together, if

the outputs are in

opposite states

excessively high

currents can

damage one or both

devices

should, in

series, certain

applications

may require

higher output

voltage

can,

together,

together they

can handle

larger load

currents and

higher

output

voltages

B 4

2 The high input impedance of MOSFETs: allows faster

switching

reduces input

current and power

dissipation

prevents dense

packing

creates low-

noise

reactions

B 2

2 The output current capability of a single 7400 NAND gate when HIGH is

called _____

source current sink current IOH source

current of

IOH

A 2

2 The time needed for an output to change from the result of an input change is

known as:

noise immunity fan-out propagation

delay

rise time C 2

2 The problem of interfacing IC logic families that have different supply voltages

(VCC's) can be solved by using a:

Level-shifter tristate shifter decoupling

capacitor

pull-down

resistor

A 2

2 What is the advantage of using low-power Schottky (LS) over standard TTL

logic?

more power

dissipation

less power

dissipation

cost is less cost is more B 2

2 When is a level-shifter circuit needed in interfacing logic? A level shifter is

always needed.

A level shifter is

never needed.

when the

supply voltages

are the same

when the

supply

voltages are

different

D 2

2 A TTL totem-pole circuit is designed so that the output transistors: are always on

together

provide linear

phase splitting

provide voltage

regulation

are never on

together

D 2

2 The most common TTL series ICs are: E-MOSFET 7400 QUAD AC00 B 1

2 Which family of devices has the characteristic of preventing saturation during

operation?

TTL ECL MOS IIL B 2

2 How many 74LSTTL logic gates can be driven from a 74TTL gate? 10 20 30 40 B 2

2 What is the difference between the 74HC00 series and the 74HCT00 series

of CMOS logic?

The HCT series is

faster.

The HCT series is

slower.

he HCT series

is input and

output voltage

compatible with

TTL.

The HCT

series is not

input and

output

voltage

compatible

with TTL.

C 4

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2 Why are the maximum value of VOL and the minimum value of VOH used to

determine the noise margin rather than the typical values for these parameters?

These are worst-

case conditions.

These are normal

conditions.

These are best-

case conditions.

It doesn't

matter what

values are

used.

A 2

2 What is the standard TTL noise margin? 5.0 V 0.0 V 0.8 V 0.4 V D 2

2 Which logic family is characterized by a multiemitter transistor on the input? ECL CMOS TTL None of the

above

C 2

2 he problem of the VOH(min) of a TTL IC being too low to drive a CMOS

circuit and meet the CMOS requirement of VIH(min) is usually easily

overcome by:

adding a fixed

voltage-divider

bias resistive

network at the

output of the TTL

device

avoiding this

condition and only

using TTL to drive

TTL

adding an

external pull-

down resistor to

ground

adding an

external pull-

up resistor to

VCC

D 4

2 How does the 4000 series of CMOS logic compare in terms of speed and

power dissipation to the standard family of TTL logic?

more power

dissipation and

slower speed

more power

dissipation and

faster speed

less power

dissipation and

faster speed

less power

dissipation

and slower

speed

D 2

2 What should be done with unused inputs to a TTL NAND gate? let them float tie them LOW tie them HIGH None of the

above

C 2

2 Which of the following logic families has the highest maximum clock

frequency?

S-TTL AS-TTL HS-TTL HCMOS B 2

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2 Why is the fan-out of CMOS gates frequency dependent? Each CMOS input

gate has a specific

propagation time

and this limits the

number of

different gates that

can be connected

to the output of a

CMOS gate.

When the

frequency reaches

the critical value,

the gate will only

be capable of

delivering 70% of

the normal output

voltage and

consequently the

output power will

be one-half of

normal; this defines

the upper operating

frequency.

The higher the

number of gates

attached to the

output, the

more frequently

they will have

to be serviced,

thus reducing

the frequency at

which each will

be serviced

with an input

signal.

The input

gates of the

FETs are

predominant

ly capacitive,

and as the

signal

frequency

increases the

capacitive

loading also

increases,

thereby

limiting the

number of

loads that

may be

attached to

the output of

the driving

gate.

D 4

2 What must be done to interface TTL to CMOS? A dropping

resistor must be

used on the CMOS

12 V supply to

reduce it to 5 V for

the TTL.

As long as the

CMOS supply

voltage is 5 V, they

can be interfaced;

however, the fan-

out of the TTL is

limited to five

CMOS gates.

A 5 V Zener

diode must be

placed across

the inputs of the

TTL gates in

order to protect

them from the

higher output

voltages of the

CMOS gates.

A pull-up

resistor must

be used

between the

TTL output-

CMOS input

node and

Vcc; the

value of RP

will depend

on the

number of

CMOS gates

connected to

the node.

D 2

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2 What causes low-power Schottky TTL to use less power than the 74XX series

TTL?

The Schottky-

clamped transistor

Nothing. The 74XX

series uses less

power.

A larger value

resistor

Using

NAND gates

C 2

2 What are the major differences between the 5400 and 7400 series of ICs? The 5400 series

are military grade

and require tighter

supply voltages

and temperatures.

The 5400 series are

military grade and

allow for a wider

range of supply

voltages and

temperatures.

The 7400

series are an

improvement

over the

original 5400s.

The 7400

series was

originally

developed

by Texas

Instruments.

The 5400

series was

brought out

by National

Semiconduct

ors after TI's

patents

expired, as a

second

supply

source.

B 2

2 Which of the following statements apply to CMOS devices? The devices should

not be inserted into

circuits with the

power on.

All tools, test

equipment, and

metal workbenches

should be tied to

earth ground.

The devices

should be

stored and

shipped in

antistatic tubes

or conductive

foam.

All of the

above.

D 2

2 Which of the logic families listed below allows the highest operating

frequency?

74AS ECL HCMOS 54S B 2

2 What is the increase in switching speed between 74LS series TTL and

74HC/HCT (High-Speed CMOS)?

5 10 50 100 B 2

2 What does ECL stand for? electron-coupled

logic;

emitter-coupled

logic;

energy-coupled

logic;

NONE OF

ABOVE

B 2

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2 What is unique about TTL devices such as the 74S00? The gate

transistors are

silicon (S), and the

gates therefore

have lower values

of leakage current.

The S denotes the

fact that a single

gate is present in

the IC rather than

the usual package

of 2–6 gates.

The S denotes a

slow version of

the device,

which is a

consequence of

its higher power

rating.

The devices

use Schottky

transistors

and diodes

to prevent

them from

going into

saturation;

this results

in faster turn

on and turn

off times,

which

translates

into higher

frequency

operation.

D 4

2 he bipolar TTL logic family that was developed to increase switching speed by

preventing transistor saturation is:

emitter-coupled

logic (ECL).

current-mode logic

(CML).

transistor-

transistor logic

(TTL).

emitter-

coupled

logic (ECL)

and

transistor-

transistor

logic (TTL).

D 2

2 In TTL the noise margin is between 0.4 V and 0.8 V. 0.0 V and 0.4 V. 0.0 V and 0.5

V.

0.0V and 0.8

V.

A 2

2 What is the transitive voltage for the voltage input of a CMOS operating from

10V supply

1V 5V 10V 15V B 2

2 The highest noise margin is offered by CMOS TTL ECL BICMOS B 2

2 What is the transitive voltage for the voltage input of a CMOS operating from

10V supply ?

1V 5V 10V 20V B 2

2 The digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS A 2

2 In a positive logic system, logic state 1 corresponds to Positive voltage Higher voltage

level

Zero voltage

level

Lower

voltage level

B 2

2 Which of the following logic families is well suited for high-speed operations ? TTL ECL MOS CMOS B 2

2 Which of the following is the fastest logic? ECL TTL MOS CMOS A 1

2 he digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS c 2

2 A binary digit is called a Bit Byte Number Character A 1

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2

2 Which of the following statements is wrong ? Propagation delay

is the time required

for a gate to

change its state

Noise immunity is

the amount of noise

which can be

applied to the input

of a gate without

causing the gate to

change state

Fan-in of a

gate is always

equal to fan-out

of the same gate

Operating

speed is the

maximum

frequency at

which digital

data can be

applied to a

gate

C 4

2 Which table shows the logical state of a digital circuit output for every possible

combination of logical states in the inputs ?

Function table Truth table Routing table ASCII table B 1

2 The digital logic family which has minimum power dissipation is TTL ECL MOS CMOS D 1

3 In the following question, match each of the items A, B and C on the left with

an approximation item on the right

A. Shift register can be used 1. for code conversion

B. A multiplexer can be used 2. to generate memory slipto select

C. A decoder can be used 3. for parallel to serial conversion

4. as many to one switch

5. for analog to digital conversion

A B C

1 2 3

A B C

3 4 1

A B C

5 4 2

A B C

1 3 5

B 4

3 A standard SOP form has __________ terms that have all the variables in the

domain of the expression.

SUM SUB Mult DIV A 1

3 How many data select lines are required for selecting eight inputs? 1 2 3 4 C 2

3 Half adder circuit is ______? Half of an AND

gate

A circuit to add

two bits together

Half of a

NAND gate

none of

above

B 2

3 The full adder adds the Kth bits of two numbers to the difference of the

previous bits

sum of all previous

bits

carry from ( K -

1 )TH bit

sum of

previous bit

C 2

3 The number of two input multiplexers required to construct a 210 input

multiplexer is,

31 10 127 1023 D 2

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3 A small dot or circle printed on top of an IC indicates Vcc Gnd Pin 14 Pin 1 D 1

3 Which of the following adders can add three or more numbers at a time ? Parallel adder Carry-look-ahead

adder

Carry-save-

adder

D.

Full adder B 2

3 An AND circuit is a memory

circuit

gives an output

when all input

signals are present

simultaneously

is a -ve OR

gate

is a linear

circuit

B 2

3 What are the three output conditions of a three-state buffer? HIGH, LOW, float 1, 0, float both of the

above

neither of

the above

C 2

3 When is it important to use a three-state buffer? when two or more

outputs are

connected to the

same input

when all outputs

are normally HIGH

when all

outputs are

normally LOW

when two or

more outputs

are

connected to

two or more

inputs

A 2

3 The device which changes from serial data to parallel data is COUNTER MULTIPLEXER DEMULTIPLE

XER

FLIP-FLOP C 2

3 A device which converts BCD to Seven Segment is called MULTIPLEXER DEMULTIPLEXE

R

ENCODER DECODER D 2

3 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 C 2

3 A device which converts BCD to Seven Segment is called Encoder Decoder Multiplexer Demultiplex

er

B 2

3 A multiplexer is a logic circuit that accepts one input

and gives several

output

accepts many inputs

and gives many

output

accepts many

inputs and gives

one output

accepts one

input and

gives one

output

C 2

3 In order to implement a n variable switching function, a MUX must have 2n inputs 2n+1 inputs 2n-1 inputs 2n-1 inputs A 2

3 Logic gates with a set of input and outputs is arrangement of Combinational

circuit

Logic circuit Design circuits Register A 2

3 A latch is constructed using two cross-coupled AND and OR

gates

AND gates NAND and

NOR gates

NAND gates D 2

3 A combinational logic circuit which sends data coming from a single source to

two or more separate destinations is

Decoder Encoder Multiplexer Demultiplex

er

D 2

3 Data can be changed from special code to temporal code by using Shift registers Counters Combinational

circuits

A/D

converters

A 2

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3 A device which converts BCD to Seven Segment is called Encoder Decoder Multiplexer Demultiplex

er

3 The gray code equivalent of (1011)2 is 1101 1010 1110 1111 B 2

3 Odd parity of word can beconveniently tested by OR gate AND gate NOR gate XOR gate D 2

3 Which one of the following will give the sum of full adders as output ? Three point

majority circuit

Three bit parity

checker

Three bit

comparator

Three bit

counter

D 2

3 The number of full and half-adders required to add 16-bit numbers is

8 half-adders, 8

full-adders

1 half-adder, 15 full-

adders

16 half-adders,

0 full-adders

4 half-

adders, 12

full-adders

B 2

3 A one-to-four line demultiplexer is to be implemented using a memory. How

many bits must each word have ?

1 bit 2 bits 4 bits 8 bits A 2

3 What logic function is produced by adding an inverter to the output of an AND

gate ?

NAND NOR XOR OR A 1

3 A demultiplexer is used to Route the data

from single input

to one of many

outputs

Select data from

several inputs and

route it to single

output

Perform serial

to parallel

conversion

All of these A 1

3 How many full adders are required to construct an m-bit parallel adder ? m/2 m-1 m m+1 B 1

3 Parallel adders are combinational

logic circuits

sequential logic

circuits

both (a) and

(b)

None of

these

B 1

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3 The digital multiplexer is basically a combination logic circuit to perform the

operation

AND-AND OR-OR AND-OR OR-AND C 2

3 How many lines the truth table for a four-input NOR gate would contain to

cover all possible input combinations ?

4 8 12 16 D 2

3 How many truth tables can be made from one function table ? 1 2 3 ANY NO B 2

3 A comparison between serial and parallel adder reveals that serial order is slower is faster operates at the

same speed as

parallel adder

is more

complicated

A 2

3 What is the largest number of data inputs which a data selector with two

control inputs can have ?

2 4 6 8 B 1

3 If a logic gates has four inputs, then total number of possible input

combinations is

4 8 16 32 C 1

3 If a logic gates has four inputs, then total number of possible input

combinations is

input

combination at the

time

input combination

and the previous

output

input

combination at

that time and

the previous

input

combination

present

output and

the previous

output

A 2

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3 A combinational logic circuit which generates a particular binary word or

number is

Decoder Multiplexer Encoder Demultiplex

er

A 1

3 Which of the following circuit can be used as parallel to serial converter ? Multiplexer Demultiplexer Decoder Digital

counter

A 2

3 In which of the following adder circuits, the carry look ripple delay is

eliminated ?

Half adder Full adder Parallel

adder

Carry-look-

ahead adder

C 2

3 Adders adds 2 bits is called so

because a full adder

involves two half-

adders

needs two

input and

generates two

output

All of these D 2

3

Excess-3 code is known as

Weighted code Cyclic redundancy

code

Self-

complementin

g code

Algebraic

code.

C 1

3 The number of control lines for 32 to 1 multiplexer is 4 16 5 6 C 2

3 The selector inputs to an arithmetic-logic unit (ALU) determine the: selection of the IC arithmetic or logic

function

data word

selection

clock

frequency to

be used

B 2

3 What are the two types of basic adder circuits? half adder and

full adder

half adder and

parallel adder

asynchronous

and

synchronous

one's

complement

and two's

complement

A 2

3 The inverter OR-gate and AND gate are called deeision-making elements

because they can recognize some input while disregarding others. A gate

words,high bytes,low bytes,high character,lo

w

A 2

3 Which one of the following set of gates are best suited for 'parity' checking and

'parity' generation.

AND, OR, NOT

gates

EX-NOR or EX-

OR gates

NAND gates NOR gates B 2

3 What are the three output conditions of a three-state buffer? HIGH, LOW, float 1, 0, float both of the

above

neither of

the above

C 2

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3 When is it important to use a three-state buffer? when two or

more outputs are

connected to the

same input

when all outputs

are normally HIGH

when all

outputs are

normally LOW

when two or

more outputs

are

connected to

two or more

inputs

A 2

3 How many inputs are required for a 1-of-10 BCD decoder? 4 8 10 1 A 1

3

Most demultiplexers facilitate which of the following?decimal to

hexadecimal

single input,

multiple outputsac to dc

odd parity to

even parityB 1

3

One application of a digital multiplexer is to facilitate:

code conversion parity checking

parallel-to-

serial data

conversion

data

generationC 1

3

Select one of the following statements that best describes the parity method of

error detection:best suited for

detecting single-

bit errors in

transmitted

codes.

best suited for

detecting double-bit

errors that occur

during the

transmission of

codes from one

location to another.

A AND B

NONE OF

THE

ABOVE

A 2

3

A multiplexed display:

accepts data inputs

from one line and

passes this data to

multiple output

lines

uses one display to

present two or

more pieces of

information

accepts data

inputs from

multiple lines

and passes this

data to multiple

output lines

accepts data

inputs from

several lines

and

multiplexes

this input

data to four

BCD lines

B 1

3In which of the following gates, the output is 1, if and only if at least one input

is 1?NOR AND OR NAND C 1

3The time required for a gate or inverter to change its state is called Rise time

Decay timePropagation

time

Charging

timeC 1

3The time required for a pulse to change from 10 to 90 percent of its maximum

value is called

Rise time Decay time

Propagation

time

Operating

speedA 1

3

The maximum frequency at which digital data can be applied to gate is called

Operating speed Propagation speed

Binary level

transaction

period

Charging

timeA 1

3What is the minimum number of two-input NAND gates used to perform the

function of two input OR gate ?one two three Four C 2

3Odd parity of word can beconveniently tested by

OR gate AND gate NOR gate XOR gate

D 1

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3Which one of the following will give the sum of full adders as output ? Three point

majority circuit

Three bit parity

checker

Three bit

comparator

Three bit

counterD 1

3

The number of full and half-adders required to add 16-bit numbers is8 half-adders, 8

full-adders

1 half-adder, 15

full-adders

16 half-adders,

0 full-adders

4 half-

adders, 12

full-adders

B 1

3

The time required for a pulse to decrease from 90 to 10 per cent of its

maximum value is called Rise time Decay time

Binary level

transition

period

Propagation

delayB 1

3

Which of the following gates would output 1 when one input is 1 and other

input is 0 ? OR gate AND gate NAND gate AND gate D 1

3

Which of the following statements is wrong ?

Propagation delay

is the time required

for a gate to

change its state

Noise immunity is

the amount of noise

which can be

applied to the input

of a gate without

causing the gate to

change state

Fan-in of a gate

is always equal

to fan-out of the

same gate

Operating

speed is the

maximum

frequency at

which digital

data can be

applied to a

gate

C 1

3 Which of the following expressions is not equivalent to X ' ? X NAND X X NOR X X NAND 1 X NOR 1 D 1

3

Which of the following gates are added to the inputs of the OR gate to convert

it to the NAND gate ? NOT AND OR XOR A 1

3The EXCLUSIVE NOR gate is equivalent to which gate followed by an

inverter ?OR gate AND NAND XOR D 1

3 A one-to-four line demultiplexer is to be implemented using a memory. How

many bits must each word have ?1 BIT 2 BITS 4 BITS 8 BITS A 1

3

What logic function is produced by adding an inverter to the output of an AND

gate ? NAND NOR XOR OR A 1

3Which of the following gates is known as coincidence detector ?

AND GATE OR GATE NOT GATENAND

GATEA 1

3

Which table shows the logical state of a digital circuit output for every possible

combination of logical states in the inputs ? Function table Truth table Routing table ASCII table B 1

3 A positive AND gate is also a negative NAND gate NOR gate AND GATE OR GATE D 1

3

A demultiplexer is used to Route the data

from single input

to one of many

outputs

Select data from

several inputs and

route it to single

output

Perform serial

to parallel

conversion

All of these A 1

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3

An OR gate can be imagined as

Switches

connected in series

Switches connected

in parallel

MOS

transistors

connected in

series

None of

these B 1

3

Which combination of gates does not allow the implementation of an arbitrary

boolean function?OR gates and

AND gates only

OR gates and

exclusive OR gate

only

OR gates and

NOT gates only

NAND gates

onlyA 1

3How many full adders are required to construct an m-bit parallel adder ?

m/2 m-1 m m+1 B 2

3Parallel adders are combinational

logic circuits

sequential logic

circuitsboth (a) and (b)

None of

theseA 1

3The digital multiplexer is basically a combination logic circuit to perform the

operationAND-AND OR-OR AND-OR OR-AND C 1

3

The output of NOR gate is High if all of its

inputs are high

Low if all of its

inputs are low

High if all of its

inputs are low

High if only

of its inputs

is low

C 1

3How many lines the truth table for a four-input NOR gate would contain to

cover all possible input combinations ?4 8 12 16 D 1

3A toggle operation cannot be performed using a single

NOR gate AND gate NAND gate XOR gate B 1

3

Which table shows the electrical state of a digital circuit's output for every

possible combination of electrical states in the inputs ? Function table Truth table Routing table ASCII table A 1

3

What is the minimum number of 2 input NAND gates required to implement

the function

F = (x'+y') (z+w)6 5 4 3 C 1

3How many truth tables can be made from one function table ?

One Two ThreeAny

numbersB 1

3

A comparison between serial and parallel adder reveals that serial order

is slower is faster

operates at the

same speed as

parallel adder

is more

complicatedA 1

3What is the largest number of data inputs which a data selector with two

control inputs can have ?2 4 8 16 B 1

3

If a logic gates has four inputs, then total number of possible input

combinations is 4 8 16 32 C 1

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3

A combinational circuit is one in which the output depends on the

input combination

at the time

input combination

and the previous

output

input

combination at

that time and

the previous

input

combination

present

output and

the previous

output

A 1

3

The function of a multiplexer is

to decode

information

to select 1 out of N

input data sources

and to transmit it to

single channel

to transit data

on N lines

to perform

serial to

parallel

conversion

B 1

3A combinational logic circuit which generates a particular binary word or

number isDecoder Multiplexer Encoder

Demultiplex

erA 1

3Which of the following circuit can be used as parallel to serial converter ?

Multiplexer Demultiplexer DecoderDigital

counterA 1

3In which of the following adder circuits, the carry look ripple delay is

eliminated ?Half adder Full adder Parallel adder

Carry-look-

ahead adderC 1

3

Adders

adds 2 bits

Is called so because

a full adder

involves two half-

adders

needs two input

and generates

two output

All of these A 1

3 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? 1 2 4 8 C 1

3For the device shown here, let all D inputs be LOW, both S inputs be HIGH,

and the input be LOW. What is the status of the Y output?LOW HIGH Don't Care

Cannot be

determinedA 1

3 Convert BCD 0001 0010 0110 to binary. 1111110 1111000 1111101 1111111 A 2

3 Convert BCD 0001 0111 to binary. 10101 10001 10010 11000 C 2

3 How many data select lines are required for selecting eight inputs? 1 2 3 4 C 1

3How many 1-of-16 decoders are required for decoding a 7-bit binary number?

5 6 7 8 D 1

3

The implementation of simplified sum-of-products expressions may be easily

implemented into actual logic circuits using all universal ________ gates with

little or no increase in circuit complexity. (Select the response for the blank

space that will BEST make the statement true.)

AND/OR NAND NOR OR/AND B 1

3

Which of the following statements accurately represents the two BEST

methods of logic circuit simplification?Boolean algebra

and Karnaugh

mapping

Karnaugh mapping

and circuit

waveform analysis

Actual circuit

trial and error

evaluation and

waveform

analysis

Boolean

algebra and

actual circuit

trial and

error

evaluation

A 1

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3

Which of the following combinations cannot be combined into K-map groups?

Corners in the

same row

Corners in the same

column

Diagonal

corners

Overlapping

combination

s

C 2

3

As a technician you are confronted with a TTL circuit board containing dozens

of IC chips. You have taken several readings at numerous IC chips, but the

readings are inconclusive because of their erratic nature. Of the possible faults

listed, select the one that most probably is causing the problem.

A defective IC

chip that is

drawing excessive

current from the

power supply

A solar bridge

between the inputs

on the first IC chip

on the board

An open input

on the first IC

chip on the

board

A defective

output IC

chip that has

an internal

open to V cc

C 2

3 Which gate is best used as a basic comparator? NOR OR Exclusive-OR AND C 1

3The device shown here is most likely a ________.

comparator multiplexer demultiplexerparity

generatorC 2

3For the device shown here, assume the D input is LOW, both S inputs are

HIGH, and the input is HIGH. What is the status of the outputs?All are HIGH. All are LOW.

All but are

LOW.

All but are

HIGH.A 1

3

In VHDL, macrofunctions is/are:

digital circuits. analog circuits.a set of bit

vectors.

preprogram

med TTL

devices.

D 1

3 Which of the following expressions is in the product-of-sums form? (A + B )(C + D ) (AB )(CD ) AB (CD ) AB + CD A 2

3

Which of the following is an important feature of the sum-of-products form of

expressions?

All logic circuits

are reduced to

nothing more than

simple AND and

OR operations.

The delay times are

greatly reduced

over other forms.

No signal must

pass through

more than two

gates, not

including

inverters.

The

maximum

number of

gates that

any signal

must pass

through is

reduced by a

factor of

two.

A 1

3

An output gate is connected to four input gates; the circuit does not function.

Preliminary tests with the DMM indicate that the power is applied; scope tests

show that the primary input gate has a pulsing signal, while the interconnecting

node has no signal. The four load gates are all on different ICs. Which

instrument will best help isolate the problem?

Current tracer Logic probe OscilloscopeLogic

analyzerA 1

3

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a

comparator. What are the output levels?A > B = 1, A < B =

0, A < B = 1

A > B = 0, A < B =

1, A = B = 0

A > B = 1, A <

B = 0, A = B =

0

A > B = 0, A

< B = 1, A =

B = 1

C 4

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3

A logic probe is placed on the output of a gate and the display indicator is dim.

A pulser is used on each of the input terminals, but the output indication does

not change. What is wrong? The output of the

gate appears to be

open.

The dim indication

on the logic probe

indicates that the

supply voltage is

probably low.

The dim

indication is a

result of a bad

ground

connection on

the logic probe.

The gate

may be a

tristate

device.

A 1

3

Each "1" entry in a K-map square represents:

a HIGH for each

input truth table

condition that

produces a HIGH

output.

a HIGH output on

the truth table for

all LOW input

combinations.

a LOW output

for all possible

HIGH input

conditions.

a DON'T

CARE

condition for

all possible

input truth

table

combination

s.

A 1

3

Looping on a K-map always results in the elimination of:variables within

the loop that

appear only in

their

complemented

form.

variables that

remain unchanged

within the loop.

variables within

the loop that

appear in both

complemented

and

uncomplemente

d form.

variables

within the

loop that

appear only

in their

uncompleme

nted form.

C 2

3

What will a design engineer do after he/she is satisfied that the design will

work?Put it in a flow

chart

Program a chip and

test it

Give the design

to a technician

to verify the

design

Perform a

vector testB 2

3

What is the indication of a short on the input of a load gate?

Only the output of

the defective gate

is affected.

There is a signal

loss to all gates on

the node.

The affected

node will be

stuck in the

LOW state.

There is a

signal loss to

all gates on

the node,

and the

affected

node will be

stuck in the

LOW state.

D 1

3

In HDL, LITERALS is/are:

digital systems. scalars.binary coded

decimals.

a numbering

system.B 1

3 Which of the following expressions is in the sum-of-products form? (A + B )(C + D ) (AB )(CD ) AB (CD ) AB + CD D 1

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3 The carry propagation can be expressed as ________. Cp = AB Cp = A + B B 1

3

A decoder can be used as a demultiplexer by ________.

tying all enable

pins LOW

tying all data-select

lines LOW

tying all data-

select lines

HIGH

using the

input lines

for data

selection and

an enable

line for data

input

D 1

3How many 4-bit parallel adders would be required to add two binary numbers

each representing decimal numbers up through 30010?1 2 3 4 C 1

3

Which statement below best describes a Karnaugh map?

A Karnaugh map

can be used to

replace Boolean

rules.

The Karnaugh map

eliminates the need

for using NAND

and NOR gates.

Variable

complements

can be

eliminated by

using Karnaugh

maps.

Karnaugh

maps

provide a

visual

approach to

simplifying

Boolean

expressions.

D 1

3

A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW

outputs. Which output goes LOW when the inputs are 1001? 0 3 9

None. All

outputs are

HIGH.

C 1

3A full-adder has a Cin = 0. What are the sum and the carry (Cout) when A = 1

and B = 1? = 0, Cout = 0 = 0, Cout = 1

= 1, Cout =

0

= 1,

Cout = 1B 1

3When adding an even parity bit to the code 110010, the result is ________.

1110010 110010 1111001 1101 A 1

3

Which of the following combinations of logic gates can decode binary 1101?One 4-input AND

gate

One 4-input AND

gate, one OR gate

One 4-input

NAND gate,

one inverter

One 4-input

AND gate,

one inverter

D 1

3

What is the indication of a short to ground in the output of a driving gate?

Only the output of

the defective gate

is affected.

There is a signal

loss to all load

gates.

The node may

be stuck in

either the HIGH

or the LOW

state.

The affected

node will be

stuck in the

HIGH state.

B 1

3How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-

to-4-line encoder, have?3 4 5 6 B 1

3A half-adder does not have ________.

carry in carry out two inputsall of the

aboveA 1

3

________ is a correct combination for an ODD-parity data transmission

system.data = 1101 1011

parity = 1

data = 1101 0010

parity = 0

data = 0001

0101

parity = 1

data = 1010

1111

parity = 0

A 1

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3A circuit that can convert one of ten numerical keys pressed on a keyboard to

BCD is a ________.priority encoder decoder multiplexer

demultiplexe

rA 1

3The ________ prefix on IC's indicates a broader operating temperature range,

and the devices are generally used by the military.54 2N 74 TTL A 1

3

When an open occurs on the input of a TTL device, the output will ________.

go LOW, because

there is no current

in an open circuit

react as if the open

input were a HIGH

go HIGH, since

full voltage

appears across

an open

still be good,

if only the

good inputs

are used

B 1

3The largest truth table that can be implemented directly with an 8-line-to-1-line

MUX has ________.3 rows 4 rows 8 rows 16 rows C 1

3

Parity generation and checking is used to detect ________.

which of two

numbers is greater

errors in binary data

transmission

errors in

arithmetic in

computers

when a

binary

counter

counts

incorrectly

B 1

3 Except for ________, STD_LOGIC may have the following values. 'z' 'U' '?' 'L' C 1

3A gate that could be used to compare two logic levels and provide a HIGH

output if they are equal is a(n) ________.XOR gate XNOR gate NAND gate NOR gate B 1

3VHDL is very strict in the way it allows us to assign and compare ________

such as signals, variables, constants, and literals.objects

LOGIC_VECTOR

Sdesigns arrays A 1

3The AND-OR-INVERT gates are designed to simplify implementation of

________.POS logic

DeMorgan's

theoremNAND logic SOP logic B 1

3

The output of a gate has an internal short; a current tracer will ________.

identify the

defective gate

show whether the

gate is shorted to

V cc or ground

probably not be

able to locate

the problem

be able to

identify the

defective

load node

A 1

3Parity generators and checkers use ________ gates.

exclusive-AND exclusive-OR/NOR exclusive-ORexclusive-

NANDB 1

3

The 7447A is a BCD-to-7-segment decoder with ripple blanking input and

output functions. The purpose of these lines is to ________. turn off the display

for any

nonsignificant

digit

turn off the display

for any zero

turn off the

display for

leading or

trailing zeros

test the

display to

assure all

segments are

operational

A 1

3One reason for using the sum-of-products form is that it can be implemented

using all ________ gates without much difficulty.NOR NAND AND DOOR B 1

3

When an open occurs on the input of a CMOS gate, the output will ________.

go LOW, because

there is no current

in an open circuit

react as if the open

input were a HIGH

go HIGH, since

full voltage

appears across

an open

be

unpredictabl

e; it may go

HIGH or

LOW

D 2

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3

To subtract a signed number (the subtrahend) from another signed number (the

minuend) in the 2's complement system, the minuend is ________.complemented

only if it is positive

complemented only

if it is negative

always

complemented

never

complement

ed

D 2

3In an odd-parity system, the data that will produce a parity bit = 1 is ________.

data = 1010011 data = 1111000 data = 1100000All of the

aboveD 2

3

The addition of two signed numbers in the 2's complement system can cause

overflow. For overflow to occur both numbers must ________. be positive be negativehave the same

sign

have

opposite

signs

C 2

3

A Karnaugh map will ________.

eliminate the need

for tedious

Boolean

simplifications

allow any circuit to

be implemented

with just AND and

OR gates

produce the

simplest sum-of-

products

expression

give an

overall

picture of

how the

signals flow

through the

logic circuit

A 2

3

An 8-bit binary number is input to an odd parity generator. The parity bit will

equal 1 only if ________.the number is odd

the number of 1s in

the number is odd

the number is

even

the number

of 1s in the

number is

even

D 2

3

Two 4-bit comparators are cascaded to form an 8-bit comparator. The

cascading inputs of the most significant 4 bits should be connected ________.to the outputs from

the least significant

4-bit comparator

to the cascading

inputs of the least

significant 4-bit

comparator

A = B to a logic

high, A < b and

a > B to a logic

low

ground A 1

3When Karnaugh mapping, we must be sure to use the ________ number of

loops.maximum minimum median Karnaugh B 1

3 The final output of a POS circuit is generated by ________. an AND an OR a NOR a NAND A 2

3After each circuit in a subsection of a VHDL program has been ________,

they can be combined and the subsection can be tested.designed tested engineered produced B 1

3The ________ series of IC's are pin, function, and voltage-level compatible

with the 74 series IC's.ALS CMOS HCT 2N C 2

3The ________ circuit produces a HIGH output whenever the two inputs are

equal.exclusive-AND exclusive-NAND exclusive-NOR

exclusive-

ORC 2

3A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1,

B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be ________.1100 10101 11000 11 C 2

3 The ________ statement evaluates the variable status. IF/THEN IF/THEN/ELSE CASE ELSIF A 2

3In VHDL, data can be each of the following types except ________.

BIT BIT_VECTOR STD_LOGICSTD_VECT

ORD 2

3When grouping cells within a K-map, the cells must be combined in groups of

________.2's 1, 2, 4, 8, etc. 4's 3's B 1

3The ________ circuit produces a HIGH output whenever the two inputs are

unequal.exclusive-AND exclusive-NOR exclusive-OR

inexclusive-

ORC 1

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3

Occasionally, a particular logic expression will be of no consequence in the

operation of a circuit, such as in a BCD-to-decimal converter. These result in

________ terms in the K-map and can be treated as either ________ or

________, in order to ________ the resulting term.

don't care, 1's, 0's,

simplify

spurious, AND's,

OR's, eliminate

duplicate, 1's,

0's, verify

spurious, 1's,

0's, simplifyA 2

3

A good rule of thumb for determining the pin numbers of dual-in-line package

IC chips would be to place the notch to your right and pin #1 will always be in

the lower right corner.

TRUE FALSENone of the

above

Can not

predictB 2

3The carry output of each adder in a ripple adder provides an additional sum

output bit.TRUE FALSE

None of the

above

Can not

predictA 1

3Truth tables are great for listing all possible combinations of independent

variables.TRUE FALSE

None of the

above

Can not

predictA 1

3A square in the top row of a K-map is considered to be adjacent to its

corresponding square in the bottom row.TRUE FALSE

None of the

above

Can not

predictA 1

3To implement the full-adder sum functions, two exclusive-OR gates can be

used.TRUE FALSE

None of the

above

Can not

predictA 1

3The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active-low

outputs is 1110. As a result, output line 7 is driven LOW.TRUE FALSE

None of the

above

Can not

predictB 2

3When decisions demand two possible actions, the IF/THEN/ELSE control

structure is used.TRUE FALSE

None of the

above

Can not

predictA 2

3TTL stands for transistor-technology-logic.

TRUE FALSENone of the

above

Can not

predictB 1

3The 54 prefix on ICs indicates a broader operating temperature range,

generally intended for military use.TRUE FALSE

None of the

above

Can not

predictA 2

3This is an example of a POS expression:

TRUE FALSENone of the

above

Can not

predictA 2

3The abbreviation for an exclusive-OR gate is XOR.

TRUE FALSENone of the

above

Can not

predictA 2

3In an even-parity system, the parity bit is adjusted to make an even number of

one bits.TRUE FALSE

None of the

above

Can not

predictA 2

3In an even-parity system, the following data will produce a parity bit = 1.

data = 1010011TRUE FALSE

None of the

above

Can not

predictB 2

3The following combination is correct for an ODD parity data transmission

system: data = 011011100 and parity = 0TRUE FALSE

None of the

above

Can not

predictA 1

3The XOR gate will produce a HIGH output if only one but not both of the

inputs is HIGH.TRUE FALSE

None of the

above

Can not

predictA 1

3When decisions demand one of many possible actions, the ELSIF control

structure is used.TRUE FALSE

None of the

above

Can not

predictA 1

3The K-map provides a "graphical" approach to simplifying sum-of-products

expressions.TRUE FALSE

None of the

above

Can not

predictA 1

3Even parity is the condition of having an even number of 1s in every group of

bits.TRUE FALSE

None of the

above

Can not

predictA 1

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3The look-ahead carry method suffers from propagation delays.

TRUE FALSENone of the

above

Can not

predictB 1

3A pull-up resistor is a resistor used to keep a given point in a circuit HIGH

when in the active state.TRUE FALSE

None of the

above

Can not

predictA 1

3A data selector is also called a demultiplexer.

TRUE FALSENone of the

above

Can not

predictB 1

3A digital circuit that converts coded information into a familiar or non-coded

form is known as an encoder.TRUE FALSE

None of the

above

Can not

predictB 1

3An exclusive-OR gate will invert a signal on one input if the other is always

HIGH.TRUE FALSE

None of the

above

Can not

predictA 1

3The following combination is correct for an EVEN parity data transmission

system: data = 100111100 and parity = 0TRUE FALSE

None of the

above

Can not

predictB 2

3The CASE control structure is used when an expression has a list of possible

values.TRUE FALSE

None of the

above

Can not

predictA 2

3An encoder in which the highest and lowest value input digits are encoded

simultaneously is known as a priority encoder.TRUE FALSE

None of the

above

Can not

predictB 2

3Three select lines are required to address four data input lines.

TRUE FALSENone of the

above

Can not

predictB 2

3Single looping in groups of three is a common K-map simplification technique.

TRUE FALSENone of the

above

Can not

predictB 2

3 In true sum-of-products expressions, the inversion signs cannot cover more

than single variables in a term.TRUE FALSE

None of the

above

Can not

predictA 2

3A combinatorial logic circuit has memory characteristics that "remember" the

inputs after they have been removed.TRUE FALSE

None of the

above

Can not

predictB 2

4 Which of the following is not a form of multivibrator? Astable. Monostable. Tristable. Bistable. C 1

4

A J-K flip-flop has two control inputs. What happens to the Q output on the

active edge of the clock if both control inputs are asserted simultaneously?

The Q output

toggles to the other

state.

The Q output is set

to 1.

The Q output is

reset to 0.

The Q

output

remains

unchanged.

A

2

4

A master/slave bistable is formed using two bistable connected in series.

TRUE False A 1

4

An astable has two metastable states and produces the function of a digital

oscillator

TRUE False A 1

4

In synchronous counters the clock input of each of the bistables are connected

together so that each changes state at the same time. TRUE False A 1

4

1: When the maximum clock rate is quoted for a logic family, then it applies to

a shift register flip-flop counter Multiplexer B 1

Unit 4-Sequntial Logic

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4

2: The number of flip-flops required in a modulo N counter is

log2 (N) + 1 log2(N-1) log2 (N) N log2 (N) C 2

4

3: Flip-flop outputs are always

Complimentary The same

Independent of

each other

same as

previous

input A 1

4

4: How many gates (minimum) are needed for a 3-bit up-counter using

standard binary and using T lip-lops ? Assume unlimited fan-in. 6 3 2 1 C 2

4 5: The clear data and present input of the JK lip-lop are known as

Synchronous

inputs Directed inputs Either (a) or (b) None of theseC 1

4 A mod-2 counter followed by a mod-5 counter is

Same as a mode-5

counter followed

by a mod- 2

counter

A decade counter

A mod-7

counter

Ripple carry

Counter A 1

4

What is the maximum counting speed of a 4-bit binary counter which is

composed of flip-flops with a propagation delay of 25 ns ? 1 MHz 10 MHz 100 MHz 8 MHz B 2

4

8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q

output. A clock pulse is fed to its clock input. The flip-lop will now

Change its state at

each clock pulse

Go to state 1 and

stay there

Go to state 0

and stay there

Retain its

previous

state D 2

4

9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is

applied at the input S,then the output

Q will flip from 0

to 1 and then back

to 0

Q will flip from 0

to 1 and then back

to 0

Q will flip from

1 to 0

Q will flip

from 0 to 1 D 2

4 The output of a sequential circuit depends on Present inputs only

Past outputs only

Both present

and past inputs

Present

outputs only

C 2

4 The ring counter is analogous to Toggle switch Latch Stepping switch J-K flip-flop C 1

4 12: In a digital counter circuit feedback loop is introduced to Improve distortion Improve stability

Reduce the

number of input

pulses to reset

the counter

Asynchrono

us input and

output

pulses C 1

4

A J-K lip-lop has its J-input connected to logic level 1 and its input to the Q

output pulse is fed to its clock input the flip-flop will now

Change its state at

each clock pulse

Go to state 1 and

stay there

Go to state 0

and stay there

Retain its

present state A 2

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4 Which of the following conditions must be met to avoid race around problem ? Δ t < tp < T T > Δt > tp 2 tp < Δt < T

None of

these B 2

4

Match List I with List II and select the correct answer form the codes given

below the list List I

A. A shift register can be

B. A multiplexer

C. A decoder can List II

1.for parallel to serial conversion

2.to generate memory can be used chip select

3.for parallel to serial conversion

CODES:

A B C

3 1 2 2 3 1 1 3 2 1 2 3 C 4

4

With the use of an electronic counter six capsules are to be filled in bottles

automatically. In such a counter what will be the number of flip-flops required

? 3 12 6 8 C

2

4 A pulse train can be delayed by a finite number of clock periods using

A serial-in serial-

out shift register

A serial-in parallel-

out shift register Both (a) and (b)

A parallel-in

parallel-out

shift register D

1

4 How many illegitimate states has synchronous mod-6 counter ? 3 2 1 6 A 1

4 A 2 bit binary multiplier can be implemented using 2 input ANDs only

2 input XORs and 4

input AND gates

only

2 input NORs

and one XNOR

gate

NOR gates

and shift

registers B

2

4 A ring counter is same as up-down counter parallel-counter shift register

Ripple carry

Counter C

1

4 The dynamic hazard problem occurs in

Combinational

circuit alone

Sequential circuit

only Both (a) and (b)

None of

these C

1

4 A n-stage ripple counter will count up to 2n

2n-1

n 2n-1

A 1

4 The clock signals are used in sequential logic circuits to

Tell the time of the

day

Tell how much time

has elapsed since

the system was

turned on

Carry parllel

data signals

Synchronize

events in

various parts

of system D

2

4 74L5138 chip functions as

Decoder/demultipl

exer

Encoder

Multiplexer

Demultiplex

er

A

1

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4

A sequential circuit outputs a ONE when an even number (> 0) of one's are

input; otherwise the output is ZERO. The minimum number of states required

is 0 1 2

None of

these C

2

4 A shift register can be used for Digital delay line

Serial to parallel

conversion

Parallel to serial

conversion All of these D

1

4 Popular application of flip-flop are Transfer register Shift registers Counters All of these D 2

4

For which of the following flip-flops, the output is clearly defined for all

combinations of two inputs ?

Q type flip-flop

R-S flip-lop J-K flip-lop D flip-flop C 2

4

When a large number of analog signals are to be converted an analog

multiplexer is used. In this case most suitable A.D. converter will be

Ripple carry

counter type Dual stop type

Forward

counter type

Successive

approximatio

n type D 2

4 To build a mod-19 counter the number of flip-flops required is 3 5 7 9 B 2

4 The astable multivibrator has

Two quasi stable

states Two stable states

One stable and

one quasi-stable

state

None of

these A 2

4

How many bits are required to encode all twenty six letters, ten symbols, and

ten numerals ? 5 6 10 48 B 2

4

The functional difference between S-R flip-flop and J-K flip-flop is that J-K

flip-flop

is faster than S-R

flip-flop

Has a feed-back

path

Accepts both

inputs 1

Both (a) and

(b) C 1

4 In a positive edge triggered JK flip-flop, a low J and low K produces No change Low state

High state

None of theseA 1

4

When an inverter is placed between both inputs of an SR flip-flop, then

resulting flip-lop is JK flip-flop D flip-flop SR flip-flop

Master slave

JK flip-flop B 2

4

A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in

the 'toggle' mode. The frequency of the signal at the output will be 1 MHz 2 MHz 6 MHz 8 MHz D 2

4 The master slave JK lip-flop is effectively a combination of

A SR flip-flop and

a T flip-flop

An SR flip-lfop and

a D flip-flop

A T flip-flop

and a D flip-

flop

Two D flip-

flops A 2

4 It is difficult to design asynhronous sequential circuit because

External clock is to

be provided It is more complex Both (a) and (b)

Generally

they involve

stability

problem D 2

4 A stable multivibrator is used as Comparator circuit Demultiplexer

Frequency to

voltage

converter

Voltage to

frequency

converter A 2

4 How many flip-flop are needed to divide the input frequency by 64 ? 2 5 6 8 C 1

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4

41: In a ripple counter using edge triggered JK flfp-flops, the pulse input is

applied to the

clock input of all

flip-flops

clock input of one

flip-flops

J and K inputs

of all flip-flops

J and K

inputs of one

flip-flop C 1

4

The number of clock pulses needed to shift one byte of data from input to the

output of a 4-bit shift register is 10 12 16 32 C 2

4 The main difference between JK and RS flip-flop is that

JK flip flop needs

a clock pulse

There is a feedback

in JK lip-lop

JK flip-flop

accepts both

inputs as 1

JK flip-flop

is acronym

of Junction

cathode

multivibrator C 2

4

Which of the following unit will choose to transform decimal number to binary

code ? Encoder Decoder Multiplexer Counter A

1

4

The flip-flops which operate in synchronism with external clock pulses are

known as

Synchronous flip-

flop

Asynchronous flip-

flop

Either of the

above

None of

these A

1

4 Which of the following flip-flop is free from race-around problem ? Q flip-flop T flip-flop SR flip-flop

Master-slave

JK flip-flop D

2

4

If the input J is connected through K input of J-K, then flip-flop will behave as

a D type flip-flop T type flip-flop S-R flip-flop

Master slave

JK flip-flop A

2

4

If a clock with time period 'T' is used with n stage shift register, then output of

final stage will be delayed by nT sec (n-1)T sec n/T sec (2n+1)T sec B

2

4 Register is a

set of capacitor

used to register

input instructions

in a digital

computer

set to paper tapes

and cards put in a

file

temporary

storage unit

within the CPU

having

dedicated or

general purpose

use

part of the

main

memory

C

1

4 The number of flip-flops required in a decade counter is 3 4 8 10 B 1

4 If in a shift resistor Q0 is fed back to input the resulting counter is

Twisted ring with

N : 1 scale

Ring counter with

N : 1 scale

Twisted ring

with 2N : 1

scale

Ring counter

with 2 N : 1

scale C

1

4

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock

signal(s) will be required to shift the value completely out of the register.

1 2 4 8 D 2

4 In a sequential circuit the next state is determined by ________ and _______

State variable,

current state

Current state, flip-

flop output

Current state

and external

input

Input and

clock signal

applied D 2

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4

The divide-by-60 counter in digital clock is implemented by using two

cascading counters: Mod-6, Mod-10 Mod-50, Mod-10

Mod-10, Mod-

50

Mod-50,

Mod-6 A 2

4

In NOR gate based S-R latch if both S and R inputs are set to logic 0, the

previous output state is maintained. True FALSE A 2

4

The minimum time for which the input signal has to be maintained at the input

of flip-flop is called ______ of the flip-flop.

Set-up time Hold time

Pulse Interval

time

Pulse

Stability

time (PST) B 2

4 74HC163 has two enable input pins which are _______ and _________ ENP, ENT ENI, ENC ENP, ENC ENT, ENI A 4

4

____________ is said to occur when multiple internal variables change due to

change in one input variable Clock Skew Race condition Hold delay

Hold and

Wait B 2

4 The _____________ input overrides the ________ input

Asynchronous,

synchronous

Synchronous,

asynchronous

Preset input

(PRE), Clear

input (CLR)

Clear input

(CLR),

Preset input

(PRE) A 4

4 A decade counter is __________. Mod-3 counter Mod-5 counter Mod-8 counter

Mod-10

counter D 2

4 In asynchronous transmission when the transmission line is idle, _________

It is set to logic

low

It is set to logic

high

Remains in

previous state

State of

transmission

line is not

used to start

transmission B 2

4 A Nibble consists of _____ bits 2 4 8 16 B 1

4 The output of this circuit is always ________. 1 0 A Abar C 1

4 Excess-8 code assigns _______ to “-8” 1110 1100 1000 0 D 1

4 The voltage gain of the Inverting Amplifier is given by the relation ________

Vout / Vin = - Rf /

Ri

Vout / Rf = - Vin /

Ri

Rf / Vin = - Ri /

Vout

Rf / Vin =

Ri / Vout A 2

4 LUT is acronym for _________ Look Up Table

Local User

Terminal

Least Upper

Time Period

None of

given

options A 2

4 The three fundamental gates are ___________

AND, NAND,

XOR OR, AND, NAND

NOT, NOR,

XOR

NOT, OR,

AND D 1

4

The total amount of memory that is supported by any digital system depends

upon ______

The organization

of memory

The structure of

memory

The size of

decoding unit

The size of

the address

bus of the

microproces

sor D 2

4 Stack is an acronym for _________ FIFO memory LIFO memory Flash Memory

Bust Flash

Memory B 2

4 Addition of two octal numbers “36” and “71” results in ________ 213 123 127 345 C 2

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4 ___________ is one of the examples of synchronous inputs. J-K input EN input

Preset input

(PRE)

Clear Input

(CLR) A 2

4

__________occurs when the same clock signal arrives at different times at

different clock inputs due to

propagation delay

Race condition Clock Skew Ripple Effect

None of

given

options B 2

4

Consider an up/down counter that counts between 0 and 15, if external

input(X) is “0” the counter counts

upward (0000 to 1111) and if external input (X) is “1” the counter counts

downward (1111 to 0000), now

suppose that the present state is “1100” and X=1, the next state of the counter

will be ___________

0 1101 1011 1111 B 1

4

In a state diagram, the transition from a current state to the next state is

determined by

Current state and

the inputs

Current state and

outputs

Previous state

and inputs

Previous

state and

outputs A 1

4 ________ is used to simplify the circuit that determines the next state. State diagram Next state table State reduction

State

assignment D 2

4

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock

signal(s) will be required to shift the value completely out of the register.

1 2 4 8 D 1

4

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish

to store the nibble 1100. What

will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

1100 11 0 1111 C 2

4 LUT is acronym for _________ Look Up Table

Local User

Terminal

Least Upper

Time Period

None of

given

options A 2

4 The diagram given below represents __________ Demorgans law Associative law

Product of sum

form

Sum of

product form D 2

4

The operation of J-K flip-flop is similar to that of the SR flip-flop except that

the J-K flip-flop ___________

Doesn’t have an

invalid state

Sets to clear when

both J = 0 and K =

0

It does not

show transition

on change in

pulse

It does not

accept

asynchronou

s inputs A 1

4 A multiplexer with a register circuit converts _________

Serial data to

parallel

Parallel data to

serial

Serial data to

serial

Parallel data

to parallel B 1

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4 A GAL is essentially a ________.

Non-

reprogrammable

PAL

PAL that is

programmed only

by the manufacturer Very large PAL

Reprogramm

able PAL D 2

4 in ____________, all the columns in the same row are either read or written. Sequential Access MOS Access

FAST Mode

Page Access

None of

given

options C 2

4 How many flip-flops are required to produce a divide-by-32 device? 2 5 6 4 B 2

4

A reduced state table has 18 rows. The minimum number of flip flops needed

to implement the sequential machine is 18 9 5 4 C 2

4

Advantage of synchronous sequential circuits over asynchronous ones is

faster operation

ease of avoiding

problems due to

hazard

lower hardware

requirement

better noise

immunity A

1

4

The characteristic equation of a JK flip flop is

Qn+1=J.Qn+K.Qn

Qn+1=J.Q’n+K’.Q

n Qn+1=QnJ.K

Qn+1=(J+K)

Qn B

1

4

WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE

SET TO LOGIC ZERO -------

THE FLOP-FLOP

IS TRIGGERED Q=0 AND Q‟=1

Q=1 AND

Q‟=0

THE

OUTPUT

OF FLIP-

FLOP

REMAINS

UNCHANG

ED D

2

4

In ________ Q output of the last flip-flop of the shift register is connected to

the data input of the first

flip-flop of the shift register.

Moore machine Meally machine

Johnson

counter Ring counter D

2

4

5-BIT JOHNSON COUNTER SEQUENCES THROUGH ____ STATES

7 10 32 25 B

2

4

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock

signal(s) will be required to shift

the value completely out of the register.

1 2 4 8 D

1

4

AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT

WILL BE THE VALUE OF

REGISTER AFTER THREE CLOCK PULSES?

2 4 6 8 D

1

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4

The alternate solution for a multiplexer and a register circuit is _________

Parallel in / Serial

out shift register

Serial in / Parallel

out shift register

Parallel in /

Parallel out

shift register

Serial in /

Serial Out

shift register A

1

4

A multiplexer with a register circuit converts _________

Serial data to

parallel

Parallel data to

serial

Serial data to

serial

Parallel data

to parallel B 2

4

A synchronous decade counter will have _______ flip-flops

3 4 7 10 B 2

4

In ________ outputs depend only on the current state.

Mealy machine Moore Machine

State Reduction

table

State

Assignment

table B

1

4

Given the state diagram of an up/down counter, we can find ________

The next state of a

given present state

The previous state

of a given present

state

Both the next

and previous

states of a given

state

The state

diagram

shows only

the

inputs/output

s of a given

states A

1

4

THE HOURS COUNTER IS IMPLEMENTED USING __________

ONLY A SINGLE

MOD-12

COUNTER IS

REQUIRED

MOD-10 AND

MOD-6

COUNTERS

MOD-10 AND

MOD-2

COUNTERS

A SINGLE

DECADE

COUNTER

AND A

FLIP-FLOP D

2

4

The design and implementation of synchronous counters start from _________

Truth table k-map state table state diagram D

2

4

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY

USING A ___________ GATED FLIP-

FLOPS

PULSE

TRIGGERED FLIP-

FLOPS

POSITIVE-

EDGE

TRIGGERED

FLIP-FLOPS

NEGATIVE-

EDGE

TRIGGERE

D FLIP-

FLOPS D

2

4 ___________ is one of the examples of synchronous inputs. J-K input EN input

Preset input

(PRE)

Clear Input

(CLR) A

1

4

A positive edge-triggered flip-flop changes its state when ________________ Low-to-high

transition of clock

High-to-low

transition of clock

Enable input

(EN) is set

Preset input

(PRE) is set A

1

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4

Flip flops are also called _____________

Bi-stable

dualvibrators

Bi-stable

transformer

Bi-stable

multivibrators

Bi-stable

singlevibrato

rs C

1

4

A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED

BY THE USER AND NOT BY

THE MANUFACTURER.

TRUE FALSE A 2

4

THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS,

CONNECTED TO FORM A 16-INPUT

MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT

__________ GATE

AND OR NAND XOR B 2

4

A particular half adder has 2 INPUTS AND 1

OUTPUT

2 INPUTS AND 2

OUTPUT

3 INPUTS

AND 1

OUTPUT

3 INPUTS

AND 2

OUTPUT B 2

4

A full-adder has a Cin = 0. What are the sum (<PRIVATE

"TYPE=PICT;ALT=sigma"> ) and the carry (Cout)

when A = 1 and B = 1?

= 0, Cout = 0 = 0, Cout = 1 = 1 B 2

4

The sequence of states that are implemented by a n-bit Johnson counter is

n+2 (n plus 2)

2n (n multiplied by

2)

2n (2 raise to

power n)

n2 (n raise to

power 2) B 2

4

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock

signal(s) will be required to shift

the value completely out of the register.

1 2 4 8 D 1

4

A GAL is essentially a ________.

Non-

reprogrammable

PAL

PAL that is

programmed only

by the manufacturer Very large PAL

Reprogramm

able PAL D 2

4

In asynchronous transmission when the transmission line is idle, _________

It is set to logic

low

It is set to logic

high

Remains in

previous state

State of

transmission

line is not

used to start

transmission B 1

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4

The alternate solution for a demultiplexer-register combination circuit is

_________ Parallel in / Serial

out shift register

Serial in / Parallel

out shift register

Parallel in /

Parallel out

shift register

Serial in /

Serial Out

shift register B 1

4

The alternate solution for a multiplexer and a register circuit is _________ Parallel in / Serial

out shift register

Serial in / Parallel

out shift register

Parallel in /

Parallel out

shift register

Serial in /

Serial Out

shift register A 2

4 In ________ outputs depend only on the current state. Mealy machine Moore Machine

State Reduction

table

State

Assignment

table B 2

4

A transparent mode means ____________

The changes in the

data at the inputs

of the latch are

seen at the output

The changes in the

data at the inputs of

the latch are not

seen at the output

Propagation

Delay is zero

(Output is

immediately

changed when

clock signal is

applied)

Input Hold

time is zero

(no need to

maintain

input after

clock

transition) A 4

4

__________occurs when the same clock signal arrives at different times at

different clock inputs due to

propagation delay.

Race condition Clock Skew Ripple Effect

None of

given

options B 2

4 ___________ is one of the examples of asynchronous inputs. J-K input S-R input D input

Clear Input

(CLR) D

1

4

Bi-stable devices remain in either of their _________ states unless the inputs

force the device to switch its state

Ten Eight Three Two D

1

4

RCO Stands for _________ Reconfiguration

Counter Output

Reconfiguration

Clock Output

Ripple Counter

Output

Ripple Clock

Output D

2

4

A positive edge-triggered flip-flop changes its state when ________________ Low-to-high

transition of clock

High-to-low

transition of clock

Enable input

(EN) is set

Preset input

(PRE) is set A

2

4

The low to high or high to low transition of the clock is considered to be a(n)

________

State Edge Trigger One-shot B

2

4

In asynchronous digital systems all the circuits change their state with respect

to a common clock

TRUE FALSE B

1

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4

If the S and R inputs of the gated S-R latch are connected together using a

______gate then there is only a

single input to the latch. The input is represented by D instead of S or R (A

gated D-Latch)

AND OR NOT XOR C

1

4 If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop 0 1 Invalid

Input is

invalid B

1

4

3-to-8 decoder can be used to implement Standard SOP and POS Boolean

expressions TRUE FALSE A 2

4 The _______ Encoder is used as a keypad encoder. 2-to-8 encoder 4-to-16 encoder

BCD-to-

Decimal

Decimal-to-

BCD

Priority D 1

4 The simplest and most commonly used Decoders are the ______ Decoders n to 2n (n-1) to 2n (n-1) to (2n-1) n to 2n-1 A 1

4

A Karnaugh map is similar to a truth table because it presents all the possible

values of input variables and the

resulting output of each value.

TRUE False A 2

4

The decimal “17” in BCD will be represented as _________10001(right opt is

not given) 11101 11011 10111 11110 C 1

4

Q2 :=Q1 OR X OR Q3

The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3

Q2:= Q1 & X

& Q3

Q2:= Q1 ! X

! Q3 B 2

4

Above is the circuit diagram of _______ Asynchronous up-

counter

Asynchronous

down-counter

Synchronous up-

counter

Synchronous

down-

counter A 2

4

The high density FLASH memory cell is implemented using ______________ 1 floating-gate

MOS transistor

2 floating-gate

MOS transistors

4 floating-gate

MOS

transistors

6 floating-

gate MOS

transistors A

1

4

A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW.

The nibble 0111 is

waiting to be entered on the serial data-input line. After two clock pulses, the

shift register is storing ________. 1110 111 1000 1001 D

1

4

At T0 the value stored in a 4-bit left shift was “1”. What will be the value of

register after three clock pulses?

2 4 6 8 D

2

4

In asynchronous transmission when the transmission line is idle, _________ It is set to logic

low

It is set to logic

high

Remains in

previous state

State of

transmission

line is not

used to start

transmission B

2

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4

A multiplexer with a register circuit converts ____ Serial data to

parallel

Parallel data to

serial

Serial data to

serial

Parallel data

to parallel B

2

4

________ is used to simplify the circuit that determines the next state.

State diagram Next state table State reduction

State

assignment D

1

4

In ________ outputs depend only on the combination of current state and

inputs Mealy machine Moore Machine

State Reduction

table

State

Assignment

table A

1

4

The _____________ input overrides the ________ input Asynchronous,

synchronous

Synchronous,

asynchronous

Preset input

(PRE), Clear

input (CLR)

Clear input

(CLR),

Preset input

(PRE) A

1

4 ___________ is one of the examples of asynchronous inputs. J-K input S-R input D input

Clear Input

(CLR) 2

4

A positive edge-triggered flip-flop changes its state when ________________ Low-to-high

transition of clock

High-to-low

transition of clock

Enable input

(EN) is set

Preset input

(PRE) is set A 1

4

In asynchronous digital systems all the circuits change their state with respect

to a common clock

TRUE False B 1

4

For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________

0 1 Q(t) Invalid B 2

4

The operation of J-K flip-flop is similar to that of the SR flip-flop except that

the J-K flip-flop ___________

Doesn’t have an

invalid state

Sets to clear when

both J = 0 and K =

0

It does not

show transition

on change in

pulse

It does not

accept

asynchronou

s inputs A 4

4

If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-

flop

0 1 Invalid

Input is

invalid C 2

4

The sequence of states that are implemented by a n-bit Johnson counter is

n+2 2n

2 raise to power

n

n raise to

power 2 B 2

4

________

of a ROM is the time it takes

for the data to appear at the Data

Output of the ROM chip after an

address is applied at the address

input lines Write Time Recycle Time Refresh Time Access Time D

1

4

In _______ the Q output of the last flip-flop of the shift register is connected

to the data input of the first flipflop.

Moore

machine

Meally

machine Johnson counter Ring counter

1

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4

At T0 the value stored in a 4-bit left shift was “1”. What will be the value of

register after three clock pulses?

2 4 6 8 D

2

4

The alternate solution for a multiplexer and a register circuit is Parallel in / Serial

out shift register

Serial in / Parallel

out shift register

Parallel in /

Parallel out

shift register

Serial in /

Serial Out

shift register A

2

4

A multiplexer with a register circuit converts _________

Serial data to

parallel

Parallel data to

serial

Serial data to

serial

Parallel data

to parallel B

2

4 The design and implementation of synchronous counters start from ________ Truth table k-map state table

state

diagram D

1

4

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY

USING A ___________

GATED FLIP-

FLOPS

PULSE

TRIGGERED FLIP-

FLOPS

POSITIVE-

EDGE

TRIGGERED

FLIP-FLOPS

NEGATIVE-

EDGE

TRIGGERE

D FLIP-

FLOPS D

1

4 ___________ is one of the examples of synchronous inputs. J-K input EN input

Preset input

(PRE)

Clear Input

(CLR) A

1

4

A positive edge-triggered flip-flop changes its state when ________________ Low-to-high

transition of clock

High-to-low

transition of clock

Enable input

(EN) is set

Preset input

(PRE) is set A 2

4

Flip flops are also called _____________ Bi-stable

dualvibrators

Bi-stable

transformer

Bi-stable

multivibrators

Bi-stable

singlevibrato

rs C 1

4

The sequence of states that are implemented by a n-bit Johnson counter is

n+2 (n plus 2)

2n (n multiplied by

2)

2n (2 raise to

power n)

n2 (n raise to

power 2) B 1

4 A transparent mode means _____________

The changes in the

data at the inputs

of the latch are

seen at the output

The changes in the

data at the inputs of

the latch are not

seen at the output

Propagation

Delay is zero

(Output is

immediately

changed when

clock signal is

applied)

Input Hold

time is zero

(no need to

maintain

input after

clock

transition) A 2

4

___________ is one of the examples of asynchronous inputs.

J-K input S-R input D input

Clear Input

(CLR) D 2

4

A positive edge-triggered flip-flop changes its state when ________________ Low-to-high

transition of clock

High-to-low

transition of clock

Enable input

(EN) is set

Preset input

(PRE) is set A 2

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4

If the S and R inputs of the gated S-R latch are connected together using a

______gate then there is only a

single input to the latch. The input is represented by D instead of S or R (A

gated D-Latch)

AND OR NOT XOR C 2

4 If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop 0 1 Invalid

Input is

invalid

1

4 Given the state diagram of an up/down counter, we can find ________

The next state of a

given present state

The previous state

of a given present

state

Both the next

and previous

states of a given

state

The state

diagram

shows only

the

inputs/output

s of a given

states A

1

4

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY

USING A ___________

GATED FLIP-

FLOPS

PULSE

TRIGGERED FLIP-

FLOPS

POSITIVE-

EDGE

TRIGGERED

FLIP-FLOPS

NEGATIVE-

EDGE

TRIGGERE

D FLIP-

FLOPS D

2

4

In ________ Q output of the last flip-flop of the shift register is connected to

the data input of the first

flip-flop of the shift register. Moore machine Meally machine

Johnson

counter Ring counter D

2

4

A counter is implemented using three (3) flip-flops, possibly it will have

________ maximum output

status.

3 7 8 15 C

2

4

We have a digital circuit. Different parts of circuit operate at different clock

frequencies (4MHZ, 2MHZ

and 1MHZ), but we have a single clock source having a fix clock frequency

(4MHZ), we can get help by

___________ Using S-R Flop-

Flop D-flipflop J-K flip-flop T-Flip-Flop C

1

4

If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop

0 1 Invalid

Input is

invalid B

1

4 If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop 0 1 Invalid

Input is

invalid C

1

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4

WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE

SET TO LOGIC ZERO

_________ THE FLOP-FLOP

IS TRIGGERED Q=0 AND Q‟=1

Q=1 AND

Q’=0

THE

OUTPUT

OF FLIP-

FLOP

REMAINS

UNCHANG

ED C 2

4

If an S-R latch has a 1 on the S input and a 0 on the R input and then the S

input goes to 0, the latch will

be set reset invalid clear A 2

4

For a positive edge-triggered J-K flip-flop with both J and K HIGH, the

outputs will______ if the clock goes HIGH.

set A 2

4

What is the difference between a D latch and a D flip-flop? The D latch has a

clock input.

The D flip-flop has

an enable input.

used for faster

operation.

The D flip-

flop has a

clock input. D 2

4

A frequency counter ______________

Counts pulse width

Counts no. of clock

pulses in 1 second

Counts high

and low range

of given clock

pulse

None of

given

options B 2

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