pwmc - pulse width modulation controller
TRANSCRIPT
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PWM
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Pulse Width Modulation
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PWM
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PWM Features General Features
- Four Channels, one 16-bit counter per channel,
- One common clock generator, providing 13 different clocks,
One Modulo n counter providing eleven clocks,
Two independent linear dividers working on modulo n counter output,
Channel Programming
- Independent enable/disable commands,
- Independent clock selection,
- Independent period and duty cycle, with double buffering system,
- Programmable selection of the output waveform polarity,
- Programmable center or left aligned output waveform.
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PWM
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View of the external PWM Signals
4 Multiplexed Channel outputs with PIOA lines
Dedicated high current output pad
- Multiplexed to PA0, PA1 and PA2 (respectively for PWM0, PWM1 andPWM2) allow the user to drive external circuitry with load current up to 16
mA (instead of 8 mA for standard pads)
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PWM
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PWM into the AT91SAM7S PMC has to be programmed 1st for PWM to work: Clock Enabling
- Set the PMC_PCER (Peripheral Clock Enable Register), bit 10 (PID10).
PIO Controller has to be programmed for the pins to behave as intended
- Disable targeted PIO line(s) by using PIO_PDR (PIO Disable Register) as shown
below
I/O Line Peripheral A Peripheral B
PA0 PWM0 TIOA0
PA1 PWM1 TIOB0
PA2 PWM2 SCK0
- Select between Peripheral A or B, respectively, in PIO_ASR or PIO_BSR in order
to select the PWM peripheral output channel(s) on the right pad(s).
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PWMC: Clock Generator
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512
/1024
MCK
PWM_MR (Mode Register)16 023 7
DIVA
811
PREADIVB
2427
PREB
1, ,1/3,..,1/255 CLKA1, ,1/3,..,1/255
CLKB
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PWMC: Channel and Interrupt Management At PWMC level, the user can, independently, enable/disable each channel
PWM_ENA (Enable Register)0
The user can use the same control panel at interrupt level plus the dedicated
mask register
3
CHID0CHID1CHID2CHID3
PWM_DIS (Disable Register)
03
CHID0CHID1CHID2CHID3
PWM_SR (Status Register)03
CHID0CHID1CHID2CHID3
PWM_IER (Interrupt Enable Register)03
CHID0CHID1CHID2CHID3
PWM_IDR (Interrupt Disable Register)03
CHID0CHID1CHID2CHID3
PWM_ISR (Interrupt Status Register)03
CHID0CHID1CHID2CHID3
PWM_IMR (Interrupt Mask Register)03
CHID0CHID1CHID2CHID3
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Set up the PWMC in your Application
Enable the PWM Clock For power saving consideration, the PWM s clock is stoppped at
Power Management Controller level by default.
PIO and PWM lines Disable the PIO lines and select the right peripheral between A or B
at multiplexing level.
Set up the Clock Generator Set up the targeted clocks which will be used for the 4 PWM
Channels.
Channel Enabling
These tasks can be performed after the complete channel setting
Interrupt Enabling
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Set up a PWM Channel Per channel:
- Channel Mode Register: Select the running mode of the channel
- Duty Cycle Register: 16-bit value to select the duty cycle of the signal
- Period Register: 16-bit value to select the period of the signal
- Counter Register: counter value- Update Register: Specific register to modify, synchronously, the Duty Cycle Register
or the Period Register.
ClockSelector
Counter
Duty CycleControl
PWM Controller
MCK. down to MCK/1024
PWM Channel 0,1,2 or 3
Comparator
Update Register
PeriodControl
Interrupt
PWMpad
CLKA
CLKB
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First Step: Clock Choice At Channel level, the
Channel Mode Register
allows the user to choose
between the 13 sources from
the clock generator
CLKA
CLKB
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512
/1024
ClockGenerator
03
CPRE
PWM_CMR (Channel Mode Register)
ChannelsCounter
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What is the best clock source ? The PWM duty cycle quantum is the first criterion:
- The user has to know his minimum requested accuracy at duty cycle level. The duty
cycle control is managed through a 16-bit PWM_CDTY register.
015
CDTY
PWM_CDTY (Channel Duty Cycle Register)
The duty cycle quantum depends on the value written in Period Register:- The M value is the required number of event in order to complete one PWM channel period (or
half period in center-aligned mode)
015
CPRD
PWM_CPRD (Channel Period Register)
N value
M value
The PWM Channel period being equal to M source period. N will be from 0 up to M value.
The higher M value, the higher the N value can be, the lower the quantum.
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Example of different PWM accuracy In this first choice, the duty cycle quantum will be 1/75 of a period
ClockGenerator
48 MHz Clock Generator on(/64) =
Channel PeriodRegister = 75
CLKA
CLKB750 kHz 10 kHz
ClockGenerator48 MHz
Clock Generator on(1) =
Channel PeriodRegister = 4800
CLKA
CLKB48 MHz 10 kHz
For the same period, the duty cycle quantum will be 1/4800 of a period.
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How to modify a channel Period or a channel
Duty Cycle value ? Before to enable the PWM Channel at PWM Controller level (PWM_ENA
Register):
The user will be able to write directly into the PWM_CDTYx or PWM_CPRDx of
this channel, respectively, for a duty cycle or period change.
As soon as this PWM channel has been enabled:It is not possible to write into these previous registers. The user will have to use
the Channel Update Register in order to modify one of the previous value.
- The contain of the Update register is put into the PWM_CDTY or PWM_CPRD
according to the value of CPD value in PWM_CMR
PWM_CUPDx
PWM_CDTYx
PWM_CUPDx
03CPRE
PWM_CMRx (Channel Mode Register)
CPD10
0
1
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Note: It is not possible to modify, in the same PWM period for one channel,
the duty cycle AND the period values.
Channel Update Register: PWM_CUPD Why use it:
- In running mode, modifying the duty cycle or the period value can be done only via
PWM_CUPD,
- The duty cycle or the period modification is going to be taken synchronously into
account at the end of the period in progress,
How use it:
- Before to write in PWM_CUPD, the user will have to be sure that the last write has
been take into account. In other case, the previous data will be overlaid by the last
one.
- Use the bit CPD, in PWM_CMR register, in order to select a duty cycle or period
modification,- Write the data into PWM_CUPD register.
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PWM_CUPD Write method
Polling or interrupt methods can be used:
- A flag rises after an end of channel period
(channel 1 for example)
PWM_ISR (Interrupt Status Register)03
CHID0CHID1CHID2CHID3
PWM_ISR (Interrupt Status Register)03
CHID0CHID1CHID2CHID3
Reading PWM_ISR automatically clears
CHIDx flags
00 0 0
000 1
Modifying duty cycle or period value in channel 1 can be possible without
overlaying risk at PWM_CUPD level.
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First Working Mode: Left-alignedPWM_CMR (Channel Mode Register)89
CALG=0
Lelt-Aligned ModeCPOL
0
PWM_CPRD
CPOL= 0
CPOL= 1
PWM_CDTY
When the PWM Counter reach theperiod value, it is cleared.
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Left-aligned Limitation in Multi-Channel use The left-aligned working mode does not allow to avoid overlapped transition in
Multi-channel use
PWM_CPRD0
PWM_CPRD1
PWM_CDTY0
PWM_CDTY1
(PWM_CDTY0 - PWM_CDTY1)
The period ofboth Channels
are equal
In Left-aligned Mode:One event depends on theduty cycle value and the
other depends on theperiod value.
For the same period, there
will be overlapped event
Channel 0Output
Channel 1
Output
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Second Working Mode: Center-alignedPWM_CMR (Channel Mode Register)89
CALG=0
Lelt-Aligned ModeCPOL
0
PWM_CPRD
CPOL= 0
CPOL= 1
PWM_CDTY
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Center-aligned: Non-overlapped event Method The center-aligned working mode allows to avoid overlapped transition in Multi-
channel use
PWM_CPRD0
PWM_CPRD1
PWM_CDTY0
PWM_CDTY1
Channel 0Output
Channel 1Output
(PWM_CDTY0 - PWM_CDTY1)