qpu-speci˙c physical properties: dw 2000q 5€¦ · qpu-speci˙c physical properties: dw_2000q_5...

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Overview

This document describes the physical properties of a particular D-WaveQPU. It includes a summary of its physical properties, an image of theworking graph, and graphed data showing the anneal schedule detailsand ICE e�ects.

QPU-Speci�c Physical Properties: DW_2000Q_5

USER MANUAL

2019-08-07

D-Wave User Manual 09-1210A-DProprietary and Con�dential, D-Wave Systems Inc.

Notice and DisclaimerD-Wave Systems Inc. (D-Wave), its subsidiaries and affiliates, makes commercially reasonable ef-forts to ensure that the information in this document is accurate and up to date, but errors mayoccur. NONE OF D-WAVE SYSTEMS INC., its subsidiaries and affiliates, OR ANY OF ITS RESPEC-TIVE DIRECTORS, EMPLOYEES, AGENTS, OR OTHER REPRESENTATIVES WILL BE LIABLEFOR DAMAGES, CLAIMS, EXPENSES OR OTHER COSTS (INCLUDING WITHOUT LIMITATIONLEGAL FEES) ARISING OUT OF OR IN CONNECTION WITH THE USE OF THIS DOCUMENTOR ANY INFORMATION CONTAINED OR REFERRED TO IN IT. THIS IS A COMPREHENSIVELIMITATION OF LIABILITY THAT APPLIES TO ALL DAMAGES OF ANY KIND, INCLUDING(WITHOUT LIMITATION) COMPENSATORY, DIRECT, INDIRECT, EXEMPLARY, PUNITIVE ANDCONSEQUENTIAL DAMAGES, LOSS OF PROGRAMS OR DATA, INCOME OR PROFIT, LOSS ORDAMAGE TO PROPERTY, AND CLAIMS OF THIRD PARTIES.

D-Wave reserves the right to alter this document and other referenced documents without noticefrom time to time and at its sole discretion. D-Wave reserves its intellectual property rights in andto this document and its proprietary technology, including copyright, trademark rights, industrialdesign rights, and patent rights. D-Wave trademarks used herein include D-Wave®, D-Wave 2XTM,D-Wave 2000QTM, LeapTM, and the D-Wave logos (the D-Wave Marks). Other marks used in thisdocument are the property of their respective owners. D-Wave does not grant any license, assign-ment, or other grant of interest in or to the copyright of this document, the D-Wave Marks, any othermarks used in this document, or any other intellectual property rights used or referred to herein,except as D-Wave may expressly provide in a written agreement. This document may refer to otherdocuments, including documents subject to the rights of third parties. Nothing in this document con-stitutes a grant by D-Wave of any license, assignment, or any other interest in the copyright or otherintellectual property rights of such other documents. Any use of such other documents is subject tothe rights of D-Wave and/or any applicable third parties in those documents.

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Contents

1 About this Document 11.1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 QPU Properties 22.1 System Identi�cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 Summary of Physical Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3 Working Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.4 Annealing Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.5 ICE E�ects on h and J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.6 Qubit Background Susceptibility E�ects . . . . . . . . . . . . . . . . . . . . . . . 82.7 DAC Quantization E�ects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.8 Freezeout Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11



1 About this Document

1.1 Intended AudienceThis document is for users of the D-Wave™ quantum computer system who want to bet-ter understand and leverage the physical implementation of the quantum processing unit(QPU) architecture. It assumes that readers have a background in quantum annealing andare familiar with Ising problem formulations.

1.2 ScopeThis document describes the physical properties of a particular calibrated D-Wave QPU. Itincludes a summary of its physical properties, an image of the working graph, and grapheddata showing the anneal schedule details and the effects of integrated control errors (ICE)on the QPU.

Note: The values provided in this document are the physical properties of a calibratedQPU. They are not product specifications.

1.3 Related DocumentationUse this document in conjunction with the following other documents, available at https://docs.dwavesys.com:

• Technical Description of the D-Wave Quantum Processing Unit—Defines terms, providesin-depth background information on the D-Wave QPU and the quantum annealingprocess, and describes the ICE effects that can affect results.

• Measuring Computation Time on D-Wave Systems—Explains how computational time isallocated to problems submitted to D-Wave systems and identifies the timing-relatedfields available in the D-Wave Solver API.


1

https://docs.dwavesys.com

https://docs.dwavesys.com


2 QPU Properties

2.1 System Identi�cationAll data presented in this document are specific to the following D-Wave QPU.

Solver name DW_2000Q_5Calibration timestamp 19-04-16-08:41

2.2 Summary of Physical PropertiesThis table lists the physical properties for the calibrated QPU.

Table 1: QPU Properties

Parameter ValueModel D-Wave 2000Q1

Chimera Graph Size C16Qubits 2030Couplers 5909Qubit Temperature (mK) 13.5 ± 1.0MAFM (pH) 1.834Average Single Qubit Thermal Width (Ising units) 0.094Single Qubit Freezeout (scaled time) 0.741Problem h Range -2.0 to 2.0Problem J Range -2.0 to 1.0Annealing Time Range (µs) 1.0 to 2000.0Programming Time2 (µs) 7005.10Default Post Programming Thermalization Time (µs) 1000.0Post Programming Thermalization Time Range (µs) 0.0 to 10000.0Readout Time (µs) 275.94Default Post Readout Thermalization Time (µs) 0.0Post Readout Thermalization Time Range (µs) 0.0 to 10000.0Annealing Slope Range3 (µs−1) -1.0 to 1.0Maximum Anneal Schedule Points 12Maximum Slope 1.0Readout Error Rate 0.0

1 Lower-noise system.2 Typical for a random problem with all h and J biases set to +/ − 1.0 run on a full working graph. Actual

problem programming times may vary depending on the nature of the problem.3 Limits ∆s

∆t for each segment of an anneal schedule PWL waveform.

2 D-Wave User Manual 09-1210A-DProprietary and Con�dential, D-Wave Systems Inc.


2.3 Working GraphThe D-Wave QPU is based on a physical lattice of qubits and couplers, known as theChimera graph. The topology comprises sets of connected unit cells, each with four hori-zontal qubits connected to four vertical qubits via couplers. Unit cells are tiled verticallyand horizontally with adjacent qubits connected, creating a lattice of sparsely connectedqubits. The notation CN refers to a Chimera graph consisting of an NxN grid of unit cells.The D-Wave 2000Q QPU supports a C16 Chimera graph: its qubits are logically mappedinto a 16x16 matrix of unit cells of 8 qubits.

Some small number of qubits and couplers in a QPU may not meet the specifications tofunction as desired. These are therefore removed from the programmable fabric that userscan access. The subset of the graph available to users is the working graph. The yield of theworking graph is the percentage of working qubits that are present.

A Note on QPU Yield

The yield of a working graph is typically less than the total number of qubits and cou-plers (devices) that are fabricated and physically present in the QPU. Manufacturingvariations and the need to prepare the QPU to operate at cryogenic temperatures ina low–magnetic field environment limits the yield. These variations are minimizedthrough an extensive calibration process that attempts to bring all of these analog de-vices into a consistent parametric regime.

Each D-Wave 2000Q QPU is fabricated with 2048 qubits and 6016 couplers. Of this total,the number of devices, and the specific set of devices, that can be made available in theworking graph changes with each system cooldown and calibration cycle. Calibratedcommercial systems typically have more than 97% of fabricated qubits available in theirworking graphs. Yields significantly higher than this are not guaranteed.

Note: The ratio of qubits available to the total fabricated is specific to a QPU model.The ratios published for this D-Wave 2000Q system may not apply to future productgenerations.

Figure 1 shows the working graph for this QPU.


3


Figure 1: Working graph.



2.4 Annealing ScheduleEqn. 2.1 shows the quantum Hamiltonian that governs the annealing process, where σ̂

(i)x,z

are Pauli matrices operating on a qubit qi and nonzero values of hi and Ji,j are limited tothose available in the graph.

Hising = −A(s)2

(∑

iσ̂(i)x

)+

B(s)2

(∑

ihiσ̂

(i)z + ∑

i>jJi,jσ̂

(i)z σ̂

(j)z

)(1)

The annealing schedule for this QPU is shown in Figure 2.

0 0.5 1

s

0

2

4

6

8

10

12

En

erg

y (

GH

z)

Figure 2: Annealing schedule for the QPU, showing energy changes as a function of scaled time.


5


2.5 ICE E�ects on h and JICE on h and J affects the user-specified problem such that the QPU solves a slightly mod-ified version of that problem, modeled as follows:

Eδising(s) = ∑

i(hi + δhi(s)) si + ∑

i>j

(Ji,j + δJi,j(s)

)sisj, (2)

where s is the scaled time t/t f , and si is the spin state of qubit i. The δh and δJ values areGaussian distributed with mean µ and standard deviation σ that vary with s during theanneal.

Figure 3 to Figure 6 show the effects of ICE on the user-specified values of h and J, atdifferent points in the anneal, for this QPU.

Figure 3: Systematic (mean) of δh distribution. This shows the worst case systematic error in h.

Figure 4: Standard deviation of δh distribution.



Figure 5: Systematic (mean) of δJ distribution. This shows the worst case systematic error in J.

Figure 6: Standard deviation of δJ distribution.


7


2.6 Qubit Background Susceptibility E�ectsQubit background susceptibility, χ, varies during the anneal; see Figure 7.

Figure 7: Qubit background susceptibility, χ, as a function of s.



2.7 DAC Quantization E�ectsThe on-QPU digital-analog converters (DACs) that provide the user-specified h and J val-ues have a finite quantization step size. That step size depends on the value of the h and Japplied because the response to the DAC output is nonlinear.

Figure 8 and Figure 9 show the effects of the DAC quantization step for the DACs control-ling the h and J values, respectively, for this system.

Figure 8: Typical quantization on the h DAC control.


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Figure 9: Typical quantization on the J DAC control.



2.8 Freezeout PointsFigure 10 shows the freezeout point, s, for logical qubits of different sizes, numbered 1 to 6.The freezeout point for a logical qubit is the last point in the anneal where any meaningfulspin-flip dynamics occur. The freezeout point of networks of logical qubits depends onfactors such as:

• Number of qubits in the network

• Coupling strength between the qubits

• Overall time scale of the anneal, t f

Figure 10: Freezeout point, s, for logical qubits of different sizes (dashed lines). Data are from 20-microsecond anneals.

The persistent current, Ip, of the qubits at the freezeout point also depends on the numberof qubits in the logical qubit network and on the annealing time. Lower annealing timeand larger clusters move the freezeout point earlier in the anneal, where Ip is lower; seeFigure 11.


11


Figure 11: Ip at freezeout as a function of logical qubit size and annealing time.


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