quantum cellular automata based efficient bcd adder structure

7/27/2019 Quantum Cellular Automata Based Efficient BCD Adder Structure

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Communications in Information Science and Management Engineering CISME

CISME Vol.2 No.2 2012 PP.11-14 www.jcisme.orgC 2011-2012 World Academic Publishing

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Quantum Cellular Automata Based Efficient BCD

Adder StructureN. A. Shah

1, F. A. Khanday

1*and Z. A. Bangi

1

1Department of Electronics and Instrumentation Technology

University of Kashmir, Srinagar-190006, India* [email protected]

Abstract-In this paper, design of quantum-dot cellular automata(QCA) based Binary Coded Decimal (BCD) adder is presented.The design is based on pipelined structure with noise problemscircumvented by careful clocking organization. The designoccupies smaller area and enjoys superior performance inrespect of noise, circuit stability and power consumptioncompared to the previously reported design. The QCA circuit issimulated and its operation is analyzed using QCA Designerbistable vector simulation.

Keywords-Nanotechnology; Nanoelectronics; Quantum-dotCellular Automata; Circuit Design; Circuit Simulation; Arithmetic

Computing

I. INTRODUCTIONQuantum Cellular Automata (QCA) originally proposed

by Lent et al. [1, 2] are a nanoelectronic digital logicarchitectures in which information is stored as configurationsof electron pairs in quantum-dot arrays. QCA use arrays ofcoupled quantum dots [3] to build Boolean logic functionsand to perform useful computations. QCA take advantage ofquantum-mechanical effects to significantly reduce the size ofdigital circuits and operate at high speeds at very low powerlevels. Conventional digital technologies use ranges ofvoltage or current to represent binary values. In contrast,QCA use the position of electrons in quantum dots torepresent binary values 0 and 1. QCAs primaryadvantages are the exceptionally high logic integrationderived from the small size of dots, the simplicity and thenotably low power-delay product [4].

The basic QCA cell consists of four quantum dots in asquare array coupled by tunnel barriers. The physicalmechanism for interaction between dots is the Coulombinteraction and the quantum-mechanical tunneling. Electronsare able to tunnel between the dots, but they cannot leave thecell. If two mobile electrons are placed in the cell, in theground state and in the absence of external electrostaticinfluence, Coulomb repulsion will force the electrons to dotson the opposite corners [5-7].

It is possible to implement all combinational andsequential logic functions by properly arranging cells so thatthe polarization of one cell sets the polarization of a nearbycell [8]. According to previous studies, several logic gates andcomputing devices [9] are implemented with QCA. Basicimplementations that have been proposed are the binary wire[2], the majority gate, AND gate [10], OR gate [10], NOTgate [10], XOR gate [10], bit-serial adder [11, 12], full adder[13, 10, 11, 14, 15], multiplier [16], multiplexer [13, 17], flip-flop [1820], serial memory [21, 22], parallel memory [23],Arithmetic Logic Unit [13, 24], microprocessor [24],Programmable Logic Array (PLA) [25], etc.

A problem encountered in binary arithmetic is that quitecomplex digital circuit is required to accomplish direct

conversion of binary to decimal (for numbers having manydigits). Therefore, often when a number is being held in adigital circuit, before it is to be displayed in decimal form,binary coded decimal (BCD) rather than straight binary codeis used. BCD encodes each decimal digit with its binaryequivalent using four bit strings. So, decimal digits are simplyrepresented in four bits by their direct binary values. Adisadvantage of BCD is its inefficiency of using only first 10of the possible 16 codes that four bits can produce.Nevertheless, the advantages usually outweigh this

disadvantage and so it is regularly used.The next immediate problem that is being experienced in

BCD addition is the use of only first 10 codes, contrary tostraight binary addition where all the 16 states are used. Theproblem in the conventional digital design is overcome byadding logic circuitry and thus giving it a special name ofBCD adder.

The QCA based BCD adder design presented in this paperoccupies less space in comparison with reported in [26]. Theoperational stability of the design has been given particularimportance by restricting the minimum wire to wire distanceto 2 cells in almost entire area of the design and the maximumwire length in a clocking zone to 13 cells. Both these

measures reduce the probability for a kink to occur.

II.QCA BCD ADDEROur main objective is to develop an efficient design of

QCA based BCD adder. A high-level block diagram of theBCD adder design is shown in Fig. 1, whereAi andBi (i = 0-3)are the BCD inputs, and Si(i = 0-3) and Cout arerespectivelyBCD sum and final carry. The design includes two ANDblocks, six full binary adder blocks, and one each of an ORBlock and an XORblock.

Fig. 1 High-level Block Diagram of the BCD Adder Design


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Fig. 2 shows the QCA implementation of the AND, OR,XOR and full binary adderblocks. The XOR and full binaryadderblocks require Inverter gate given in Fig. 2(e). BothAND and OR blocks are usually based on a three-inputmajority voter (MV) gate, settling into minimum energybetween the input and output cells. The gate performs thetwo-input AND-operation when its third input is set at logicalzero or the two-input OR-operation when its third input is

fixed at logical one. The XOR gate basically consists of twoAND gate and a single OR gate with one input of the each

AND gate is inverted ( BABAXOR ). The full binaryadder block given in Fig. 2(d) is based on Fig. 3 expressed interms of MVs and inverters.

The final QCA implementation layout of the proposedBCD adder is depicted in Figure 4. It can be easily seen thatthe clocking phases are traversed in the proper order (0, 1, 2,3, 0, 1 . . .) so that the required clock phases are alwaysadjacent to one another to allow correct signal propagation.The signal propagates diagonally with a line profile from thetop left block to the bottom right block. Also using pipeliningstructure, the proper signals arrive simultaneously at theinputs of the blocks.

The circuit was designed and simulated usingQCADesigner tool. In the environment of the previouslymentioned tool, the overall QCA cell dimensions are definedto be 1818nm; the dot diameter is defined to be 5 nm and theinter-cell distance to be 2 nm. According to the QCADesignertool, the design consists of 1903 cells covering an area of29381870nm2, that is, approximately 5.5m2 and the ratio ofthe area covered by QCA cells to the overall area of the layoutis (0.61m

2/5.5m

2) 1/9. The simulation results of the design,

acquired by the QCADesigner bistable vector simulationengine, are given in Fig. 5.

There are some design concerns taken into account toincrease the robustness of the QCA circuit [27]. The length ofthe wire within a given clocking zone is kept minimum toincrease the probability that a QCA cell will switchsuccessfully which decreases in proportion to the distance ofthis particular cell from a clamped (frozen) input at thebeginning of the wire. Additionally, short wire lengths resultin circuit operation with higher clock rates. Thus, themaximum wire length in the proposed design equals 13 cells.Further, minimum wire length decreases the probability for akink to occur (a QCA cell to align differently from itsexpected polarization) at higher temperatures. The area of theclocking zones is kept minimum to increase uniformity andconsequently manufacturability. Furthermore, by keeping the

area to a minimum, wire lengths are also kept to a minimumand consequently the circuit can operate at highertemperatures with no kink occurrence.

Another problem associated with complex QCA designs isthat usually large amount of white space wasted area is leftbetween cells [4, 30]. In the presented design the use ofclocking zones with many cells is avoided and consequentlythe QCA cells are uniformly distributed into the clockingzones. The clocking zones are also designed in such a waythat the uncovered areas can be as small as possible. Finally,to overcome this problem, the total area covered by QCAcells was minimized by keeping the distance between binarywires as close as possible according to QCA design rules

proposed by Kim et al. [28, 29]. As a result, the proposedarchitecture does not leave a large amount of unused area.

(a) (b)

(c)

(d)

(e)

Fig. 2 Elementary Block Implementation for the BCD Adder Design

(a) AND Block (b) OR Block (c) XOR Block (d) Binary Full Adder and (e)

Inverter.

Fig. 3 Binary Full Adder Circuit Diagram by MV and Inverter Gates


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A comparison of proposed design with previouslyreported [26] is given in Table I. A study of this table showsthat the new design uses significantly lesser area. Besides, ithas a delay of 9 clock phases compared with 11 clock phasesdelay of the previous design. Further, the design hassignificantly smaller maximum wire length which leads to ahigher maximum temperature for kink-free operation.

TABLE I

COMPARISON OF THE PROPOSED DESIGN IN THIS PAPER WITH [26]

CharacteristicsReported design

[26]

Proposed

design

No. of cells ~ 3193 1903

Estimated area by

QCADesigner tool (m2)9.00 5.50

Computational time 11 9

Maximum wire length in azone (cells)

More than 30 13

III.CONCLUSION

We presented the design and simulation of a QCA BCDadder circuit and analyzed its operation. The design consistsof less number of cells than the earlier design. The designutilizes lesser number of clock phases and has significantlysmaller maximum wire length which leads to kink-freeoperation at higher operating temperature. Further, to increasethe robustness of the QCA design, various design concernshave been addressed.

Fig. 4 QCA Implementation of the BCD Adder

Fig. 5 Simulation Results of the BCD Adder

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quantum cellular automata based efficient bcd adder structure

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