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Altera Quartus II Tutorial CSE140L – WI06 TA: Jianhua Liu CSE Dept. UCSD

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Quartus i i Tutorial

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  • Altera Quartus II Tutorial

    CSE140L WI06TA: Jianhua Liu

    CSE Dept. UCSD

  • Altera Quartus II

    z The Quartus II development software provides a complete design environmentfor FPGA designs.

    z Design entry using schematics, block diagrams, VHDL, and Verilog HDL .

    z Design analysis and synthesis, fitting, assembling, timing analysis, simulation.

  • Altera Quartus II

    Design flow Design entry

    Analysis andsynthesis

    Fitting

    Assembling

    Timing analysis

    Simulation

    Quartus II HDL editor Block diagram,schematic editor

    Compiler tool

    Compilation report

    Timing closure floorplan

    Simulator tool

    Waveform editor

  • Tutorial Outline

    z Open Quartus II and pick a device.z Build a full adder. (Block/Schematic)z Add componentsz Add portsz Add connections (single wire connection)

    z Build a 4-bit adder.z Create a block for full adderz Use conduit and port mapping

  • Tutorial Outline

    z Compile the 4-bit adder.z Open compiler toolz Read compilation reportz Open timing closure floorplan

    z Simulate the 4-bit adder.z Open simulator toolz Edit simulation waveformz Observe simulation results

    z Schematic for 16-bit Multiplexerz Use connections by name

  • Start Quartus II

    z Open Quartus II, click on the icon

    Work spaceProject Navigator

    Message window

  • Create a new project

    z Menu File New Project Wizard

  • Build a full adder

    z Menu File Newz Create a Block Diagram/Schematic Filez Menu File Save As: fadder.bdf

    LibraryNew BlockSingle WireBusConduit

  • Build a full adder

    z Click on libraryz Find xor under primitives logic

  • Build a full adder

    z Place two xor, two and2 and one or2.

  • Build a full adder

    z Find input and output under primitives pin, and place three input and two output

    z Double click on each pin, to change pin name.

  • Build a full adder

    z Connect them by single wire

    z Save the file

  • Questions

  • Build a 4-bit adder

    z Menu File Newz Create a Block Diagram/Schematic Filez Menu File Save As: adder4.bdfz Click on new block , and draw a block.z Double click on the block name, change it to fadder

  • Build a 4-bit adder

    z Right click on the block, and select Block Properties in the pop-up menu.

    z In the tag I/Os, add the following ports:

  • Build a 4-bit adder

    z Click on OK to dismiss the properties window.

    z Right click on the block, and select AutoFit in the pop-up menu.

    z Select the block, make four copies by copy/paste.

    z Add 3 inputs and 2 outputs.

  • Build a 4-bit adder

    z Use conduit tool to connect each fadder to inputs and outputs. Conduit can stop at any point on a block border.

  • Build a 4-bit adder

    z The primary input Cin is automatically connected to the Cin port of inst by the same same.

    z Right click on the conduit, select properties, the connection can be found in the tab Signals.

  • Build a 4-bit adder

    z For A[3..0], B[3..0] and S[3..0], port mapping should be manually defined. Edit the signals property for A[3..0] like this:

  • Build a 4-bit adder

    z After port mapping for A[3..0], B[3..0] and S[3..0], you will see this:

  • Build a 4-bit adder

    z Place single wires for carry signals.

  • Build a 4-bit adder

    z Double click on a port mapper , and define port mapping in the tab Mappings. For example, map Coutto signal C1.

  • Build a 4-bit adder

    z Heres the final diagram.

  • Questions

  • Compile the design

    z Menu Tools Compiler Tool

    z Click on Start. The design will be compiled automatically.

  • Compile the design

    z Click on Report button after compilation.

  • Compile the design

    z Worst delay can be found in Timing Analyzer report

  • Compile the design

    z Select the worst delay, right click on it, and select locate in the pop-up menu Locate in Timing Closure Floorplan. You can see the design implementation in the FPGA device.

  • Simulate the design

    z Menu Tools Simulator Tool

    z Type adder4 for Simulation input

  • Simulate the design

    z Click on Open button , and save the file as adder4.vwf

    Signals Waveforms

  • Simulate the design

    z Double click on signals area, and click the button Node Finder

    z List all the pins and select the primary inputs and outputs, then click OK.

  • Simulate the design

    z To change the value of each input, right click on the input and select value in the pop-up menu.

  • Simulate the design

    z Set value to each inputs and save the file.

  • Simulate the design

    z Go back to the simulator tool, and click on the button Start . adder4.vwf will be updated after the simulation.

  • Simulate the design

    z The correctness of the design is verified, and the worst delay can be identified.

  • Questions

  • Schematic for 16-bit Multiplexer

    z The schematic diagram of a 4-bit Multiplexer. Note that the wires connected by name.

  • Schematic for 16-bit Multiplexer

    z To name a wire/bus, right click the wire/bus, select properties in the pop-up menu, and then fill in the name.

  • Schematic for 16-bit Multiplexer

    z The schematic diagram of a 16-bit Multiplexer.

  • Questions


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