question bank chapter 5 introduction to memory
TRANSCRIPT
Digital Technique Mrs. Sunita M Dol, CSE Dept
Walchand Institute of Technology, Solapur Page 1
Chapter 5: Introduction to Memory
1. A computer can be divided which of the following categories or subsystem:
a. the central processing unit (CPU),
b. the main memory and
c. the input/output subsystem.
d. All of above
2. CPU has
a. An arithmetic logic unit (ALU),
b. A control unit and a set of registers,
c. Fast storage locations.
d. All of above
3. The arithmetic logic unit (ALU) performs
a. Logic
b. Shift
c. Arithmetic
d. All of above
4. Which memory type is volatile
a. RAM
b. ROM
c. EPROM
d. None of above
5. Which memory type is volatile
a. RAM
b. ROM
c. Both a and b
d. None of above
Digital Technique Mrs. Sunita M Dol, CSE Dept
Walchand Institute of Technology, Solapur Page 2
6. Types of RAM is/are
a. Dynamic
b. Static
c. Both a and b
d. None of above
7. Types of ROM is/are
a. Programmable read-only memory (PROM).
b. Erasable programmable read-only memory (EPROM).
c. Electrically erasable programmable read-only memory (EEPROM).
d. All of above
8. The CPU and memory is/are normally connected by which of the following
bus
a. Data bus
b. Address bus
c. Control bus
d. all of above
9. _________ determines the location in memory that the processor will read
data from or write data to
a. Data bus
b. Address bus
c. Control bus
d. all of above
10. _________ contains the contents that have been read from the memory
location or are to be written into the memory location
a. Data bus
b. Address bus
c. Control bus
d. all of above
Digital Technique Mrs. Sunita M Dol, CSE Dept
Walchand Institute of Technology, Solapur Page 3
11. _________ manages the information flow between components indicating
whether the operation is a read or a write and ensuring that the operation
happens at the right time
a. Data bus
b. Address bus
c. Control bus
d. all of above
12. The set of lines used for data inputs as well as data output is called
a. Unidirectional
b. Bidirectional
c. Multidirectional
d. None of above
13. To write the word into the selected memory location requires logic ___
voltage to be applied to CS and Write(WR) inputs and logic ___ voltage to
Read (RD) input
a. 1, 0
b. 0, 0
c. 0, 1
d. 1, 1
14. For writing a word into a particular memory location, select the proper
sequence of operation to be performed:
i. The chip select signal is applied to the CS terminal.
ii. The word to be stored is applied to the data-input terminals.
iii. The address of the desired memory location is applied to the
address-input terminals.
iv. A write command signal is applied to the write-control input
terminal with RD = 0.
a. ii, iii, iv, i
b. i, ii, iii, iv
c. ii, iii, i, iv
d. iv, i, ii, iii
Digital Technique Mrs. Sunita M Dol, CSE Dept
Walchand Institute of Technology, Solapur Page 4
15. ________is the minimum amount of time for which the valid address must
be present for writing a word in the memory
a. Write cycle time
b. Write pulse time
c. Write release time
d. Data set up time
16. ________is the minimum length of the write pulse
a. Write cycle time
b. Write pulse time
c. Write release time
d. Data set up time
17. ________is the minimum amount of time for which the address must be
valid after the write pulse ends
a. Write cycle time
b. Write pulse time
c. Write release time
d. Data set up time
18. ________is the minimum amount of time for which the data must be valid
before the write pulse ends
a. Write cycle time
b. Write pulse time
c. Write release time
d. Data set up time
19. ________is the minimum amount of time for which the data must be valid
after the write pulse ends.
a. Write cycle time
b. Data hold tome
c. Write release time
d. Data set up time
Digital Technique Mrs. Sunita M Dol, CSE Dept
Walchand Institute of Technology, Solapur Page 5
20. For reading a data word to be stored at a particular address, select the
sequence of operation to be performed:
i. The chip select signal is applied to the CS terminal.
ii. The address of the desired memory location is applied to the
address-input terminals.
iii. A read command signal is applied to the read-input terminal.
a. ii, iii, i
b. iii, ii, i
c. i, ii, iii
d. none of above
21. __________is the minimum amount of time for which the valid address
must be present for reading a word from memory.
a. Read cycle time
b. Access time
c. Read to output valid time
d. Read to output active time
22. __________is the maximum time from the start of the valid address of the
read cycle to the time when the valid data is available at the data outputs.
a. Read cycle time
b. Access time
c. Read to output valid time
d. Read to output active time
23. __________is the maximum time delay between the beginning of the read
pulse and the availability of valid data at the data output.
a. Read cycle time
b. Access time
c. Read to output valid time
d. Read to output active time
Digital Technique Mrs. Sunita M Dol, CSE Dept
Walchand Institute of Technology, Solapur Page 6
24. __________is the minimum time delay between the beginning of the read
pulse and the output buffers coming to active state.
a. Read cycle time
b. Access time
c. Read to output valid time
d. Read to output active time
25. ________is the maximum time delay between the beginning of the chip
select pulse and availability of valid data at the outputs
a. Chip select to output valid time
b. Chip select to output active time
c. Output tri-state from read
d. Data hold time
26. ________is the minimum time delay between the beginning of the chip
select pulse and the output buffers coming to active state.
a. Chip select to output valid time
b. Chip select to output active time
c. Output tri-state from read
d. Data hold time
27. ________is the maximum time delay between the end of the read pulse and
the output buffers going to high impedance state.
a. Chip select to output valid time
b. Chip select to output active time
c. Output tri-state from read
d. Data hold time
28. ________is the minimum time for which the valid data is available at the
data outputs after the address ends.
a. Chip select to output valid time
b. Chip select to output active time
c. Output tri-state from read
d. Data hold time
Digital Technique Mrs. Sunita M Dol, CSE Dept
Walchand Institute of Technology, Solapur Page 7
29. To obtain a 16x8 memory using 16x4 memory ICs, how many chips is/are
required
a. 1
b. 2
c. 3
d. 4
30. To obtain a 2048x8 memory using 256x8 memory ICs, how many chips are
required
a. 7
b. 8
c. 9
d. 5