R. Ludwig and G. Bogdanov“RF Circuit Design: Theory and Applications”

2nd edition

Figures for Chapter 6

Figure 6-1 Lattice structure and energy levels of silicon. (a) schematic planar crystal arrangement with thermal breakup of one valent bond resulting in a hole and a moving electron for T > 0 K. (b) equivalent energy band level representation whereby a hole is created in the valence band WV and an electron is produced in the conduction band WC. The energy gap between both bands is indicated by Wg.

Si Si

Si Si

Si Si

Free electron

Hole

Hole Valence band

Conduction band

Forbidden Band

or BandgapWg

WC

WV

(a) Planar representation of covalent bonds (b) Energy band levels

Ele

ctro

n e

ner

gy

Table 6-1 Effective concentrations and effective mass values at T = 300 K

Semiconductor

Silicon (Si) 1.08 0.56 2.8 × 1019 1.04 × 1019 1.45 × 1010

Germanium (Ge) 0.55 0.37 1.04 × 1019 6.0 × 1018 2.4 × 1013

Gallium Arsenide (GaAs) 0.067 0.48 4.7 × 1017 7.0 × 1018 1.79 × 106

mn* /m0 mp

* /m0 NC, cm3–

NV, cm3–

ni, cm3–

Figure 6-2 Conductivity of Si, Ge, GaAs in the range from –50°C to 250°C.

–50 0 50 100 150 200 250

Temperature, ºC

Co

nd

uct

ivit

y

, Ω

–1cm

–1

Ge

Si

GaAs

102

100

10–2

10–4

10–6

10–8

10–10

10–12

10–14

Figure 6-3 Lattice structure and energy band model for (a) intrinsic, (b) n-type, and (c) p-type semiconductors at no thermal energy. WD and WA are donor and acceptor energy levels.

Valence band

(a) Intrinsic (b) n-type (c) p-type

Conduction band

Valence band

Conduction band

Valence band

Conduction band

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

P

Si

Si

Si

Si

Si

Si

Si

Si

B

Si

Si

Si

Si

Si

Si

Si

WC

WF

WF

WFWV

WC

WV

WC

WV

WD

WA

Figure 6-4 Current flows in the pn-junction.

p-type n-type

xx = 0

Electric field

Hole

diffusion

current

Space

charge

Space

charge

Electron

diffusion

current

IF

Figure 6-5 The pn-junction with abrupt charge carrier transition in the ab-sence of an externally applied voltage.

(a) pn-junction with space charge extent

(b) Acceptor and donor concentrations

(c) Polarity of charge density distribution

(d) Electric field distribution

p-type n-type

Space

charge

Space

charge

xx = 0–dp dn

x

n, p

pp = NA (majority carrier)nn = ND (majority carrier)

np < < pp

–dp dn

pn < < nn

x

(x)

dpdn

qND–qNA

x

E

–dp dn

E0 = –qNAdp/( r 0)

Figure 6-5 The pn-junction with abrupt charge carrier transition in the ab-sence of an externally applied voltage. (Continued)

(e) Barrier voltage distribution

x

V(x)

–dp dn

Vdiff

Figure 6-6 External voltage applied to the pn-junction in reverse and forward directions.

Voltage distribution in the pn-junction

(a) Reverse biasing (VA < 0) (b) Forward biasing (VA > 0)

E

x

E

x

p n p n

Space charge distribution in the pn-junction

Electric field distribution in the pn-junction

x

V

x

V

–dp dn –dp dn

Vdiff

VA

VA

Figure 6-7 The pn-junction capacitance as a function of applied voltage.

Applied voltage VA, V

7

Jun

ctio

n c

apac

itan

ce C

, p

F

Vdiff

0–5 –4 –3 –2 –1 0

1

2

3

4

5

6

1

Figure 6-8 Current-voltage behavior of pn-junction based on Shockley equation.

–1

1

2

3

4

5

6

7

0.5 1.0 1.5 2.0–0.5–1.0–1.5–2.0

p n

VA

VA/VT

I / I0

I

Figure 6-9 Metal electrode in contact with p-semiconductor.

(a) Energy band model (b) Voltage-current characteristic

Metal p-semiconductor

WC

WFWF

WV

I

VA

Figure 6-10 Energy band diagram of Schottky contact, (a) before and (b) after contact.

(a) (b)

Metal n-semiconductor

Free electron energy level

x

WM

WF

WS

WC

WF

WV

q

Metal n-semiconductor

x

WC

qVd

qVCWF

WV

WF

Wb

ds

Table 6-2 Work function potentials of some metals

Material Work Function Potential,

Silver (Ag) 4.26 V

Aluminum (Al) 4.28 V

Gold (Au) 5.10 V

Chromium (Cr) 4.50 V

Molybdenum (Mo) 4.60 V

Nickel (Ni) 5.15 V

Palladium (Pd) 5.12 V

Platinum (Pt) 5.65 V

Titanium (Ti) 4.33 V

VM

Figure 6-11 Cross-sectional view of Si Schottky diode.

n-type epitaxial layer

n+-type substrate

SiO2 SiO2

Metal contact

Metal contact

Metal contact

Metal contact

Depletion

region

Cg

RJ

Repi

Rsub

RS

CJ

n

n+

Figure 6-12 Circuit model of typical Schottky diode under forward bias.

RSLS

RJ

CJ

Cg

Figure 6-13 Schottky diode with additional isolation ring suitable for very highfrequency applications.

Metal contact

Metal contact

p-type

ringn-type epitaxial layer

n+-type substrate

SiO2 SiO2

Figure 6-14 PIN diode construction.

n+-type substraten+

p+p+

SiO2

(a) Simplified structure of a PIN diode (b) Fabrication in mesa processing technology

SiO2

I = nI = n

Figure 6-15 PIN diode in series connection.

(b) Reverse bias (isolation)

(a) Forward bias

ZG = Z0

ZG = Z0

ZL = Z0

ZL = Z0

RJ (VQ)VG

VG

CJ

Figure 6-16 Attenuator circuit with biased PIN diode in series and shunt configurations.

(b) Shunt connection of PIN diode

(a) Series connection of PIN diode

RFC

RFC

PIN Diode

CB CB

DCbias

RFin RFout

RFC

RFC

PIN Diode

CB CB

CB

DCbias

RFin RFout

Figure 6-17 Transducer loss of series connected PIN diode under forward-bias con-dition. The diode behaves as a resistor.

Tra

nsd

uce

r lo

ss,

dB

Junction resistance RJ, Ω

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 2 4 6 8 10 12 14 16 18 20

ZG = Z0

ZL = Z0RJ (VQ)VG

Figure 6-18 Transducer loss of series connected PIN diode under reverse-bias con-dition. The diode behaves as a capacitor.

Tra

nsd

uce

r lo

ss,

dB

0

10

20

30

40

50

60

70

10 MHz 100 MHz 1 GHz 10 GHz 100 GHz

CJ = 0.1 pF

2.5 pF

0.3 pF0.6 pF1.3 pF

Frequency

ZG = Z0

ZL = Z0VGCJ

Figure 6-19 Simplified electric circuit model and capacitance behavior of varactor diode.

Cap

acit

ance

CV,

pF

Biasing voltage VQ, V

0–0.2–0.4–0.6–0.8–1.0–1.2–1.4–1.6–2.0

0.20

0.18

0.16

0.14

0.12

0.10

0.08–1.8

CV (VQ)RS

CV0 = 0.2 pF, Vdiff = 0.5 V

Figure 6-20 Pulse generation with a varactor diode.

Varactor

t

t

Vout

Vout

IV

IV

tV

VA

VA

VA, IV

R

Figure 6-21 IMPATT diode behavior.

(a) Layer structure and electric field profile (b) Impact ionization

+

+

+

Hole

Electron

Impact

Ip+

WE

x

p+n+

Figure 6-22 Applied voltage, ionization current, and total current of an IMPATT diode.

2π 3π 4ππ

2π 3π 4ππ

2π 3π 4ππ

I

VA

I ion

T

T

T

Figure 6-23 Electric circuit representation for the IMPATT diode.

RL CL

C ion

L ion

Figure 6-24 Tunnel diode and its band energy representation.

d+

WFn

WCn

WVp

WCp

WFp

WVn

Wg

Wg

Vdiff

p+

n+

Figure 6-25 Interdigitated structure of high-frequency BJT.

(a) Cross-sectional view of a multifinger bipolar junction transistor

(b) Top view of a multifinger bipolar junction transistor

Base bonding pad

Emitter bonding pad

p+ base contacts

p base well

n+ emitter contactsMetallization

B E B E B E B E B E B

p-base

n-type collector

C

p+ p+ p+ p+ p+ p+

n+ n+ n+ n+ n+

Figure 6-26 Cross-sectional view of a GaAs heterojunction bipolar transistor involving a GaAlAs-GaAs interface.

C B B

E n+

p+

n+ n

n-GaAlAsDielectric

p-substrate

Figure 6-27 npn transistor: (a) structure with electrical charge flow under forward active mode of operation, (b) transistor symbol with voltage and current directions, and (c) diode model.

B

E

C

n-type

collector

p-type

base

n-type

emitter

elec

tro

n

coll

ecti

on

elec

tro

n

dif

fusi

on

elec

tro

n

inje

ctio

n

Electron

recombination

Hole recombination

Hole

injection

C

B

E

IB

IC

IE

VCB

VBE

VCE

C

E

B

(a) (b) (c)

++

––

+

–

Figure 6-28 Biasing and input, output characteristics of an npn BJT.

(a) Biasing circuit for npn BJT in common-emitter configuration

(b) Input characteristic of transistor

Cutoff

Sat

ura

tio

n

(c) Output characteristic of transistor

IB4

IB3

IB2

IB1

IC

RC

RB IB

+ VBEVBB

+VCEVCC

Load line –1/RB

IB

VBB/RB

Q point

VBEVBB

IBQ

ICQ

V BEQ

V CEQ

Load line –1/RC

Incr

easi

ng

bas

e cu

rren

t

Q point

VCEVCC

IC

VCC/RC

–

+

+–

Table 6-3 BJT parameter nomenclature

Parameter description Emitter (n-type) Base (p-type)Collector (n-type)

Doping level

Minority carrier concentration in thermal equilibrium

Majority carrier concentration in thermal equilibrium

Spatial extent

NDE

NAB

NDC

pn0

Eni

2ND

E⁄= np0

Bni

2NA

B⁄= pn0

Cni

2ND

C⁄=

nn0

Epp0

Bnn0

C

dE dB dC

Figure 6-29 Minority carrier concentrations in forward active BJT.

B

E C

Forward-biased

junction

Reverse-biased

junction

n p n

x

–IE IC

pn (0)E

np (0)B

pn0E np0

B pn ≈ 0C

x = 0x = –dE x = dB x = dB + dC

Figure 6-30 Reverse active mode of BJT.

BForward-biased

junction

Reverse-biased

junction

npn

x

E

–IE

C

IC

pn0 Cnp0

B

x = 0x = –dE x = dB x = dB + dC

pn ≈ 0E

np (dB)B pn (dB)

C

Figure 6-31 Transition frequency as a function of collector current for the 17 GHz npn wideband transistor BFG403W (courtesy of NXP).

20

16

12

8

4

01 10

Tra

nsi

tio

n f

req

uen

cy f

T,

GH

z

Collector current IC, mA

Figure 6-32 Typical current gain as a function of collector current for various junction temperatures at a fixed

140

120

100

80

60

40

20

00 1 2 3 4 5 6

Cu

rren

t g

ain

IC

/IB

Collector current IC, mA

Tj = 100°C

Tj = 150°C

Tj = 50°C

Tj = 0°C

Tj = –50°C

βFVCE.

Figure 6-33 Typical base current as a function of base-emitter voltage for various junction temperatures at a fixed VCE.

10

8

6

4

2

00.5 1.0 1.5 2.0

Bas

e cu

rren

t I B

, m

A

Base-emitter voltage VBE, V

Tj = 100°C

Tj = 150°C

Tj = 50°C

Tj = 0°C

Tj = –50°C

Figure 6-34 Thermal equivalent circuit of BJT.

Heat sink

Power BJT

Die

Ceramic cover

Collector

BaseEmitter

Ta

Tj

Tc

Th

Ta

RthjsPth

Rthjs

Rthha

Rthcs

Rthha

Rthcs

Figure 6-35 Operating domain of BJT in active mode with breakdown mechanisms.

SOAR

IC

ICmax

VCElimit

PVmax = VCEmaxICmax

VCE

Figure 6-36 Construction of (a) MISFET, (b) JFET, and (c) MESFET. The shaded areas depict the space charge domains.

p-type substrate

induced

n-channel

Source

(a) Metal insulator semiconductor FET (MISFET)

(b) Junction field effect transistor (JFET)

(c) Metal semiconductor FET (MESFET)

Gate DrainInsulator

n+n+

Source Gate DrainInsulator

n

p+ substrate

p+n+ n+

n

Buffer

layerSemi-insulating layer

Source Gate Drain

n+ n+

Figure 6-37 Functionality of MESFET for different drain-source voltages.

+

+

S G

D

L

y

+–

–

–

–S G

D

L

d

Low VDS

(a) Operation in the linear region. (b) Operation in the saturation region.

dS(y)dS(y)

High VDS

+

VGS VGS

n+ n+ n+n+

Figure 6-38 Transfer and output characteristics of an n-channel MESFET.

G

S

D

S

–1

1

Linear Saturation

(a) Circuit symbol (b) Transfer characteristic (c) Output characteristic

IDsat/IDSS

VGS/|VT0|

VGS = 0

VGS < 0

VDS

ID

Figure 6-39 Drain current versus VGS computed using the exact and the approximate equations (6.86) and (6.87).

Gate-source voltage VGS, V

Sat

ura

tio

n d

rain

cu

rren

t I D

sat, A

Exact formula

Quadratic law

approximation

–4 –3.5 –3 –2.5 –2 –1.5 –1 –0.5 00

1

2

3

4

5

6

7

VT0 = –3.44

Figure 6-40 Drain current as a function of applied drain-source voltage for different gate-source biasing conditions.

4

3.5

3

2.5

2

1.5

1

0.5

00 1 2 3 4 5

Drain-source voltage VDS, V

Dra

in c

urr

ent

I D,

A

ID = IDsat(VDS)VDS = VDSsat

VGS = –1 V

VGS = –1.5 V

= 0.03

= 0

VGS = –2.5 V

VGS = –2 V

Figure 6-41 Typical maximum output characteristics and three operating points of MESFET.

1

2

3

VDSVDSmaxVDS2VDS1VDS3

ID3

ID2

ID1

IDmax

ID VDS = VDsat

Pmax

Figure 6-42 Cross-sectional view of an n-channel MOS transistor: (a) physical con-struction, (b) symbols.

G

S

D

B

G

S

D

(b)(a)

BDepletion region

Inversion layer

+–

+–

Gate oxide

L

SiO2

p-substrate

S G D

n+ n+

VGS

VDS

tox

Figure 6-43 Generic heterostructure of a depletion-mode HEMT.

0.1

µm

1 µ

m3

00

µm

Source Gate Drain

n-GaAlAs

GaAlAs

2DEGGaAs

Semi-insulating GaAs

30

nm

10

nm

–d

0

x

y

n+ n+

Figure 6-44 Energy band diagram of GaAlAs-GaAs interface for an HEMT.

–d 0x

W

GaAlAs GaAs

2DEG

Schottky

contact

(a) Energy band diagram (b) Close-up view of conduction band

WH

WF

WF

WGaAlAs

WGaAs

∆WC–WG

Figure 6-45 Drain current in a GaAs HEMT.

30

25

20

15

10

5

00 1 2 3 4 5

Drain-source voltage VDS, V

Dra

in c

urr

ent

I D,

mA

VGS = –0.25 V

VGS = –0.5 V

VGS = –1 V

VGS = –0.75 V

VGS = 0 V

Figure 6-46 The internal structure of the LDMOS power transistor BLF4G22-100 at three levels of magnification: (a) overall package, (b) die interconnections, and (c) transistor die (courtesy of NXP).

Drain lead

Bond wire

Die

Inductor

Drain

metallizationSource

finger Drain finger

Bond wireGate finger

Gate

metallization

Inductor

MOS capacitor

MOS capacitor

Gate lead

100 µm

ChipsSource and

heat-sink

contact

5 mm

1 mm

(a)

(b) (c)

Figure 6-47 The power transistor mounted on a demonstration board.