r05410207-vlsidesign (2)
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jntu Vlsi Systems DesignTRANSCRIPT
JNTUWORLD
Code No: R05410207 R05 Set No. 2
IV B.Tech I Semester Examinations,November 2010VLSI DESIGN
Common to Electronics And Computer Engineering, Electronics AndControl Engineering, Electronics And Instrumentation Engineering,
Electrical And Electronics EngineeringTime: 3 hours Max Marks: 80
Answer any FIVE QuestionsAll Questions carry equal marks
? ? ? ? ?
1. (a) Why is the design process carried out in NMOS although CMOS is the dom-inant technology?
(b) Sketch the cross sectional view of the following:
i. NMOS Enhancement mode transistor.
ii. NMOS Depletion mode transistor.
iii. PMOS Enhancement mode transistor. [4+4+4+4]
2. In the inverter circuits, what is meant by Zpu and Zpd? Derive the required ratiobetween Zpu and Zpd if nMOS inverter is to be driven from another nMOS inverter?
[16]
3. (a) Build a comparator using an adder and a complementer and also draw itsschematic.
(b) Draw the product flow of bits for a 4 x 4 array multiplier and explain itsoperation. [8+8]
4. Describe the following briefly:
(a) Cascaded inverters as drivers.
(b) Super buffers.
(c) BiCMOS drivers. [8+4+4]
5. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOSinverter.
(b) What are the effects of scaling on Vt?
(c) What are design rules? Why is metal- metal spacing larger than poly -polyspacing. [8+4+4]
6. (a) Explain how VHDL is developed and where it was used initially.
(b) What are the different design capture tools? Explain them briefly. [8+8]
7. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/Ostructure.
(b) Explain any one chip architecture that used the antifuse and give its advan-tages. [8+8]
1
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Code No: R05410207 R05 Set No. 2
8. (a) What type of defects are tested in manufacturing testing methods?
(b) What is the Design for Autonomous Test and what is the basic device used inthis?
(c) What type of tests are used to check the noise margin for CMOS gates?[4+6+6]
? ? ? ? ?
2
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JNTUWORLD
Code No: R05410207 R05 Set No. 4
IV B.Tech I Semester Examinations,November 2010VLSI DESIGN
Common to Electronics And Computer Engineering, Electronics AndControl Engineering, Electronics And Instrumentation Engineering,
Electrical And Electronics EngineeringTime: 3 hours Max Marks: 80
Answer any FIVE QuestionsAll Questions carry equal marks
? ? ? ? ?
1. (a) Why is the design process carried out in NMOS although CMOS is the dom-inant technology?
(b) Sketch the cross sectional view of the following:
i. NMOS Enhancement mode transistor.
ii. NMOS Depletion mode transistor.
iii. PMOS Enhancement mode transistor. [4+4+4+4]
2. (a) Explain how VHDL is developed and where it was used initially.
(b) What are the different design capture tools? Explain them briefly. [8+8]
3. In the inverter circuits, what is meant by Zpu and Zpd? Derive the required ratiobetween Zpu and Zpd if nMOS inverter is to be driven from another nMOS inverter?
[16]
4. (a) Build a comparator using an adder and a complementer and also draw itsschematic.
(b) Draw the product flow of bits for a 4 x 4 array multiplier and explain itsoperation. [8+8]
5. (a) What type of defects are tested in manufacturing testing methods?
(b) What is the Design for Autonomous Test and what is the basic device used inthis?
(c) What type of tests are used to check the noise margin for CMOS gates?[4+6+6]
6. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/Ostructure.
(b) Explain any one chip architecture that used the antifuse and give its advan-tages. [8+8]
7. Describe the following briefly:
(a) Cascaded inverters as drivers.
(b) Super buffers.
(c) BiCMOS drivers. [8+4+4]
3
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JNTUWORLD
Code No: R05410207 R05 Set No. 4
8. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOSinverter.
(b) What are the effects of scaling on Vt?
(c) What are design rules? Why is metal- metal spacing larger than poly -polyspacing. [8+4+4]
? ? ? ? ?
4
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JNTUWORLD
Code No: R05410207 R05 Set No. 1
IV B.Tech I Semester Examinations,November 2010VLSI DESIGN
Common to Electronics And Computer Engineering, Electronics AndControl Engineering, Electronics And Instrumentation Engineering,
Electrical And Electronics EngineeringTime: 3 hours Max Marks: 80
Answer any FIVE QuestionsAll Questions carry equal marks
? ? ? ? ?
1. (a) Explain how VHDL is developed and where it was used initially.
(b) What are the different design capture tools? Explain them briefly. [8+8]
2. (a) What type of defects are tested in manufacturing testing methods?
(b) What is the Design for Autonomous Test and what is the basic device used inthis?
(c) What type of tests are used to check the noise margin for CMOS gates?[4+6+6]
3. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOSinverter.
(b) What are the effects of scaling on Vt?
(c) What are design rules? Why is metal- metal spacing larger than poly -polyspacing. [8+4+4]
4. In the inverter circuits, what is meant by Zpu and Zpd? Derive the required ratiobetween Zpu and Zpd if nMOS inverter is to be driven from another nMOS inverter?
[16]
5. (a) Why is the design process carried out in NMOS although CMOS is the dom-inant technology?
(b) Sketch the cross sectional view of the following:
i. NMOS Enhancement mode transistor.
ii. NMOS Depletion mode transistor.
iii. PMOS Enhancement mode transistor. [4+4+4+4]
6. (a) Build a comparator using an adder and a complementer and also draw itsschematic.
(b) Draw the product flow of bits for a 4 x 4 array multiplier and explain itsoperation. [8+8]
7. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/Ostructure.
(b) Explain any one chip architecture that used the antifuse and give its advan-tages. [8+8]
5
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JNTUWORLD
Code No: R05410207 R05 Set No. 1
8. Describe the following briefly:
(a) Cascaded inverters as drivers.
(b) Super buffers.
(c) BiCMOS drivers. [8+4+4]
? ? ? ? ?
6
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JNTUWORLD
Code No: R05410207 R05 Set No. 3
IV B.Tech I Semester Examinations,November 2010VLSI DESIGN
Common to Electronics And Computer Engineering, Electronics AndControl Engineering, Electronics And Instrumentation Engineering,
Electrical And Electronics EngineeringTime: 3 hours Max Marks: 80
Answer any FIVE QuestionsAll Questions carry equal marks
? ? ? ? ?
1. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/Ostructure.
(b) Explain any one chip architecture that used the antifuse and give its advan-tages. [8+8]
2. (a) What type of defects are tested in manufacturing testing methods?
(b) What is the Design for Autonomous Test and what is the basic device used inthis?
(c) What type of tests are used to check the noise margin for CMOS gates?[4+6+6]
3. (a) Why is the design process carried out in NMOS although CMOS is the dom-inant technology?
(b) Sketch the cross sectional view of the following:
i. NMOS Enhancement mode transistor.
ii. NMOS Depletion mode transistor.
iii. PMOS Enhancement mode transistor. [4+4+4+4]
4. (a) Build a comparator using an adder and a complementer and also draw itsschematic.
(b) Draw the product flow of bits for a 4 x 4 array multiplier and explain itsoperation. [8+8]
5. Describe the following briefly:
(a) Cascaded inverters as drivers.
(b) Super buffers.
(c) BiCMOS drivers. [8+4+4]
6. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOSinverter.
(b) What are the effects of scaling on Vt?
(c) What are design rules? Why is metal- metal spacing larger than poly -polyspacing. [8+4+4]
7
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JNTUWORLD
Code No: R05410207 R05 Set No. 3
7. (a) Explain how VHDL is developed and where it was used initially.
(b) What are the different design capture tools? Explain them briefly. [8+8]
8. In the inverter circuits, what is meant by Zpu and Zpd? Derive the required ratiobetween Zpu and Zpd if nMOS inverter is to be driven from another nMOS inverter?
[16]
? ? ? ? ?
8
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