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Code No: 37241/37242 R05 Set No - 1

IV B.Tech I Semester Regular Examinations,Nov/Dec 2009VLSI DESIGN

Common to Electronics And Computer Engineering, Electronics AndControl Engineering, Electronics And Instrumentation Engineering,

Electrical And Electronics EngineeringTime: 3 hours Max Marks: 80

Answer any FIVE QuestionsAll Questions carry equal marks

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1. (a) What is Conditional Signal Assignment Statement? Write its syntax withexample.

(b) Explain the method of logic-level simulation for CMOS circuits and name suchsimulators. [8+8]

2. (a) Differentiate between nMOS inverter pair delay and CMOS inverter pair delay.

(b) Derive the expressions for rise and fall time of CMOS inverter delay.

(c) What is the total input capacitance value offered by the inverter to achievesymmetrical operation? [6+8+2]

3. (a) Explain how a Booth recoded multiplier reduces the number of adders.

(b) Draw circuit diagram of a one transistor with transistor capacitor dynamicRAM and also draw its layout. [8+8]

4. (a) Calculate body factor of threshold for the given parametersNA =3 × 1016cm−3, tox = 200A0 , εox =3.9 × 8.85 × 10−14 F/cm,εsi=11.7 × 8.85 × 10−14F/cm, Electron charge =1.6 × 10−19 coulombs.

(b) Mention the parameters on which the threshold voltage depends. [8+8]

5. What is an LUT? Explain how an 4 to 1 multiplexer is implemented using LUT?[16]

6. Distinguish between thin film resistors and thin film capacitors in all aspects. [16]

7. Briefly discuss the limits of scaling. Why scaling is necessary for VLSI circuits?[16]

8. (a) Draw the basic structure of parallel scan and explain how it reduces the longscan chains.

(b) Draw the state diagram of TAP Controller and explain how it provides thecontrol signals for test data and instruction register. [8+8]

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Code No: 37241/37242 R05 Set No - 2

IV B.Tech I Semester Regular Examinations,Nov/Dec 2009VLSI DESIGN

Common to Electronics And Computer Engineering, Electronics AndControl Engineering, Electronics And Instrumentation Engineering,

Electrical And Electronics EngineeringTime: 3 hours Max Marks: 80

Answer any FIVE QuestionsAll Questions carry equal marks

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1. (a) Draw the typical architecture of PAL and explain the operation of it.

(b) What is CPLD? Draw its basic structure and give its applications. [8+8]

2. Describe the two commonly used methods for obtaining integrated capacitor.[16]

3. (a) Write a architecture for a 4- bit Counter in both behavioral and structuralstyles.

(b) Explain with example how mixed mode simulator are more for CMOS circuitstesting. [8+8]

4. (a) Explain how the cost of chip can effect with the testing levels,

(b) Explain how observability is used to test the output of a gate within a largercircuit.

(c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5]

5. (a) Discuss the rule for n well and VDD and Vss contacts (2µm CMOS).

(b) Discuss the rule for pad and over glass geometry (2µm CMOS). [8+8]

6. Describe the following briefly

Cascaded inverters as drivers.

(a)(b) Super buffers.

(c) BiCMOS drivers. [8+4+4]

7. Develop a model for the read time of a ROM with 2n rows and 2m columns analo-gous to that of SRAM. Assume the wire capacitance in the ROM array is negligiblecompared to the gate and diffusion capacitance. Assume the ROM cells are laidout such that two cells share a single diffusion contact and hence each contributesonly C/2 of diffusion capacitance. [16]

8. A CMOS process produces gate oxides with a thickness of tox = 100A0. The FETcarriers mobility values are given as µn=550cm2/V-Sec, µp =210cm2/V-Sec.

(a) Calculate the oxide capacitance per unit area in units of pF/µm2.

(b) Find the process transconductance values for nFET and pFET.Place youranswer in units of µA/V 2. [16]

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Code No: 37241/37242 R05 Set No - 2

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Code No: 37241/37242 R05 Set No - 3

IV B.Tech I Semester Regular Examinations,Nov/Dec 2009VLSI DESIGN

Common to Electronics And Computer Engineering, Electronics AndControl Engineering, Electronics And Instrumentation Engineering,

Electrical And Electronics EngineeringTime: 3 hours Max Marks: 80

Answer any FIVE QuestionsAll Questions carry equal marks

? ? ? ? ?

1. Two NMOS inverters are cascaded to drive a capacity load CL= 14Cg as shownin figure 1. Calculate the pair delay Vin to Vout in terms of τ for the given datainverter-A. [16]Lpu=12λ, Wpu=4λ, Lpd=1λ, Wpd=8λInverter-BLpu=4λ, Wpu=4λ, Lpd=2λ, Wpd=8λ

Figure 1

2. Draw the stick diagram and a translated mask layout for nMOS inverter circuit.[16]

3. Explain the following:

(a) Thermal oxidation technique

(b) Kinetics of thermal oxidation. [8+8]

4. (a) What is the difference between Flop-Flop and Latch? Write a VHDL programfor a latch.

(b) Why logic-level simulators are suitable for testing a fast and large CMOScircuits and how to calculate the delay of the gate? [8+8]

5. (a) Draw and explain the schematic of Pseudo-nMOS comparator.

(b) Draw and explain the structure of multiplier which computes the partial prod-ucts in a radix-2 manner. [8+8]

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Code No: 37241/37242 R05 Set No - 3

6. (a) What is BIST? Explain in detail.

(b) Write the advantages of BIST. [10+6]

7. (a) Discuss the nFET resistance with relevant equations.

(b) Calculate the linearized drain source resistance of an nFET with followingparameters. W=8µm, L=0.5µm, k′n=180 µA/V2, Vtn =0.7V and VDD=3.3V.

[8+8]

8. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/Ostructure.

(b) Explain any one chip architecture that used the antifuse and give its advan-tages. [8+8]

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Code No: 37241/37242 R05 Set No - 4

IV B.Tech I Semester Regular Examinations,Nov/Dec 2009VLSI DESIGN

Common to Electronics And Computer Engineering, Electronics AndControl Engineering, Electronics And Instrumentation Engineering,

Electrical And Electronics EngineeringTime: 3 hours Max Marks: 80

Answer any FIVE QuestionsAll Questions carry equal marks

? ? ? ? ?

1. Explain

(a) Propagation delay

(b) Wiring capacitance. [8+8]

2. (a) Discuss fabrication differences between NMOS and CMOS technologies. Whichfabrication is preferred and why?

(b) Explain the various steps in PMOS fabrication. [8+8]

3. Write briefly about:

(a) Channelled gate arrays

(b) Channelless gate arrays with neat sketches. [8+8]

4. (a) Compare the number of simulation cycles in serial and parallel fault simulationprocesses.

(b) Explain the method of delay fault testing with suitable CMOS circuit. [8+8]

5. Compare the relative merits of three different forms of pull up for an invertercircuits. What is the best choice for realization in

(a) nMOS technology

(b) CMOS technology. [16]

6. (a) Draw the following transistors using lambda based design rules

i. NMOS enhancement

ii. NMOS depletion

iii. PMOS enhancement.

(b) Discuss the design rules for wires (both NMOS and CMOS) using lambdabased design rules. [2+2+2+10]

7. (a) What is the importance of operator precedence in VHDL? Is the AND oper-ation takes place before OR operation?

(b) What is mean by Hierarchy in VHDL? Write a program for 4 input multiplexerfrom 2 input multiplexers. [8+8]

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Code No: 37241/37242 R05 Set No - 4

8. (a) Compare different types of CMOS subsystem Adders.

(b) Draw the mask layout for 6 transistor static RAM used in ASIC memories.[8+8]

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