Radiation Effects in 3D Integrated Systems: A Monte Carlo Analysis of Metallic Layers

M. L. BreedingInterdisciplinary Matierals Science & Engineering Program

Vanderbilt University Nashville, TN 37235

matthew.l.breeding@vanderbilt.edu

R. A. Reed; K. M. Warren, M. L. Alles Electrical Engineering and Computer Science Department

Vanderbilt University Nashville, TN 37235

Abstract—White new technologies implementing 2.5D and 3D integration schemes, there is a growing need to understand the fundamental mechanisms and contributions these new configurations have on soft errors. The complexities of vertical integration present great difficulties in analyzing single event effects; these new difficulties suggest the study of novel component integration schemes starting by simulation of basic test cases and using results to motivate design and experiment options, allowing deeper error analysis by building up and understanding individual contributions. Monte Carlo Radiative Energy Deposition (MRED) is a radiation transport simulation tool developed at Vanderbilt University which provides optimal capabilities for probing the difference between material systems in 3D integrated circuits. Simulations indicate significant single-event response modulation as a function of metal species used for vertical interconnects and other bulk metal layers; these differences are highly dependent on the radiation environment and the device’s critical charge threshold.

Keywords—soft-errors, signle-event effects, radiation transport, neutron radiation effects, semiconductor device reliability

I. INTRODUCTION

Since the development of the transistor and its subsequent implantation in integrated circuits (ICs), Moore’s law has governed the increased performance and compactness of modern computing technologies. As device feature size is pushed farther into the nanoscale, previous key paradigms for understanding device physics and performance begin to break down as certain quantum mechanical effects become significant.

Despite quickly approaching the limit of 2D device performance due to size scaling, industries are highly motivated to continue delivering faster, smaller, and more reliable technologies to the market in keeping with historical trends and customer expectations. This has led to a new direction in semiconductor device research, which seeks to find better ways of enhancing these features without resorting to miniaturization alone. This framework is known as the “More than Moore” approach [1].

As small scale devices become increasingly difficult to

develop and manufacture, the next place to look for improving performance is in how the ICs themselves are interconnected. 2D ICs are spread out on a planar wafer as shown in Fig. 1(a). For relatively large circuits in such a configuration there can be considerable time constraints on processing speed based on the distance the signals are required to travel. Additionally, chips are commonly separated within a system according to functionality (i.e. analog, memory, RF, logic etc. each resides on an individual die which are then interconnected at the substrate level). Research efforts aimed at the More-than-Moore approach are exploring the possibility of stacking components and dies in three dimensions to mitigate these delays and thus improve performance. While universal industry standards have yet to be established for vertical integration, there are several promising directions currently under investigation.

This work is sponsored by DTRA, grant HDTRA1-18-1-0002

Figure 1: Schematic of vertical stacking techniques: (a) Traditional 2D integration (b) 2.5D integration using an interposer with TSVs (c) Overview of 3D integration,

including Through-Mold-Vias (TMVs), Through-Silicon-Vias (TSVs), interposers, and stacked die [4], [5]

DISTRIBUTION A. Approved for public release: distribution is unlimited.

The current state of vertically integrated devices falls into roughly two categories: 2.5D and 3D. Examples of 2.5D and 3D ICs are shown in Fig. 1(b) and Fig. 1(c), respectively. The differentiating feature of 2.5D ICs is the presence of an interposer, which acts as a passive high-density interconnect for the chip(s) mounted on top [4]. Fully integrated 3D ICs, on the other hand, can be broken down into two further categories: 3D packaging and 3D monolithic structures. 3D packaging refers to individually assembled layers which are later joined together in a vertical stack, while monolithic 3D ICs are manufactured in one continuous process flow [6]. Each of these configurations presents unique and challenging problems for reliability testing, as traditionally accessible components are now buried under several active and/or passive layers. Understanding functional or error response is, in some cases, impossible without destroying the device due to the intimate contact required between layers [4]. Components which were previously accessible during device operation are now buried or otherwise not readily contacted.

Several unique challenges are introduced with 3D ICs, all of which require creative solutions due to this lack of access. One of the key reliability issues to consider is susceptibility to radiation. Even in traditional 2D ICs, soft errors specifically can result in a higher failure rate than all other reliability mechanisms combined [7]. Intimate contact between several layers has the potential of enhancing known radiation effects with potentially detrimental results for performance and reliability.

One of the most common ways of interconnecting chips is known as a Through-Silicon Via (TSV) as seen in Figure 1(c). There are several production methods for TSVs, and whereas bulk metallic layers in traditional 2D circuits rarely exist near sensitive regions of the circuit, such intimate contact is unavoidable in 2.5D and 3D circuits. TSVs are thus the primary motivation for the simulations discussed herein.

II. RADIATION EFFECTS AND SOFT ERRORS Radiation effects in semiconductor devices are broken

down into two categories: total-dose effects and single-events [8], [9]. The first deals with the accumulation and trapping of charge within sensitive regions of a device (typically the gate oxide or insulating layers) generated over periods of exposure to irradiation. Single event effects (SEEs) refer in general to any device response which results from the collision of an incident energetic particle.

SEEs can be further classified according to the type of effects they produce within the circuitry. Single Event Upsets (SEUs) and Single Event Transients (SETs) together make up the class of SEE known as soft errors, which manifest as current pulses at sensitive nodes capable of changing the circuit’s logic state [8], [10], [11]. Soft errors pose one of the highest reliability threats to ICs and thus will be the focus of this work [7], [10].

Neutrons generate ionizing radiation through nuclear interactions with the target material and are of specific interest as they are the primary concern of the terrestrial commercial

industry [12]. Due to the intractable nature of closed form analytic solutions to radiation transport and nuclear physics problems in complex materials systems, Monte Carlo methods are used to provide reasonably good approximations of the desired effects.

Figure 2: Critical charges for SEUs in SRAM technology

as a function of feature size [19]

Figure 3: Configuration of the MRED simulation

environment (not to scale). Metal layers used: copper, cobalt, tungsten, ruthenium; silicon used in place of

metal layer to establish baseline response.

There is a wide range of configurations (e.g. characteristic dimensions, materials, and radiation environments) which may be of interest. The approach we illustrate is applicable to that wide range of cases; here, we present case study examples using reasonable dimensions and radiation types of interest in order to illustrate the type of results obtainable. MRED (Monte Carlo Radiative Energy Deposition) is a radiation transport tool built specifically for such a purpose by researchers at Vanderbilt University, capturing the stochastic nature of the relevant physics, and providing reasonable approximations for semiconductor device response [13], [14].

Since charge generation is of primary importance, ionizing particle energy deposition is understood by an approximation known as linear energy transfer (LET), commonly referred to as stopping power. Normalized for material density, LET is given in the one-dimensional case by:

𝐿𝐸𝑇 = − '()*)+(1)

where the differential is the average energy loss (energy deposited) per unit path length. Total energy deposited by an incident particle travelling a distance L is thus given by:

𝐸 = 𝜌 𝐿𝐸𝑇 𝑥 𝑑𝑥/ (2)

𝐸 ≈ 𝜌 𝐿𝐸𝑇(𝑥) 𝐿 (3)

While LET is a useful and accurate simulation tool, a derivation of the concept from first-principles physics remains to be established [15].

For semiconductor materials, the radiation ionization energy, Ee-h, is introduced; this material-dependent parameter describes the average energy required from an incident particle to excite an electron-hole pair (e.g. for Si, Ee-h @ 3.6 eV/pair – roughly three times the band gap) [8]. With this value, the charge generated per neutron-induced event is approximated by the total number of free mobile carriers generated over i ionizing secondary particles as:

𝑄 = ( /*45 + )+*6789:;<=9>?@A (4)

This quantity is of central importance to studying SEUs. When an ionizing particle penetrates the material of an IC, carriers are excited along the particle track length within a device [11]. There are various recombination effects to consider in this process. The depletion region of a junction introduces internal electric fields which sweep away charge carriers and prevent near-instantaneous recombination, allowing instead for charge collection at sensitive nodes of the circuit. 𝑄><9= is defined as the critical amount of charge needed to induce an upset. This is hardly a universal value; 𝑄><9= depends on bias conditions, the size of the device, the structure of the substrate, and the material systems present just to name a few factors [7].

A sensitive volume is defined as a region within which a critical amount of generated charge 𝑄><9= will result in a soft error. This value varies significantly based on the operational parameters of the device. Smaller operating voltages, faster switching times, and reduced sizes are all aspects (projected or actualized) of improved 2D technologies and 3D integration which contribute to lower energy thresholds for soft errors. Sensitive volumes are simulated corresponding to approximations of the spatial dimensions of sensitive regions within the device susceptible to charge generation. The minimum charge that must be collected on a circuit node to cause an upset is called the critical charge, 𝑄><9= . 𝑄><9= for various SRAM technology nodes is presented in Figure 2; SRAM is a common architecture for exploring 3D integration thus these values will prove relevant in the results and discussion section [16]-[18].

III. SIMULATION METHODS In the MRED simulation environment, built on Geant4

[20], a 2 µm X 2 µm X 20 µm silicon wafer is defined as the semiconductor material, with a 0.5 µm X 0.5 µm X 2.5 µm metal plug acting as the TSV embedded at the top, the surface normal to incident neutron irradiation. Sensitive volumes are constructed in MRED as regions within which energy deposition histograms are collected during the simulation. Multiple sensitive volumes are situated below the metal layer, with dimensions corresponding to the sizes of relevant technology nodes. A cartoon of the simulation configuration is given in Figure 3. Neutrons are simulated at energies of 30 MeV, 100 MeV, and 300 MeV in a directional beam. Copper, cobalt, tungsten, and ruthenium are the metal species tested; an additional simulation with silicon in the plug position provides baseline response information. While there are other considerations (conductivity, thermal properties etc.) which certainly play a role in determining material suitability for 3DICs, the effects of radiation as modulated by metal layer selection must be fully explored.

IV. RESULTS AND DISCUSSION The integrated cross section for a given threshold, 𝜎*C8, is

given in units of cm2 (or cm2 bit-1) and denotes the relative probability of depositing 𝐸4D or more of energy within the region of interest (or equivalently, of generating charge greater than or equal to𝑄><9= , where the conversion between charge and energy is given by 22.5 keV/fC).

Fig. 4 shows the result of this cross-section integration for simulations of 30 MeV neutrons ran with Cu, W, and Si as the plug materials. To compare the effects of these different materials on the energy deposited, a range of energy thresholds are considered (illustrated as vertical lines in Fig. 4) where the intersection points give the relevant cross section for a given system. This range as employed in subsequent figures is based on the minimum values of 𝑄><9= as given in Figure 2, corresponding to relevant technology dimensions.

Sampled at lower and higher thresholds, Figure 5 and 6 highlight the differences in response at 30 MeV and 300 MeV

neutrons respectively for sensitive volumes 100 nm2 X 10 nm placed directly below the metal layer. Simulations indicate that the metal layer effectively shields the sensitive region from energy deposition via neutron-produced secondaries regardless of metal species at sufficiently low thresholds. Low energy neutrons do not produce high LET secondary fragments from high-Z targets. Fig. 5 demonstrates this effect, with all metal systems at lower cross sections than that of pure silicon for 𝑄><9==0.44 fc. At higher thresholds and energies (Fig. 6), this shielding effect becomes a function of metal selection and thus of more importance for 3D ICs. High-Z materials such as tungsten are explored in detail as a function of energy in [18]. Figure 7 shows similar data generated from 100 MeV neutron simulations, demonstrating behavior consistent at an intermediate energy relative to Figures 5 and 6.

V. CONCLUSION The configurations of 3D ICs presents new considerations

and challenges for characterization of soft errors. The presence of metallic layers in 3D semiconductor technologies may also complicate SEE studies. Trends towards vertical integration introduce new concerns for such devices due to the introduction of new materials and geometries. The choice of metal used in vertical interconnects and other metal layers may impact soft error rates.

This work has demonstrated the use of Monte-Carlo radiation transport simulations to study the impact of geometry and material choices. In this case study, simulations demonstrate that in lower energy neutron environments, tungsten reduces the vulnerability of circuitry to secondary ion species.. This shielding effect is maintained in the presence of higher energy neutrons for low energy thresholds, with implications for smaller, more rad-sensitive devices. Cobalt and copper are similarly behaved, while ruthenium exhibits no clear advantage over the more traditional copper (or tungsten). Bulk metals are shown to modulate the soft error response of material systems as a function of distance; at close distances, this effect is significant.

Figure 5: Material response to 30 MeV neutrons; secondaries produced in metal layer do not have

sufficient range to escape

Figure 6: 300 MeV neutron response. At higher

thresholds, tungsten and ruthenium generate sufficiently energetic secondaries as to significantly amplify charge

generation.

Figure 4: Example of integrated cross section plot

generated from energy deposition histograms. The vertical lines denote energy thresholds, i.e. the relative probability of depositing energy (charge) greater than or equal to the

threshold amount.

Figure 7: 100 MeV neutron response

Although these data are motivated by and presented in the context of bulk vertical interconnects, further research is needed to determine if such trends are similarly obtained for smaller metallization layers, to verify the trends presented here experimentally, and to explore effects due to multiple layer stacking. Other reliability considerations must be taken into account in conjunction with these data (e.g. thermal, conductive properties) for materials selection in 3D ICs.

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