radiation induced sees
DESCRIPTION
conference presentation for ESREF2015TRANSCRIPT
Radiation-induced Single Event Transients Modeling and Testing on
Nanometric Flash-based Technologies
L. Sterpone1, B. Du1, S. Azimi2
1Politecnico di Torino, Torino, Italy2Noshirvani University of Technology, Babol, Iran
Goal
A new methodology combining an analytical and oriented model for analyzing the sensitivity of SET nano-metric technologies
Results of radiation test experiments on Flash-based FPGA using heavy ions
Outline
• Introduction• The proposed SET nanometer model• SET generation and analytical model• SET characterization
• Experimental analysis• Conclusions and future work
Introduction
Flash-based FPGA Non-volatile configuration memory Floating-gate based switches suffering
from SEEs
Analysis of transient pulse through data path and routing resources Radiation test[3] Electrical fault injection [4][5][6][7]
Strong SET pulse-width modulation when SET pulses traverse logic gates
Proposed Model
Accurate modeling of the SET phenomena generated by radiation particles within the silicon structure of nanometer devices. Generation of the SET pulse Localization of all the combinational gates in the
design Execution of the SET propagation from each
sensitive node till an input of memory element
Integration of physical design analysis and Matlab computations in order to evaluate the dynamic behavior of a VLSI circuit
SET Generation and Analytical Model
On the basis of the Resistive and Capacitive load calculated on the GDS-II 3D model of the circuit
SET Characterization
With SETA tool [11] Locates all circuit combinational gates and Identify their propagation nodes till a memory
element Performs SET propagation of a SET pulse from
each sensitive node traversing all the circuit logic path and
Store the maximal length of SET pulse observed at the input of each memory element
Two databases reporting Maximal SET pulse at the input of each Flip-
Flop The broadening coefficient between all couple
of gates
Radiation Experiment
RISC5x from OpenCores a RISC micro-processor, compatible with
the 12-bit opcode PIC family
Fault Tolerant Strategies
ECC in Regs(RAM)
TMR (Register Triplication with Synplify & Entity level)
with SET-aware Place and Route algorithm [10]
Radiation Test Setup
DUT: ProASIC3 A3P250 from Microsemi Flash-based, 130-nm device
RISC clock frequency: 20MHz
An Altera board used as monitor board Kripton ion beam at Cyclotron of the
Universite Catholique de Louvain (UCL) with support from ESA Fluence: 3.04E8 [particles]
Average flux: 1E4 [particles/secs]
Test Results
Four RISC versions
Test Results
Cross-section [errors/particles] comparing the four versions
Test Results
Error event classification Outputs are repeated sequences of 8
numbers from PORTA
Errors by SEEs can be classified as 4 types
Conclusions and Future Works
Analysis of sensitiveness of a RISC micro-processor against SEEs induced by radiation particles
with different fault tolerant strategies on Flash-based FPGA
The experimental results demonstrate Effectiveness of the proposed approach
Reduction of the SET-sensitivity of more than 76% vs a non-mitigated version, while 48% vs traditional TMR methods
Extend the studies on effectiveness of ASIC cell libraries based 15nm technology
Thanks for attention!
Questions?