Radio Frequency CMOS Transmitter Frequency Modulation in Ultra-Wideband

Leonel Severino de Almeida

INESC-ID / Instituto Superior Técnico, TU Lisbon

Rua Alves Redol, 9

1000-029 Lisboa, Portugal

E-mail: leonelsalmeida@netcabo.pt

Abstract— In order to allocate the growth of different types of RF

devices, a continuous management and usage improvement of the

available spectrum is needed. Also, higher data rates, low power

consumption and smaller circuits are among users, and therefore

industry, top demands.

The Ultra-Wideband concept is focused in sharing already

allocated bands, some of them proprietary, without causing

interference to existing narrowband applications, while allowing

simultaneously high data transmission rates.

This work describes the implementation of a radio frequency

CMOS transmitter operating around 8 GHz, based in a constant-

envelope frequency-domain approach called Frequency

Modulation Ultra-Wideband (FM-UWB) and implemented using

a standard 0.13 µm CMOS technology. The two main transmitter

circuits are based on a relaxation oscillator topology, since it is

inductorless, it is wideband tunable and provides huge area

savings. In this type of oscillator a triangular signal is also

present in the circuit which can be used advantageously in this

type of transmitter.

With the help of a simple control circuit, it is possible to obtain

an FSK oscillator that generates a triangular signal with two

different oscillation frequencies, controlled by the transmitted

data. Also, using only MOS Varactors, it was implemented a

VCO capable of achieving 1 GHz of tuning range bandwidth with

an operation frequency around 8 GHz.

Simulations results are very satisfactory, proving the potential of

the designed circuit in fulfilling the desired goals for obtaining a

low-power and low-cost transmitter, capable of achieving high

data rates and sharing already occupied RF transmission bands.

Keywords - FM-UWB, CMOS Transmitter, Low-Power, Low-

Cost, Low-Area

I. INTRODUCTION

In the past decade, result of the explosive growth of technological devices, short-range wireless networks management became a major priority. The necessity of granting communication and the capability to share information between almost all devices created a demand for RF bandwidths and the increase of transmission data speeds. At circuit level, battery operated, mass market devices, require the development of compact circuits with minimum area and cost, with low power consumption and lower voltage supply, and with high degree of integration, leading to an increase of the

study, research and development both in the academic environment and in the semiconductors and communications industries.

Towards short-range applications, Ultra-Wideband Radio Technology can drive the potential solutions for many of the identified problems in the areas of spectrum management and radio systems engineering. The novel and unconventional approach underlying the use of modern UWB is based on the optimally sharing of the existing radio spectrum resources rather than looking for still available but possibly unsuitable new bands [1].

In radio frequency communication systems, modern Ultra-Wideband is used to describe signals with a minimum bandwidth of 500MHz, (for operation frequencies above 3.1GHz) [2], by comparison with traditional narrowband communication systems, with bandwidths of a few kHz.

In order to allow UWB transmission in allocated bands, the signal power level must be very low, therefore Federal Communication Commission authorized wideband signal format with a low Effective Isotropic Radiated Power level of -41.3 dBm/MHz, creating this way a UWB signal mask that prevents interference with other systems.

The UWB definition does not specify any type of air interface or modulation scheme, so it is possible to use many different techniques to create this type of signal [2]. Three of the most common implementation techniques are Impulse Radio UWB (IR-UWB), Multi-Band Orthogonal Frequency Division Multiplexing (MB-OFDM) and more recently Frequency Modulation UWB (FM-UWB).

This paper explores the development of a radio frequency CMOS transmitter using a 0.13 µm CMOS technology and based in a constant-envelope frequency-domain approach called Frequency Modulation Ultra-Wideband (FM-UWB). First is applied a low-modulation index, using digital frequency-shift keying (FSK), followed by high-modulation index analog FM, thus, a constant-envelope signal with flat spectrum and a very wide bandwidth with step spectral roll-off is produced, as shown in Figure 1.

The purpose of this transmitter is mainly portable non-critical applications and its key features are minimum area and cost, low power consumption and low voltage supply. Also,

This work was supported by FCT (INESC-ID multiannual funding) through PIDDAC

Program Funds and SCOMagNo (PTDC/CTM-NAN/112672/2009).

FM-UWB is being proposed as a standard for biomedical applications.

Figure 1 - Spectrum of a FM-UWB signal and an unmodulated RF carrier

at 4 GHz [2].

This paper is organized as follows: Section II – Transmitter Architecture. A study about the concepts involving the FM-UWB transmission technique is performed and the characteristics of each block composing the transmitter are defined; Section III – Circuit Implementation. The implementation of each block composing the circuit is described along with the several modifications performed to a single relaxation oscillator topology in order to adapt its different characteristics to the transmitter requirements; Section IV – Simulation and Results. Simulation results for the transmitter and its final circuit parameters are presented, along with the circuit layout. Besides the circuit core simulation, it is included an overall demonstration of the circuit performance using already an output buffer, bonding wires, pads and ESD protections; Section V – Conclusions.

II. TRANSMITTER ARCHITECTURE

FM-UWB use a double FM scheme, which means that first, is necessary to modulate a subcarrier signal m(t) using the data to be transmitted d(t) and then use this subcarrier signal to modulate the carrier signal XFM(t) as illustrated in Figure 2.

Figure 2 - Time-domain view of data d(t), subcarrier m(t), and UWB signal

XFM(t) [2]

The FM-UWB transmitter proposed in this paper is based in two main blocks (Figure 3), a frequency-shift keying oscillator, controlled by the data, which is the key element to generate a sub-carrier signal, and a voltage controlled oscillator used to produce the carrier signal.

Figure 3 - FM-UWB high level modulator schematic.

A. Subcarrier Modulation

To obtain a transmitted signal with UWB properties such as a flat spectrum and a very wide bandwidth with steep spectral roll-off is necessary to have a triangular waveform signal modulating the RF carrier signal, as presented in Figure 2.

This subcarrier must also contain information, so some of its properties must change according to the modulating data. Once again, the change will only be performed in its frequency, which means that we are again in the presence of frequency modulation. This type of discrete frequency modulation is called frequency-shift keying. For our specific case, the modulation will be made to transmit only binary data (BFSK) with a low-modulation index fΔ.

Thus, the subcarrier block generates a triangular wave signal with two different periods T0 and T1, corresponding to the two different frequencies f0 and f1, needed to codify the data d(t) digital low (0) and digital high (1), respectively.

B. Carrier Modulation

The carrier modulation is implemented using a VCO. This circuit generates a sinusoidal carrier that can be represent by (1)

(1)

where AC is the carrier’s amplitude and (t) is the carrier’s instantaneous phase, that can be represented by (2)

(2)

𝜙 (t) represents the phase instantaneous deviation and to perform a change in carrier’s frequency fc, it is necessary to define the frequency instantaneous deviation F(t) (3)

(3)

where fΔ is the frequency modulation index or the frequency deviation used to describe the maximum instantaneous difference between an FM modulated frequency and the carrier’s frequency fc.. In these conditions it is possible to define the VCO transfer function (4)

(4)

This block defines carrier’s amplitude AC, center frequency fc and the VCO gain that corresponds to the frequency deviation fΔ.

These three parameters are directly related to the fundamental properties of the transmitted signal, such as the transmitted power and the signal bandwidth, which means that it is necessary to determine which values are needed to obtain the required specifications, as the data rate and the power transmission.

C. Transmitter Characteristics

The transmission power allowed is clearly the most

important specification, since it is a requirement to the signal

transmission. The range with line of sight (LOS), the RF centre

frequency as well as the raw data rate were chosen taking in

consideration some aspects, such as the final applications and

the compatibility for transmission in different regions of the

globe.

The carrier’s amplitude, the RF bandwidth and the

subcarrier frequencies are other transmitter characteristics that

are not specifications, but result from the simulations made to

respect those specifications.

All the referred characteristics are presented in table I.

TABLE I. TRANSMITTER CHARACTERISTICS

Transmission power ≈ -42.78 dBm/MHz

Range with LOS 2 m

RF centre frequency 7.9 GHz

Raw data rate 1 Mbps

Carrier amplitude 25 mV

RF bandwidth 1 GHz

Subcarrier frequencies 2 – 4 MHz

III. CIRCUIT IMPLEMENTATION

To implement the transmitter, two relaxation oscillators are used, one to implement the subcarrier generator and the other to implement the voltage controlled oscillator. In both blocks,

different characteristics of this type of oscillator are exploited. Since both oscillators are inductorless circuits, it is possible to minimize the area size and the complexity of the transmitter, leading to a low-cost and low-power implementation.

A. Relaxation Oscillators

It is possible to separate the existing oscillators in two main types: quasi-linear oscillators and strongly non-linear [3].

Quasi-linear oscillators include the LC oscillators, the most common in this category. LC oscillators can use dielectric resonators, crystals, striplines and LC tanks as a resonator element and are known by their good phase-noise performance.

Strongly non-linear (or relaxation) oscillators are usually implemented with RC-active circuits [4]. Relaxation oscillators are RC type and tend to have a higher phase-noise when comparing to LC oscillators. However, by using only resistors

and capacitors as passive devices, instead of inductors, relaxation oscillators can achieve lower area and cost, being widely used in fully integrated circuits where phase-noise requirements are not demanding [4], [5].

The relaxation oscillator is referred to as a first order oscillator, since its behaviour can be described in terms of first order transients [6]. The simple operation mode is based on the alternated charging and discharging of a capacitor between two threshold voltage levels that are pre-defined, and its oscillation frequency is inversely proportional to its capacitance [7].

Relaxation (or RC) oscillator operation mode can be

described using a high-level model, comprising an integrator and a Schmitt-trigger, as shown in figure 4.

Figure 4 - Relaxation oscillator block diagram.

The Schmitt-trigger controls the sign of the integration constant by imposing a threshold value to the integrator, the sign is changed when that value is reached. The output waveforms of the two blocks are represented in figure 5.

Figure 5 - Oscillator output waveforms VINT and VST.

The oscillator implementation should be as simple as possible for operation at very high frequencies, reducing this way the number of potential noise sources. The relaxation oscillator topology used is presented in figure 6.

Figure 6 - Relaxation oscillator implementation.

B. FSK Oscillator Implementation

It is usual to use a direct digital synthesizer (DDS) for this type of subcarrier generation [8], but due to its complexity, it was chosen to use an oscillator. It is necessary to generate a triangular wave with two different frequencies of operation and to do so, the characteristic that will be explored in the oscillator

is the integrator output waveform VINT rather than the usual Schmitt-trigger output waveform VST.

1) FSK Implementation

The integration constant is the current that flows through the capacitor over its capacitance (ic/C), meaning that changing the current ic or the capacitance C, will linearly change the capacitor time of charging and discharging and therefore the frequency of the output waveform VINT, as shown in figure 7.

Figure 7 - Integrator waveform vC0 (corresponding to a capacitance C) and vC1

(corresponding to a capacitance 2C).

The solution adopted was to change the oscillator capacitance value and to perform that, the oscillator is implemented with two capacitors of about the same value, where one of them could be used or not, by turning on or off a pair of transistors. This circuit is illustrated in figure 8.

Figure 8 - Relaxation oscillator with variable capacitance.

This implementation leads to a differential output where the pretended waveform is vC = v3 – v4. When the signal DATA is equal to “0” the transistors M3 and M4 will be cut-off and vC will be equal to vC0, otherwise when DATA is equal to “1” the transistors M3 and M4 will be conducting and the capacitance value will lead to vC equal to vC1.

2) Control Circuit

To guarantee that the capacitance value only changes when the capacitor completely charges or discharges, it is necessary to develop an additional control circuit. By performing this operation the error introduced in the modulated signal is lower. However, it is impossible to eliminate this error completely since it results from the impossibility to generate signals with an infinite frequency precision, due to the discrete capacitance values allowed.

The control circuit schematic is shown in figure 9.

Figure 9 - Control circuit schematic.

The control circuit is composed by a buffer and a flip-flop

D edge-triggered. The buffer is used to transform the signal v1 or v2 into a digital signal, that will be used as clock to control the flip-flop D. This way, the flip-flop D only changes its value when v1 or v2 changes, synchronizing the signal DATA with the integrator transitions. The signal d(t) represents the data to be transmitted.

C. VCO Implementation

The VCO is implemented using a relaxation oscillator whose capacitance variation is controlled by a reference voltage in a linear way. This oscillator also generates a sinusoidal carrier necessary for transmission. Considering the oscillator output the signals vout1 or vout2, and knowing that for higher oscillation frequencies these signals present an almost sinusoidal behavior, the major problem concerns the wide variation needed to achieve at least 1 GHz bandwidth.

The most conventional solution is to use an array of p-n junction varactors to provide a linear and continuous frequency tuning range within different bands, however, this solution implies a control circuit with some complexity.

The solution adopted in this work is to use the parasitic capacitances gate-source Cgs and gate-drain Cgd of a MOS transistor as variable capacitances.

Combining some properties of the MOS transistors that

affect its parasitic capacitance and rearranging the basic

relaxation oscillator topology, it is also possible to use the

differential output produced by the FSK oscillator, otherwise it

would be necessary to use a differential-to-single converter,

introducing more complexity to the circuit and possible signal

distortion. The proposed topology for the VCO is presented in

figure 10.

Figure 10 - Proposed topology for VCO with MOS varactors and differential tuning signals.

1) MOS Varactors

MOS varactors are variable, voltage-controlled capacitors based on the MOS structure. Their main advantage is an intrinsic capacitance ratio (Cratio) that is much higher than that of p-n junction varactors. For the small-signal model, Cratio values of 2 to 5 can be achieved in practice, even with control voltage swings as small as 1V [9].

The MOS varactor is not a four-terminal device as the transistor but a three-terminal device. The source and drain regions are shorted to apply the voltage Vtune that tunes the variable capacitance. The p- body is grounded and the voltage Vgate is applied to the gate node. The variable capacitance CG (5) appears between the gate node and all the others.

CG ≈ Cgs + Cgd (5)

Depending on the voltage applied at the gate terminal Vgate,

it is possible to define different operation regions for the MOS varactor, known as accumulation-, depletion- and inversion-mode. Inversion- and accumulation-mode are the most common varactor configurations. Because electrons are the majority carriers in the depletion and accumulation regions, the accumulation-mode device has less parasitic resistance than the inversion-mode device, which uses holes as majority carriers [10].

For the NMOS device, the source and drain are n+ doped.

The substrate (or well) region between and around source and drain is of opposite doping, i.e. p

- type. Process determined the

polysilicon gate is of the same doping as source and drain, i.e. n

+ type. A PMOS device is obtained when all regions have

opposite doping as in the NMOS [11]. Hence, the inversion-mode capacitance characteristic CG of a PMOS varactor is the symmetric of a NMOS varactor. In figure 11 are represented both NMOS and PMOS inversion-mode capacitance characteristics CG.

Figure 11 - PMOS and NMOS varactor inversion-mode capacitance characteristic CG.

Due to these characteristics, since they are symmetric, using a NMOS varactor as variable capacitance C1 and a PMOS varactor as variable capacitance C2, (remember figure 10), allow the possibility to use the differential output produced by the FSK oscillator, to generate a carrier with the desired frequency variation. Also, it was necessary to use a pair of varactors for both capacitances (C1 and C2), not only to achieve the desirable capacitance variation values, but also to create a common input control terminal, as shown in figure 12.

Figure 12 - Three terminal MOS varactor circuit schematic.

IV. SIMULATION AND RESULTS

The transmitter core schematic is presented in figure 13. In order to simplify the drawn schematic the current sources are only represented by its symbols

Figure 13 - Transmitter core circuit schematic.

In table II the final elements parameters used in the transmitter are shown. All the elements used to implement the transmitter are RF elements from the UMC 0.13 µm design kit. The transistor models used to implement the NMOS and PMOS type were the N_12_RF and P_12_RF.

TABLE II. TRANSMITTER CORE PARAMETERS

The variable capacitances C1 and C2 were implemented

with a pair of varactors assembled in anti-parallel. The variable capacitances C3 and C4 represent the MOS varactors implemented with two pairs of MOS transistors. Transistors M1C3 and M2C3 correspond to capacitance C3 and transistors M1C4 and M2C4 to capacitance C4, as indicated in the previous table.

In figure 14 is possible to observe that the signal DATA impulses have different duration. These different duration impulses result from the constant synchronization between the output produced by the FSK oscillator and the original data d(t), this happens due to the impossibility of creating an oscillator with an infinite precision frequency, as already referred.

Figure 14 - Signal d(t) with transitions between “0” and “1” and simulation

result for signal DATA.

The output Vtune1 and Vtune2 produced by the FSK oscillator, as well as the differential signal vc (resulting from the difference between them), are illustrated in figure 15 and figure 16.

Figure 15 - Differential output produced by the FSK oscillator.

Figure 16 - Simulation result for the signal vc (Vtune1-Vtune2).

In figure 17 is possible to observe the synchronization between the signal vc and the signal DATA.

Figure 17- Simulation result showing the synchronism between the signal

DATA and signal vc.

In figure 18 is presented the signal Vout1 along with a graphical result of its instantaneous frequency variation during the simulation.

Figure 18 - Simulation result for signal Vout1 (including its instantaneous

frequency).

The signal Vout1 presents some amplitude modulation. This phenomenon occurs due to the frequency variation in the VCO. Since it is working at very high frequencies, the VCO output voltage does not have enough time to reach its maximum and minimum values, (which also grants to the signal an almost sinusoidal behavior). Thus, for higher frequencies the signal has a lower amplitude and vice-versa. The signal presents a frequency variation between 7.37 GHz and 8.50 GHz and its maximum and minimum voltage are 1.14 V and 545 mV respectively.

A. Results using Pads, Bonding Wires, ESD protection and

Antenna

The signal Vout1 has an average amplitude of 425 mV, since the pretended amplitude value for transmission is of about 50 mV peak-to-peak (to respect the imposed EIRP level), a simple common drain stage is used to drive the load.

This common drain stage is usually used as an isolator [10]. It was implemented with two transistors, in which transistor M2 is used as a current source, as shown in figure 19.

Figure 19 - Common drain stage schematic.

In order to connect the circuit core with the test board it is necessary to use pads and bonding wires, thus, it is important to test the circuit with these elements, since they can affect the circuit performance and its respective output signal. Moreover, it is also used electrostatic discharge (ESD) protection elements to prevent permanent damage in the integrated circuit while it is being tested. ESD is easy to occur by a

simple human touch in the circuit terminals, so it is necessary to add this protection in the nodes that are connected to the outside. Another important element for the transmitter simulation is the antenna, since it is necessary to evaluate the emitted signal.

The pad and the ESD protection parameters are presented in table III. The schematic of the ESD protection is depicted in figure 20 (a). The bounding wire model schematic is presented in figure 20 (b) and the its parameters presented in table IV. The antenna model used is depicted in figure 20 (c), with its values presented also in table IV for a nominal frequency of 8.3 GHz.

TABLE III. PADS AND ESD PROTECTION PARAMETERS

Width [m] Length [m] Multiplier

Pads 74.2 µ 74.2 µ 1

ESD protection 600n 120µ 1

TABLE IV. BOUNDING WIRE AND ANTENNA MODEL PARAMETERS

R L C

Bounding Wire 1 Ω 2 nH 100 fF

Antenna 50 Ω 3.99 nH 92 fF

Figure 20 - Circuit Schematic for (a) ESD protection, (b) bounding wire and

(c) antenna model.

In figure 21 is shown the antenna output signal Vant out along with two samples that allows a closer look into the signal shape and amplitude. Also, in figure 22 is depicted the signal Vant out instantaneous frequency and its respective DFT.

Figure 21 - Simulation result for signal Vant out.

The signal Vant out presents the expected sinusoidal behaviour. The output buffer parameters were adjusted to allow a signal Vant out maximum amplitude of [-36.23, 35.71] mV and a minimum amplitude of [-17.07, 16.98] mV. The signal average amplitude is of about 53 mV (peak-to-peak), what is concordant with the pretended value of 50 mV, although this undesired amplitude modulation will slightly affect the transmitted PSD, as shown in figure 22.

Figure 22 - Simulation result for signal Vant out instantaneous frequency and DFT.

The signal Vant out presents a frequency variation between

7.33 GHz and 8.50 GHz, corresponding to a 1.17 GHz

bandwidth. The highest PSD sample value detected is of -

40.937 dBm, corresponding to a frequency of 7.372 GHz.

Despite this value being out of the EIRP level allowed by the

FCC, a closer look in the DFT reveals that only 3 bins are

above the FCC spectral mask. As shown in figure 22, the

majority of the bins are way below the allowed value of -41.3

dBm, meaning that in practice this value may even not be

achieve if we consider all the non-idealities, concerning the

signal attenuation, that were not taken in account.

A summary of the transmitter characteristics obtained with

this simulation, including the expected consumption of all

circuits used in its implementation, are shown in table V.

TABLE V. TRANSMITTER SIMULATION RESULTS

The layout presented in figure 5.18 is the FM-UWB

transmitter already including the pads, the ESD protections and the respective output buffers designed for the VCO output signals. This layout has an area of 360 µm x 366 µm ≈ 0.132 mm

2.

Figure 23 - FM-UWB transmitter layout with pads, ESD protections and

output buffers.

V. CONCLUSIONS

This paper describes the implementation of a radio frequency CMOS transmitter operating around 8 GHz, based on Frequency Modulation in Ultra-Wideband and using a 0.13 µm CMOS technology

The circuit topology was selected to fit the requirements, since the basic purpose of the circuit was to target low cost applications, it was decided to use inductorless circuits reducing the circuit area and leading to a price decrease. The solution was to use a relaxation oscillator topology, (based only on resistors and capacitors as passive elements), that after a brief study revealed that had the potential to be adapted in order to obtain the desired results.

To implement the FSK oscillator, a second capacitance and a pair of switches was added to the RC oscillator, allowing the possibility of obtain a triangular signal with two different frequencies, capable of being controlled by the transmitted data with the help of a simple control circuit.

Taking advantage of the differential output produced by the FSK oscillator and using an NMOS and a PMOS varactor as variable capacitances, it was possible to redesign an RC oscillator and convert it into a VCO capable of achieving 1.17 GHz of bandwidth.

The standalone simulation of the transmitter core and the simulation including all the circuits and components needed to broadcast the signal showed very satisfactory results, proving the capabilities of the designed circuit.

Finally and after the circuit layout design it was possible to conclude that there is a huge area saving when compared with circuits using inductors.

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