radio frequency integrated circuits communications: design...

Radio Frequency Integrated Circuits for Communications:

Design, Analy sis and Experiments

bY Mihai Adrian Margarit

Dipl. hg., Politehnica Univ. Bucharest, Romania, 1984

A THESIS SUBMITïED IN PART= FULFILLMENT OF

THE REQUIREMENTS FOR THE DEGREE OF

DOLTOR OF PHILOSOPHY

in the School

of

Engineering Science

Mihai Adrian Margarit 1999

SIMON FRASER UNIVERSITY

May 1999

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Abstract

This thesis focuses on the research of novel techniques for radio frequency circuits

used in communications. The purpose of the research is to develop state-of-the art mono-

lithic circuits as well as to implement novel analysis techniques that are specific to radio

frequency applications. These analysis techniques provide the designer with investigation

tools that are more powerful than classic simulators such as SPICE.

First, architectures of a communication system are presented. The important func-

tions of building blocks within a communication system are outlined and components

such as low noise amplifiers, voltage-controlled oscillators and phase-locked loops are

pointed out as key components.

Second, the design principles for low noise and low distortion that are extremely

useful in the design of communication circuits are investigated. These principles are of

general interest and they will be used throughout this research work. A novel high fre-

quency BJT mode1 and a low noise, low distortion amplifier design are presented and dis-

cussed, and comparisons are made between analytic calculations and simulations.

Third, voitagecontrolled oscillaton are investigated in detail. High performance

design solutions are identified that provide high immunity to substrate coupling, low

phase noise levels and low power consumption. The principles for low phase noise design

in oscillators are investigated. A low phase noise VCO is implemented and characterized.

The novel analysis method used to investigate the phase noise performance of this design

is described, and good agreement between experiments and shulations/modeling were

obtained.

Fourth, phase-locked loops with specific application in communications are ana-

lyzed. A iow noise, high spectral purity frequency translational loop used in radio trans-

ceivers is implemented and characterized. A novel analysis method is developed in order

to investigate the spectral purity performance of the frequency translational loop and good

results, as well as good agreement between experiments and simulations, were obtained.

Finally, novel radio frequency circuit techniques were developed. At the same

Ume, new and innovative analysis methods were implemented that allow for an in-depth

investigation of circuits performance in terms of noise and spectral purity. This research

creates the fiame work for future developments in the area of radio frequency circuits,

such as VCO's and PLL's for communications.

Acknowledgments

It is my pleasure to acknowledge the thoughtful guidance provided by Dr. M J. Deen,

my senior supervisor, during the course of this thesis, and for affording me the opportunity

for academic advancement. W ithout his care ful supervision, encouragement, assistance

and feedback, this thesis would not be completed. 1 also thank the following members of

Prof. Jamal Deen's Integrated Devices and Circuits Research Group - Javier de la Hidalga

(INAOE, Puebla), P. Kolev, W. S. Kwan, Chih-Hung Chen, L. Nathawad (now a graduate

student at Stanford), A. Raychaudhuri (now at Rockwell) and Z.X. Yan (now at Rockwell)

- for their support, cornrnents and assistance during the course of this research.

1 wish to thank Dr. Elmasry, Dr. Steve Hardy, Dr. Shawn Stapleton and Dr. Ljiljana

Trajkovic for acting as members of my thesis examining conunittee. I would like to thank

the Canadian Microelectronics Corporation for arranging the fabrication of the test chips.

1 am also grateful to Micronet, a Federal Center of Excellence in Microelectronics,

Mitel, Norte1 and the Natural Sciences and Engineering Research Council (NSERC) for

various financial support of this research.

I also wish to thank my family for their encouragement and understanding in my

academic pursuits.

TABLE OF CONTENTS

... Abstract ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Acknowledgments ..................................................... ...... ........-..-.. .................. v Table of contents .............................................................................................. vi List of figures .................................................................................................... ix

-. . List of tables ....... .-....-..S.-....-.S..-..................... . ....................... ...... ...-..... ..-.... . .... .XIII

List of symbols and acronyms ..............................-.........-.......*......................... xiv

Chapter 2 Low Noise, Low Distortion Amplifiers for Radio Frequency Appüca-

2.1 Introduction .................... .. ................................................................... 5 2.2 Review of Literature on Low Noise Amplifiers. ......................... . .-......... -3 2.3 Design of Low Noise Amplifien. ............................................................... 7

2.3.1 Noise Mode1 of the BJT at High Frequency. ........ .... ...... ... ............... -.7 2.3.2 Front-end Matching for Low Noise Ampli fiers ... .... . . . . . ... .. . . . .. .. . . . . .. ... 20

2.4 Design for Low Distortion .............................. ......- 2.4.1 Conventional Distonion Analysis ...................................................... 24

2.4.2 High Frequency Distortion .4nalysis Using Volterra Series .............. 38

2.4.3 Distonion Analysis of RF Amplifiers with Adjustable Gain ............. 46 2.5 Design of a Low Noise Amplifier with Adjustable Gain for

Radio Frequency Applications ...... .... .. ...... . .. . .. .. . . . . . . . . . . . .-. . . . . . . . .. ..... .. . .. . ..49

2.5.1 Design of the Low Noise Amplifier ................................................... 49

2.5 -2 Simulation Results . . . .. .. . .. ... . . .... . . ... . .. .. .. .. . ... .. ... . . .-.. .. .. .. . . . ..-. 53

2.5.3 Measurement Results ... ..,... . . .... .. ... .. .. . .. . .. .. . . . . . . . . . . .. .. .. . . ... -. ...- ... . ..-. -54 REFERENCES .. ......... . . .... .. . . . .. ... ..... ...... .. ... . .. .. .. .. . .. . . . ... .. . . . . .. . ..... . .. . . . .. .. .. . . . . . - 3 6

Chapter 3 ............................. Monolithic LC Voltage-ControUed Oscillators .. 59

................................................................................................. 3.1 Introduction 59 ...................................................... 3.2 Review of Literature on LC Oscillators 59

3.3 LC Oscillator Topologies ........................ ...... ....................................... 60

3.3.1 Single Ended and Differential Topologies for Monolithic LC .......................*.......... .................*..............-.--...--....--. Oscillators ...... 6û

3 -3 -2 Topologies for Voltage-Controlled Oscillators .................................. 69 ...................................................... 3.4 Voltage-Controlled Oscillator Start-Up 73

.......................................................................... 3.4.1 Oscillation Build-Up 73 ...................................................... 3.4.2 Oscillator Steady-State Behavior -76

...................... 3.4.3 Voltage-Controlled Oscillator Resonator Topologies -77 ................................................................................................ REFERENCES 82

Chapter 4 Phase Noise in Oscillators mmmooooooooooooooomoooooooo~ooomooomoooomomoooooooomooooooooooomo 84

4.1 introduction .............................................................................................. 84 4.2 Small Signal Noise in Oscillators .............................................................. 86

4.2.1 Small Signal Noise Analysis in Oscillators ........................................ 86

4.2.2 The Duality between Phase Noise in Frequency Domain and .......................................................................................... Time Jitter 92

.... 4.2.3 Optimization of Oscillator Components for Minimal Phase Noise 94 ..................................................... 4.3 Nonlinear Noise Analysis in Oscillators 98

................................................. 4.3.1 Effects of Nonlinearity in Oscillators 98

.......................... 4.3.2 Noise Analysis Based on the State Space Approach 99

4.3 -3 Techniques for Reduction of Phase Noise Generated by ..................................................................................... Nonlinearities 101

4.4 Design of a Low Noise Low Power VCO with Automatic Amplitude .........*.......... .......................... Control for Wireless Applications ..... 102

4.4.1 Design of a High Frequency VCO with Automatic Amplitude ....................................................... ............................ Control ...... 1 0 2

................................................................ 4.4.2 VCO Phase Noise Analysis 107

......................................................................... 4.4.3 Measurement Results 119 ............................................................................................... REFERENCES -122

. vii .

Chapter 5 Monolithic Phase-Lock Loops for Communications Appücations 124

............................................................................................ 5.1 Introduction 124 ........................ 5.2 Review of Literanire and Theory of Phase-Locked Loops 124

.................................................................. 5.2.1 Review of PLL Literature 124

5.2.2 Basic Theory of the Phase-Locked Loop .......................................... 126

5 .2.3 Building BIocks for PLL' s Used in Communications ....................... -137 5.3 Modeling and Simulation of Phase-Locked Loops ..................................... 142

.................................................... 5.3.1 Advanced Simulation Techniques 1 4 2 ..................................... 5.3.2 Behavioral Models used in PLL Simulations 146

5.4 Design and Simulation of a Low Noise High Spectral Punty Frequency Translational Loop for Wireless Communications ................... 149

5.4.1 Design of the Frequency Translational Loop ..................... ... ......... 149

........ 5.4.2 Analysis and Simulation of the Frequency Translational Loop 154 ....................................................................... 5.4.3 Measurement Results 161

................................. .................................. REFERENCES ... 164

Chapter 6 Conclusions ................................................ 166

Appendix A ..... SPICE File Used for Simulations of the High Frequency BJT Mode1 169

. viii .

Fig . 1.1. Fig . 2.1.

Fig . 2.2. Fig . 2.3. Fig . 2.4. Fig . 2.5. Fig . 2.6.

Fig . 2.6. c) Fig . 2.7. Fig . 2.8. Fig . 2.9. Fig . 2.10. Fig . 2.1 1 . Fig . 2.12. Fig . 2.13. Fig . 2.14.

Fig . 2.15.

Fig . 2.16. Fig . 2.17. Fig . 2.18. Fig . 2.19. Fig . 2.20. Fig . 2.2 1 .

Fig . 2.22.

Fig . 2.23. Fig . 2.24. Fig . 2.25.

..... Block diagram of a tranxeiver used in wireless communications 2

Evolution of microelectronic technologies for high frequency ......................... applications .. ........................................................... 6

.......................... BJT with emitter degeneration (small signal model) 7 ............................................................. RC network equivalent to Zm 10

. .......... BJT high frequency mode1 . Zm is of the type given in fig 2.3 1 1 n -mode1 used to denve the BJT T-mode1 .................... .... .......... 12

a) T-Mode1 of the BJT obtained from the n -Modele b) n -Mode1 with ................................................................. equivalent resistor r, = l/g , 13

T-Mode1 of the BJT with the intrinsic noise sources: ......................... 13 .......................... . Noise figure vs frequency with Cu* and Cu=2 1 fF 16

Noise figure vs . source reactance ........................................................ 17 Noise figure vs . source resistance ................................. .... ................. 17 Noise figure vs . bias current ............................................................... 18 Optimum source reactance vs . frequency .......................................... 19 Optimum source resistance vs . frequency .......................................... 20 Input matching network for low noise amplifier ................................ 22 Cut-off frequency fT versus bias current in a bipolar transistor . Operation region is chosen to be 10%-20% lower than peak fT ....... 23 Nonlinear transfer function that lends itself to a power series expansion ......................................................................................... 25

Effect of feedback on distortion ...................................................... 30

Distortion in common-emitter BJT ..................................................... 32 Distortion analysis on BIT with finite source resistance .................... 34 Distortion in BJT differential pair ....................................................... 35

....... Block diagram used for illustration of Volterra senes expansion 39

Model used for high frequency distortion analysis in ............................................................................... single ended stage 40

Model used for high frequency distortion analysis in differential pair .................................................................... ......................... stage .. 4 4

Wide-band amplifier with adjustable gain .......................................... 46 Distortion level vs . attenuation for the circuit of fig . 2.23. ................. 49

..................... Block diagram of the IF amplifier with adjustable gain 50

Fig . 2.26. Fig . 2.27. Fig . 2.28. Fig . 3.1. Fig . 3.2. Fig . 3.3. Fig . 3.4. Fig . 3.5. Fig . 3.6. Fig . 3.7.

Fig . 3.8. Fig . 3.9. Fig . 3.10. Fig . 3.1 1 . Fig . 3.12. Fig . 3.13. Fig . 3.14-

Fig . 3.15- Fig . 3.16. Fig . 3.17. Fig . 3.18,

Fig . 3.19. Fig . 4.1. Fig . 4.2.

Fig . 4.3. Fig . 4.4. Fig . 4.5. Fig . 4.6.

Fig . 4.7. Fig . 4.8.

Fig . 4.9.

IF amplifier with adjustable gain .................... .. ....... ... ............ 5 1 Simulated ac-gain versus frequency . 3dB bandwidth is at 4SOMHz .. 54 Microphotograph of the IF amplifier ............................................ 5 6 General LC oscillator .......................................................................... 60 Colpitts osciilator ..................... .. ..................................................... 62 Circuit with negative input resistance ............................................. 62 Clapp oscillator ................................................................................. 64 Pierce oscillator ................................................................................... 64 Modified Colpitts osciilator for cornmon base configuration ............ -66 Oscillator with capacitive feedback in common ernitter configuration ....................................................................................... 67

......................... Fully differential oscillator 6 t h capacitive feedback 68 .......................................... Single ended voltage-controlled oscillator 70

............................................ Differential voltage-controlled oscillator 70 ................................................................... Differential CMOS VCO -71

.................................................. Enhanced differential Colpitts VCO -72 ........................... ............................ Harmonic Oscillator Models ..... -73

a) ECP with positive feedback (left) and b) 1-V charactenstic of ECP (right) ................................................................................... 77 VCNR with varactor-tuned parallel resonant tank .............................. 78 Equivdent circuit of figure 3.1 5 . with package parasitic ................... 79

...................... ................... Admittance of circuit in figure 3.16. .... 80 Circuit of figure 3.16. with a damping resistor in series with package . . . ......................................................................... parasitic inductance 8 0

................................................... Admittance of circuit in figure 3.18. 81 ............................................... Differential VCO with feedback ratio 85

Mixing process of a noise source of frequency close to the carrier ...................................................................................... 8 7

.................................................................................. Oscillator mode1 88 Double-side band noise power density in oscillators .......................... 94

............................................................. Fully integrated 4GHz VCO 95 Equivalent circuit model for monolithic inductor used in the VCO of fig . 4.5. .......................................................................................... 95

....... CMOS VCO with tapped inductors . Tapping ratio is (l+L2)L 1 96 Reduction of phase noise in a Clapp osciilator by tapping

........................................................................................ the resonator 97 ................................................ Technique of reducing phase noise by 98

Fig . 4.10. Fig . 4.1 1 .a) Fig . 4.1 1 . b) Fig . 4.12. Fig . 4.13.

Fig . 4.14. Fig . 4.15. Fig . 4.16. Fig . 4.17. Fig . 4- 18 .

Fig . 4.19. Fig . 4.20.

Fig . 4.2 1 .

Fig . 4.22. Fig . 4.23. Fig . 4.24. Fig . 5.1. Fig . 5.2. Fig . 5.3. Fig . 5.4. Fig . 5.5. Fig . 5.6. Fig . 5.7. Fig . 5.8. Fig . 5.9. Fig . 5.10.

Fig . 5.1 1 . Fig . 5.12. Fig . 5.13. Fig . 5.14.

Fig . 5.15.a)

............................................ VCO with noise-feedback cancellation 102 ................... Simplified diagram of a Voltage Controlled Oscillator 105

................ Voltage Controiled Oscillator with damping resistor RS 105 .................................................... Schematic of the VCO with AAC 106

Sequence of pulses used to excite the oscillator; b) Block diagram of the behavioral test generator; c) VCO test points for phase sensitivity

............................................................................. to injected charge 109

Impulse shape ............................................................................ 1 10 .............................................................. Tai1 current noise spectrum 1 1 1

............................ a) VCO output wavefonn; b) Simulated function 112

..................................................................... Frequency spectrum of 113 VCO output waveform; b) Collector current of Ql; c) Simulated

................................ functions (continuous line) and (dashed line) 115

..................................................................... Frequency spectrum of 116 Phase noise (continues line) and figure of merit (dashed line) versus feedback ratio .................................... .... ........................................... 117 Cornparison of the phase noise calculated with phase noise sirnulated in SpectreRF ..................................................................................... 119

.................................................. Photograph of the VCO with AAC 120

...................................................................... VCO output spectmm 120

..................................................................... Measured phase noise 121 .......................................................... Basic block diagram of a PLL 126

Filters used in second order loops .................................................... 128 Error response of the locked loop ................................................. 130 Three-decibel bandwidth of a second-order loop ............................ 130 Bode plot of a second order loop .................................................... 132 Frequency translational loop used in radio transrnitters .................. 138

...................... Frequency translational loop with in-loop modulator 139

................................................................ Phase-frequenc y detec tor 140

.......................... ................................ Fast CMOS charge pump ... 141 Selection of PSSfund as the highest common multiple of al1

. . . . frequencies in the circuit ................................................................ 145

..................... Frequency conversion performed in Pnoise analysis .. 147 ..................................... Behavioral phase-frequenc y detector ... . . 148

................................................................. Behavioral charge pump 148

Block diagram of the Frequency Translational Loop . The onchip components are inside the dashed box ............................................. 150

......................................... Schematic of the ECL resetable flip-flop 152

Fig. 5.15.b) Fig- 5.16. Fig. S. 17. Fig. 5.18.a) Fig. S. 18.b)

Fig. 5.19.

Fig. 5.20.a)

Fig. 5.20.b)

Fig. 5.2 1.

Fig. 5.23.

Schematic of the high speed charge pump ..................... .. ............ .... 153 Schematic of the mixer and low-pass filter ................... . *............ .... 1 5 3 Schematic of the RF buffer with automatic amplitude control. ....... 154 Circuit used for the analysis of spurious products. .......................... 155 PFD convergence gain from harmonies of the IF to frequencies within the loop bandwidth; k is the order of the harmonic of IF. .............. 156 Noise contributions of the i=ll building blocks to the phase noise at the RFoutput ............................................................................. 158 Simulated output noise voltage of the PFD and charge pump. The PFD is run at an IF irequency of 3ûûMHz. ...................................... .. 1 5 9 Simulated noise figure of the mixer and buffers. The mixer is run at an LO frequency of 1.1 SGHz. LO power is - 1CkiBm. ......................... 160 Measured output spectmm. Two spurious products exist at 4ûûkHz offset from a 89 1.2MHz carrier. Here RF=89 1 -2MHz; LO=1089.2MHz; IF= 198MHz. Spurious products are at: 2 L O - 1 1 xIF=400kH~.. ................ ......... ...... .............................=400...=400.=400.. 162 Measured output phase noise level is - 120dBcIHz at 4ûûkHz offset from a 900MHz carrier. .... .. ........ .......................... . .......... ........... 163 Microphotograph of the Frequency Translational Loop. ................. 163

- xii -

LIST OF TABLES

.................................................... Table 2.1. Simulated noise figure and P ldB -54 ................. Table 2.2. Measured values for noise figure. P ldB and bandwidth 55

........................ Table 4.1. Cornparison of performance of monolithic VCO's -86 Table 4.2. Noise contributors to total phase noise .......................................... 118

................................................... Table 5.1. Cornparison of PLL performance 125

LIST OF SYMBOLS AND ACRONYMS

Total and DC quantities, such as total base-resistance R, , where R, = r, + R , and bias voltage, Vbias, are represented by uppercase syrnbols. Small-signal quantities, such as incremental change in transistor collector current i,, are represented by lower case syrnbols. A list of subscripts is also included.

SYMBOLS

= gain = voltage gain = susceptance = capacitance = collector-junction capacitance = emitter-junction capacitance = base-emitter capacitance = collector-base capacitance = frequency = unity-current gain frequency = transconductance = large-signal transconductance = smail-signal transconductance = unit impulse excess phase response = DC eIectric current = small-signai electric current = total collector current = saturation current = Boltzmann's constant = phase detector gain = VCO sensitivity = inductance = noise density = power = noise power spectral density = ~eriodic noise

- xiv -

= outband blocking power level = quality factor = electron electric charge = resistance = total base series resistance = total collecter series resistance = total emitter series resistance = smail-signal emitter resistance = small-signai base resistance = Ume = absolute temperature = loop gain; S= (a + jo)

= DC electric voltage = small-signal voltage = Earl y voltage kT = - '7

= admittance = reactance = impedance = base-ernitter impedance = emitter-collecter forward current gain = base-collector forward current gain = angular frequency = phase = total excess phase = base transit time

ACRONYMS

AAC AGC

AM DCS FM FoM FTL GSM

= automatic amplitude control = automa~ic gain control = amplitude modulation = dual-band cellular systems = frequency modulatotion = figure of ment = frequency translational loop = global system for mobile

HD2 = 2nd harmonic distortion HD3 = 3rd harmonic distortion IF = intermediate frequency IM3 = 3rd order intermodulation IM2 = 2nd order intemodulation IP3 = 3rd order intercept point LO = local oscillator PA = power amplifier PFD = phase frequency detector P U = phase Iocked loops PM = phase modulatotion PSS = periodic steady-state PTAT = proportional to absolute tempera- PI dB = I dB compression point R F =radiofrequency RFC = radio frequency coi1 nns = rmt-mean-square SSB = single-side band VCNR = voltage controlled negative resistance VCO = voltage controlled oscillator

Subscripts

= B JT' s base

= BJT's collector = collector-base = collector-substrate = BR'S emitter = effective = equivalent = forward = gate = input = load = modulation = maximum

- xvi -

min = rninimurn n, N = noise O, out = output opt =optimum osc = oscillation

P = parasitic P = phase R = reverse Sui? = substrate T = unity gain v , V =voltage

- xvii -

CHAPTER 1: INTRODUCTlON

CHAPTER 1

INTRODUCTION

The recent advances in microelectronics have led to remarkable developments in

the area of monolithic circuits for communications. htegrated circuits for such applica-

tions as wireless or fiber optic communications not only achieve ever higher operating fre-

quencies, but also accomplish increased Ievels of integration. Bipolar processes with fT's

of around 25 GHz, that were available in the Iast 2-3 years, ailowed for medium to large-

scaie integration Ievels of the radio circuits.

The system in fig. 1.1 represents a transceiver for wireless applications. The com-

ponents inside the dashed box are integrated on one chip. It can be seen that the down-con-

verter and the frequency synthesizer are the only components that are not integrated

together with the transceiver. However, there are more recent BiCMOS processes that

allow a complete integration of systems like the one in Fig. 1.1 [l. 11, [1.2].

The wireless transceiver in fig. 1.1 performs the functions of receiving and trans-

mitting a modulated carrier in different tirne slots. For the cellular GSM (Global System

for Mobile) standard, the frequency bands are: 89ûMHz-9 15- for the uansmitter and

935MHz-960MHz for the receiver. Each of these bands contains multiple communication

channels of 2ûûkHz bandwidth. The UHF synthesizer performs the channel selection by

providing the UHF frequency to the receiver or the transrnitter in increments of 200kHz.

The VHF synthesizer provides IF frequencies to the receiver or transrnitter. The IF fre-

quencies have fixed values for the receiver and transmitter.

The specifications of a wireless standard, like GSM, pose stringent requirements on

the transceiver building blocks. In the receiver chah , the low-noise amplifier (LNA) must

have a noise figure of around 2dB and input PldB (lm compression point) of around -

1

CHAPTER 1: INTRODUCTION

20dBm. The variable gain IF amplifier rnust have a noise figure of less than 7dB and a

variable gain range of at least 40dB. Design pnnciples for low noise and low distortion in

RF circuits wili be discussed in chapter 2 of this work and they will be applied to a vari-

able-gain IF amplifier.

In the transmitter chah, there are stringent requirements on the phase noise level at

the frequency translational loop (FIL) output. Thus, the phase noise level must be lower

than - 120dBc/Hz at 400kHz and lower than - 162dBdHz at 20MHz offset from a 900MHz

carrier. At the same time, there are strict requirements on the spectral purity of the trans-

mitter. For example, the spurious products at the FTL output need to be lower than -63dBc.

LNA

I

SAW ' IF BASE-BAND , RLTEU 1 AMP AMP

1 FREQUENCY TRANSLATIONAL LOOP

L - - - - - - - - - - - - - - - - - - - - - - - J

Fig. 1.1. Block diagram of a transceiver used in wireless communications.

Goals of the research

Am Conv.

DSP UP

DIA Conv.

The purpose of this work is to develop circuit techniques with improved perfor- 2

CHAPTER 1: INTRODUCTION

mance for key building blocks used in communications. Such building blocks were iden-

tified in the above presentation to be: low noise, low distortion amplifiers, voltage-

controlled oscillators and PLL's.

The development of novel circuit techniques for low noise and low distortion

amplifiers, including a detailed noise and distortion analysis of high frequency circuits, is

presented in chapter 2. A novel high frequency distortion analysis for the common ernitter

and differential pair configurations is developed by using Volterra series. The results of

this analysis provide a deeper understanding of distortion mechanisms in circuits operated

at high frequencies and are, therefore, used as generai design guidelines in ail subsequent

chapters of this work. A novel design for a low noise and low distortion amplifier with

adjustable gain is implemented in the last part of chapter 2.

The design principles for voltage controlled oscillators used in communications are

explored in chapter 3. Novel LC oscillator techniques that are suitable for monolithic

implementations are investigated in order to identify the trade-off between important fea-

tures such as: power consumption, frequency stability, reliable start-up and noise perfor-

mance. A small-signal analysis of oscillator start-up is developed in this chapter that is

used in predicting the initial circuit behavior, especially when multiple resonances are

present. This analysis is particularly useful in the design of monolithic LC oscillators,

where the package parasitic element values are of the same order of magnitude as the ele-

ments in the resonator, such that multiple resonances are always present.

Chapter 4 focuses on the phase noise performance of monolithic voltage controlled

oscillators. Novel oscillator topologies that are specifically optimized for low phase noise

are explored. A monolithic LC oscillator that presents outstanding performance in terms of

phase noise level and power consumption is implemented during this work. At the sarne

time, a novel analysis technique which allows the optimization of phase noise for the

implemented oscillator is developed. This analysis technique takes the oscillator nonlin-

earities into account and it enables an optimization based on the noise characteristics of the

active devices during a complete limit cycle. It will be demonstrated in the analysis that

noise contributions from the active devices are more important than the contributions from

time invariant elements represented by the resonator, therefore a linear noise analysis is not

suitable in this situation.

Phase locked loops with specific applications in radio transceivers are explored in

chapter 5. A novel phase locked topology is used in this chapter in order to irnplement a

frequency translational loop (FTL) with application in radio transrnitters. The design

guidelines for low phase noise voltage controlled oscillators developed in chapter 4 find

application in the design of the low phase noise frequency translational loop. Also, a new

analysis method is developed in this work and used in order to improve the spectral punty

of the circuit. This analysis provides an accurate characterization of the mechanisms that

generate spurious products in the present design. Moreover, the method can be applied in

general to any FIZ topology.

The development of novel circuit techniques for communications is achieved

throughout the present work by not only employing new designs, but also by creating new

analysis methods for these circuits; methods that provide a better characterization than the

one usudly available in classic SPICE-type simulators.

REFERENCES

[ 1.1 ] 035 BiCMOS Process Description, Memorandum, Conexant S ystems, 1998.

[1.2] Design Rules for BiCMOS Process, Notes, Temic Inc., 1997.

C-R 2: LOW NOISE, LOW DISTORTION ...

CHAPTER 2

LOW NOISE, LOW DISTORTION AMPLIFIERS FOR RADIO

FREQUENCY APPLICATIONS

2.1. INTRODUCTION

The design principles for low noise and low distortion amplifiers are presently

revisited in a general effort to develop highiy integrated components for modem commu-

nications. Such integrated components include low noise amplifiers (LNA's), mixers, IF

amplifien, voltagecontrolled oscillators (VCO's), components which are required to

deliver the highest performance in terms of noise and distortion levels with minimum

power consumption.

The originality of the work in this chapter consists in the development of a novel,

elaborate noise mode1 for high frequency BJT's. Another area of originality consists in the

design and implementation of an adjustable gain IF amplifier that is part of a monolithic

transceiver for wireless applications. This implementation was perforrned using the design

principles for low noise and low distortion, including high frequency distortion analysis

with Volterra series that are presented here. The design and resuits from it are reported in

literature [2.1].

The results obtained in this work both for noise and distortion are of general interest

in the design of RF analog circuits, and they will be used in al1 subsequent chapters.

2.2 REVIEW OF LITERATURE ON LOW NOISE AMPLIFIERS.

The design principles of low noise amplifiers for radio frequencies have been

developed over the past decades and there are several books that can be used as reference in

C m R 2: LOW NOISE, LOW DISTORTION ...

this area [2.2], [2.3]. However, the recent advances in rnicroelectronic technologies have

stimulated a tremendous effort in the development of new circuit techniques that are spe-

cific to the integrated circuit design with applications in the radio frequency range. Low

noise amplifiers (LNAs) were available only in discrete implementations using GaAs tran-

sistors in the past decade. In the last four to five years, integrated LNAs together with

down-convercer mixers have appeared in bipolar technologies and more recently in CMOS

technologies. Fig. 2.1 presents the trend in terms of maximum frequency for different tech-

nologies [2.4]. From this trend it can be inferred that GaAs technologies continue to find

applications in the highest frequency range and for the highest prices; the bipolar technol-

ogies, such as silicon and SiGe, find applications in the mid-frequency range and for more

reasonable prices; CMOS technologies are used in the lower frequency range and large

integration scale, but are rapidly expanding into applications that seemed to be reserved to

bipolar or even Ga& technologies.

However, with the rapid advances in technologies, there are already designs which

integrate on a large scale complete transceivers [2.4], [2.5], and people already envision the

"Single-Chip Radio", that integrates the front-end, the transceiver. the ND and DIA con-

verters and possibly even the DSP processor [2.6].

A Cut-off / frcquency

GaAs

- BJT CMOS

/ 4 / /

4

1 r * 1985 1990 1995 2000 year

Fig. 2.1. Evolution of microelectronic technologies for high Frequency applications. 6

C w R 2: LOW NOISE, LOW DISTORTION ...

2.3 DESIGN OF LOW NOISE AMPLIFIERS.

2.3.1 Noise Mode1 of the B JT at High Frequency.

A smd-signal model for the BJT operated at high frequency will be derived in this

section. This a.c. model provides the analog designer the accuracy required for high fre-

quency applications, while stitl maintainhg the circuit complexity at the level where basic

understanding can be achieved without computer simulations. From this perspective, it is

desirable in analog design that computer simulations be used for refinement of a design

which is already functional. The accuracy of this high frequency transistor model resides

in the fact that both the collecter-base capacitance and the emitter resistance are accounted

for.

Miller Eflecr with Emitter Degeneration.

The goal is to find an equivalent impedance for the C,, capacitor of the BJT model,

when there is emitter degeneration. This equivalent impedance has to be placed across 2,.

In order to derive the expression of the equivalent impedance, Z,, the following set of

equations can be wntten for the transistor model in fig. 2.2

Fig. 2.2. BJT with emitter degeneration (small-signal model).

7

C w R 2: LOW NOISE. LOW DISTORTION ...

By introducing equations (2.2) and (2.3) into (2.1) it follows chat:

Therefore, 2, will be written:

Usually the C,Rc time constant will give a zero at frequencies well above the tran-

sistor cut-off frequency. As an example, for transistor mode1 NN5211 lx the following

parameters are provided by CMC: R, = 77.7R, C, = 21 fF,

Equation (2.5) becomes

v1 - 1

z m = ~ - [l + (gm + &)R. + g r n ~ J s - cP

Equation (2.6) needs to be discussed for low frequencies and for high frequencies.

For low frequencies, equation (2.6) is simply

In the low frequency range, the equivalent impedance is a capacitar having the

value

Cm = [ l + g m ( R e + R c ) I - C p - (2.8)

CHAPTER 2: LOW NOISE, LOW DISTORTION ...

At this point it is worth noting that Cm calculated above gives a well-known equiv-

alent capacitance when referred at the input of the emitter degenerated transistor. Indeed,

any capacitance across r, will be equivalent to the following capacitance connected

between base and ground

Therefore Cm of equation (2.8) wiH have the following equivalent, which is the well

known Miller relationship

For high frequencies, equation (2.6) becomes

The transfer function in equation (2.1 1) has two poles: one pole is given by CI,, the l , equation (2.1 1) becomes second by 2,. For frequencies higher than f > f, = C,R,

It is worth noting that usually equation (2.12) is valid for frequencies starting two

decades before the transistor cut-off frequency, depending on the quiescent current Ic. For

example, for transistor mode1 NN52111x biased at 1mA: f, = 12CH.z. C, = 454fF ,

r , = 2.675k, f, = 130MHz.

The problem now is to find the impedance which satisfies equation (2.12). Let us

C w R 2: LOW NOISE. LOW DISTORTION ...

consider the network in fig. 2.3 which has the impedance

Fig. 2.3. RC network equivaîent to 2,.

For SC R« 1, Z becomes

Z = 1

SC, + sC2 + s2C, C2R

In equation (2.12), for C, = Ci, + g,sF = g,rF, the following simplification can be done

Equation (2.15) can further be manipulated as follows,

The components corresponding to the network of fig. 2.3 are

C-R 2: LOW NOISE. LOW DISTORTION ...

Thus, the BJT model for high frequency is given in fig. 2.4

Fig. 2.4. BJT high frequency mode1. Z, is of the type given in fig. 2.3.

I< is worth noting that the only restriction imposed is that C, = gm.rF. This implies

that the bias cunent must be large enough so that Ci, « Cs = gmsF . For completeness, the 1

assumption that - ,, o for frequencies up to f, is checked. This assumption was used in RCl

equation (2.14). Indeed

High Frequency Noise Model for the Bipolar Junction Transistor.

The model generally used for calculating the noise figure of the bipolar transistor is

a T-mode1 denved from the cornmon ï ï -model. The T-mode1 was used in the early papers

of Nielsen [2.7]. Hawkins [2.8] to derive expressions for the noise figure, optimum source

impedance and noise resistance of the BJT [2.9], [2.18].

In the following section, the T-mode1 will be derived starting from the il -mode1

and the results of previous section. The ïI -mode1 with Miller effect is given in fig. 2.5 and

C w R 2: LOW NOISE, LOW DISTORTION ..,

is derived from the calculations of previous section.

(Re + R,) Fig. 2.5. n -mode1 used to derive the BfT T-model. m = Cp

=f

In order to obtain the T-model, the voltage-controlled current source is routed from

collecter to base and from base to emitter as in fig. 2.6. The final T-mode1 is given in fig.

2.6b). This mode1 is easier to use in high frequency modeling because it decouples the

input port from the output port, while still accounting for the collector-base capacitance.

Thus. it is usefid in deriving the S-parameters of the device. In this work, the T-mode1 will

be used for calculating the noise figure of the BJT. The intrinsic noise sources of the bipo-

lar transistor are considered in fig. 2 .6~) . The following set of equations c m be written for

the mode1 in fig. 2 . 6 ~ )

CHAP'ïER 2: LOW NOISE, LOW DISTORTION ...

Fig. 2.6. a)T-Mode1 of the BJT obtained from the n -Model. b) -Mode1 with eqsivalent resistor .\

re = 1 /g, = r,/P ; 1, = g, VI .

Fig. 2.6. c) T-Mode1 of the BJT with the intrinsic noise sources:

c: = 4kTRs(An source resistance thermal noise 2

eb = 4kTRB(AB base resistance thermal noise

C w R 2: LOW NOISE, LOW DISTORTION ..-

2 eE = 4kTRe(An emitter resistance thermal noise

e f = 2 kTre(Aj) ernitter shot noise .2 T 2 1 = 2 k - ( a o - [a] )(AB collecter shot noise CP

From the set of equations (2.18)-(2.2 1) an expression for the output current i, is

denved

w here Zs=R,+jXs and 1

N = -{[i - a + j o ( C , , + ( I +m)C, ) re ] (Zs+ Rb) + r e + [ l + j o ( C p + ( l +m)C,)r , ]R, } a

The BJT noise figure is defined as the total noise at the output divided by the output

noise due to the source resistance ody. The output noise due to the source resistance only,

90 * is given by equation (2.22) if eb = eE = e , = O and i,,, = 0 .

Thus, the BJT noise figure is

Equation (2.23) is used to denve expressions for the optimum source reactance and

14


optimum source resistance. The optimum source reactance XSop, is obtained by solving dF

the equation: - = O . Thus Xsopr becornes d*s

The optimum source resistance is calculated by solving the equation: - and Rsop, becornes

By introducing equations (2.24) and (2.25) into equation (2.23). the minimum noise

figure is calculated to be

The set of equations (2.23)-(2.26) agrees with previous results ([2.7], [2.8]) if Re

and CI, are neglected. The importance of the present work is that it considers a more

refined model of the BJT when cornpared to the earlier results. Thus, the emitter resistance

is taken into account and the effect of C , is considered by finding a high frequency Miller

equivalent of this capacitance.

Simulation Results for the Bipolar Junction Transistor.

The analytic expressions of the previous section are used to simulate the high fre-

quency noise characteristics of a bipolar transistor. The transistor model used for simula-

tions was NN52 1 1 lx of the Canadian Microelectronic Corporation having the following


parameters:

Rb = 261 Re = 12 R, = 77.7 BF = 103

Cj, = 15 10-l5 V - = 0.8 M I E = 0.267 7'''' = 1.1 - 10-11 Je

cjc = 21 - 10-l5 V. = 0.71 M J C = 0.397 . JC

In fig. 2.7, it can be seen that the noise figure starts increasing forfilGHz This is

due to the fact tbat the transistor gain drops at this frequency. This result is in good agree-

ment with previous results I2.81. However, by including CI, in the model, the noise figure

is higher by 0.5dB to 1dB above 2GHz. when compared with predictions without CI,.

Fig. 2.7. Noise figure vs. frequency with CI, = O (solid line) and Cp = 21 fF (dashed Iine).

The noise figure as a function of the source reactance is plotted in fig. 2.8. As

expected, the noise figure is minimum for a value of the source reactance as predicted in

equation (2.24). As can be seen in fig. 2.9, the noise figure is minimum for a value of the

source resistance given by equation (2.25).

C w i t 2: LOW NOISE, LOW DISTORTïON .-.

Fig. 2.8. Noise figure vs. source reactance forelGHz and I,=lmA.

Rs [ohml

Fig. 2.9. Noise figure vs. source resistance for filGHz and I,=lmA.


The noise figure vs. bias current is plotted in fig. 2. 10. It can be seen that there is

an optimum value of the bias current for which the noise figure is minimum. Indeed, for

low cwents, the dominant term of the noise figure is r, , which drops with the increasing

current, and for high current the dominant term is C,, which goes up as the current

increases.

Fig. 2.10. Noise figure vs. bias current at fi 1 GHz.

The optimum source reactance vs. frequency is plotted in fig. 2.1 1. X,,, is always

positive, meaning that the source reactance must be inductive. This can be more clearly

seen when considering [al2 = a. , so that equation (2.24) c m be approximated by

The above relationship expresses the fact that the optimum source reactance

cancel out the capacitive reactance seen at the transistor input.

18

must


Fig. 2.1 1 . Optimum source reactance vs. frequency at I,=lmA.

Fig. 2.12 represents the optimum source resistance vs. frequency. For low frequen-

cies this value is hi h, as the dominant term in equation (2.25) is re [ 2 ( R b + Re) + re f 2(Rb + R,) + re - -

+ r n ) ~ ~ ] ~ 0 2 - r e - [ c l i + ( l + m ) ~ ~ ] ~ - 1--

For high frequencies that are close to the transistor's cut-off frequency, the domi-

nant term in equation (2.25) becomes RSop, = Rb + R E . This means that for these frequen-

cies, Rb + RE gives the value of the optimum source resistance, so in a 50R system one

should choose Rb + RE = 50C2. thus obtaining both minimum noise figure and matching

input impedance.

The SPICE file used for these simulations and the transistor mode1 are provided in

appendix A.

C)IAPTER 2: LOW NOISE. LOW DISTORTION ...

Fig. 2.12. Optimum source resistance vs. frequency at I,=lmA.

2.3.2 Ftont-end Matching for Low Noise Amplifiers

It can be shown that inductive degeneration provides a positive real part to the

input impedance of a bipoiar amplifier. More generally, an arbitrary ernitter (or source for

the case of a MOS amplifier) degeneration impedance Z is modified by a factor equal to

[pua) + 1 ] when reflected to the base (gate) circuit, where Pua) is the high frequency

current gain

For the generai case [2.10]


Hence, the input impedance is that of a series RLC network, with a resistive term that is

directly proportional to the inductance value.

From equation (2.28) it c m be seen that capacitive degeneration contributes a neg-

ative resistance to the input impedance. Hence, any emitter-to-substrate capacitance off-

sets the positive resistance from inductive degeneration. Tt is important to take this effect

into account in any actual design. If inductive degeneration is used, this contributes a pos-

itive resistive part to the input impedance. Whatever the value of this resistive term, it does

not bring with it the thermal noise of an ordinary resistor because a pure reactance is noise-

less. Therefore, this property is used to provide a specified input impedance without

degrading the noise performance of the amplifier.

Equation (2.28) shows that the input impedance is purely resistive at only one fre-

quency, at resonance. However, this method provides a narrow-band impedance match.

Fortunately, there are numerous instances when narrow-band operation is desirable, so

inductive degeneration is a valuable technique. Therefore, the topology of Fig. 2.13 will

be examined next. The inductance Le is chosen to provide the desired input resistance

equal to the source resistance. Since the input impedance is purely resistive only at reso-

nance, inductance Lb is needed to resonate out the input capacitance Ci,. At resonance, the

base-emitter voltage is Q times as large as the input voltage. This statement is based on the

observation that for frequencies o * COjdB, the baseernitter impedance is dorninated by

C,. This treatment is equally valid for a MOS amplifier, where the input impedance is

basically capacitive, it is C,,. The overall transconductance G, is therefore

gm 1 where aT = -. ' i n

C m R 2: LOW NOISE, LOW DISTORnON ...

It should be emphasized that the overall transconductance is independent of the

device's transconductance. This result is the consequence of two competing effects that

cancel precisely. To iliustrate thïs, we consider the situation where the transistor bias cur-

rent is reduced, hence gml is reduced proportionally. However, the input capacitance

would also shrink by the same factor, since Ch = Ci, + g, tfz g, - tf . and the induc-

tances would have to increase by the same factor to maintain resonance. Since the ratio of

inductance to capacitance increases, the Q of the input network must increase. The

increase in Q cancels precisely the reduction in device transconductance, so that the overall

transconductance remains unchanged.

Fig. 2.13. Input matching network for low noise amplifier.

The optimum source resistance value for minimum noise figure was previously cal-

culated in equation (2.25). It is ofien difficult to arrange al1 design parameters such that

this optimum source resistance value is the sarne as the system source resistance, which is

usually 50R . Equation (2.25) shows that the optimum source resistance is detennined by

the transistor's base resistance, rb, transconductance, g,, and current gain, Pua) , at the

frequency of interest. There are certainly several degrees of freedom in optimizing the

value of Rsopr One is the choice of device size such as to provide a desired value for rb.

Limitations here are given by parasitic capacitances, Ccb, Ces, which increase with increas-

ing device's size. Another degree of fieedom is the choice of biasing current that ailows

optirnization of the cut-off f ~ q u e n c y or. The dependence of device's cut-off frequency


on biasing current is depicted in fig. 2.14. In a good design, the biasing current is chosen

such that the operating cut-off frequency is about 10% to 20% lower than the peak cut-off

frequency. However, the choice of biasing current is limited by the desired power gain of

the amplifier, as well as by the value of the optimum transconductance for minimum noise

figure.

operating rcgion Kirk

f effect

Fig. 2.14. Cut-off frequency fT versus bias current in a bipolar transistor. The operation region is

chosen to be 10%-20% lower than peak fT.

In the process of optirnizing the amplifier overall performance, one should first pro-

vide proper power matching. This is of great concern, since a poor match will decrease the

amplifier power gain and this effect will cause an increase in the overall noise figure of the

system. The effect is especially tnte when the low noise amplifier drives a down-converter

mixer with much poorer noise performance.

It is often difficult to design the amplifier such that the optimum source resistance

for minimum noise figure is equal to the resistance requïred for power matching. However,

we can make the observation that the value of the noise figure will increase insignificantly

from its minimum value if the amplifier's equivalent input noise resistance, Rn, has a low

value with respect to the actual source resistance. Indeed, the noise figure expression can

be written as


and in the usual case where the reactive part is resonated out, equation (2.30) can be written

The equivaient input noise resistance for a bipolar transistor is given by

Equation (2.32) shows that the actuai noise figure value will present insignificant degrada-

tion from its minimum value if the base resistance is low and the transistor is biased at

fairly high collector currents.

2.4 DESIGN FOR LOW DISTORTiON

2.4.1 Conventional Distortion Analysis

An important aspect in the design of low noise, linear amplifiers for communica-

tions is the arnount of distortion introduced by these circuits. There are several conven-

tional methods used to quant i5 the distortion behavior of a circuit. While the most

cornmon description of distortion in audio frequency applications is the total harmonic dis-

tortion (THD), the concepts used in high frequency communication circuits are the P ldB

(1dB compression point), IP3 (third order intercept point) and IP2 (second order intercept

point). These concepts are used to describe the dynamic range and the spurious free

dynamic range of the circuit 12.1 11.

A conventional distortion anaiysis as used in the mid-frequencies range, where the

CH-R 2: LOW NOISE, LOW DISTORTION .-.

parasitic energy storage elements can be neglected, wiil be presented. In this case the non-

linearities generating distortion are assumed to be resistive. A power series can be derived

for the circuit's transfer fûnction.

Suppose that a circuit has the transfer function of fig. 2.15. Then, the output signal

can be expressed as a fûnction of the input signai as follows

S, = a l ~ , - + a z ~ : + a 3 ~ : + ... (2-33)

where coefficients ai's are constants.

c s i Subtnct bias

Fig. 2.15. Nonlinear transfer function bat lends itself to a power series expansion.

Using the power series of equation (2.33). an analysis of intermodulation products

c m be performed. Intermodulation occun when two or more harmonic waves are applied

to a circuit. Usually, the third order intermodulation product is of interest in communica-

tion systerns. To explain this, we can consider that the desired signal is of frequency o,

and that there is an unwanted signal of frequency a2, which is close to o, . It will be dem-

onstrated shortly that there are intermodulation products at frequencies 2w2 - al = o, and

2 0 , - a2 = 0, . These products are a major source of distortion in radio receivers.

Let the input signal be

Si = S I - cos (O, t) + S* - cos (o*t)


If expression (2.34) is introduced in equation (2.33), the third order intermodulation

product can be calculated. Thus, the power series expansion contains the following cubic

terms

Equation (2.35) contains third order intermodulation terms which appear at

202 - al and 2w1 - oz. IM3 is defmed as the ratio between the amplitude of the third

order intermodulation terms and the amplitude of the fundamental. For SI=$ in equation

(2.34), IM3 referred to the input yields C2.123

When referred to the output signal, IM3 becomes

Following a similar denvation for the cubic terms containing the frequencies 3 0

and 3 0 9 , the third harmonic is calculated to be

By comparing equations (2.37) and (2.38) it can be seen that IM3 is three times as large as

HD3, or expressed in decibels: IM3(dB)=Hm(dB)+9.5dB.


The third order intercept point, IP3, represents the theoreticai input level for which

the level of the third order intermodulation product is equal to the level of the fùndamental.

IP3 can be obtained from equation (2.37), by setting IM3=1

The calculated level for IP3 is theoretical only, and it is obtained by extrapolating

the value for IM3 assessed at low distortion levels. For high distortion levels, as would be

the case where IP3 occurs, there would be higher order terms in the power senes that would

mix and contribute to IM3. In that situation, equation (2.37) is not vd id anymore. In real

applications, IP3 is used to characterize the circuit's linearity, but it is understood that the

input signal will never be equal to IP3.

IM2 is defined as the ratio between the amplitude of the second order intermodula-

<ion terms and the amplitude of the fundamental. For the calculation of fM2. the following

quadratic terms are considered

a2s f = o*(S, - cos (a1 t ) + S2 cos ( 0 2 t ) ) 2

a2s? = ... + O ~ - S ~ S ~ [ C O S ( C O ~ - W ~ ) ~ + c o s ( ~ ~ + ~ ~ ) t j -

For SI=S2 in equation (2.34), IM2 referred to the input yields

When referred to the output signal IM2 becomes

C m R 2: LOW NOISE. LOW DISTORTION ...

A similar calculation is carried out in order to determine the second order distor-

tion. HD2, by considering the ternis of frequencies 2 0 , and 202. The expression for HD2

is

It can be seen that 1M2 is twice as large as HD2, or expressed in decibels:

IM2(dB)=HDZ(dB)+tSdB.

The nonlinearities studied so far imply the presence of two tones. The gain com-

pression of a circuit due to its nonlinearities is characterized using a single tone analysis.

The input signal level that causes IdB drop in gain from the small-signal gain is defined as

PldB (IdB compression point). A single tone is applied to the input in order to quantify the

gain compression

Si = S , - cos(o,r) . (2.44)

When expression (2.44) is inserted in equation (2.33). the output yields

Equation (2.45) shows that the cubic term contributes to the fundamental frequency

a, . Thus, the apparent gain is

5 alS1 + 4 a 3 ~ :

Gain = 3a3 = '(1 + P-$). 1

CHAPTER 2: LOW NOISE. LOW DISTORTION ...

This represents a gain reduction from the small signal gain, since the coefficient a3

is negative in real circuit implementations. The input signal for 1dB compression occurs

for

From equation (2.47) the input signal yields

The numerical relation between PldB and IP3 can be calculated from equations

(2.39) and (2.48) to be PldB(dB)=IP3(dB)-9.6dB 12.1 21.

A topic of interest in radio receivers refers to "outband blockers". This represent

large interfering signais that cause compression in the gain of the amplifier, even when the

desired signal is smail 12.131. The outband blocking level (Poe) is defined as the strength

of the interfering signai (in dBm) that causes 3dB drop in gain for a smail desired signal. In

order to study the effect of outband blockers, the input signal is assumed to be

Si = S , c o s ( o l t ) + S2cos(02t) , where SI is the small desired signal and S2 is the large

blocker. The above expression is inserted into equation (2.33) and the following expres-

sion for the output signal is obtained

Thus. the apparent gain of the desired signal at o, is reduced

3 a l S I + Z n j ~ j ~ $

Gain = S.


The outband blocking POB is calculated from 201og 1 + - - ~ f = -3dB , which yields [ ::: 1

The numencal relationships between Pm, IP3 and PldB can be calculated from equations

(2.39), (2.48) and (2.5 1 ): PoB(dB)= IP3(dB)-8.3dB and P d d B ) = PldB(dB)+ l dB.

Eflect of feedback on distortion

The distortion analysis presented so far concerns the effects of nonlinearities on

unidirectional circuits. It is of great interest to study the influence of feedback on anodin-

ear circuit.

The amplifier in fig. 2.16 is considered to be nonlinear, while the feedback network

is linear- The following equations c m be written for this circuit

Su = o p , + a& + a& + -.. (2.52)

SE = Si- fSo (2.53)

Fig. 2.16. Effect of feedback on distortion.

By inserting equation (2.53) in equation (2.52), the following expression for the

output signal is obtained

So = a,(Si-fS,) + O ~ ( S ~ - ~ S , ) ~ + ~ ~ ( S ~ - ~ S ~ ) ~ + ... (2.54)

30


Equation (2.54) has the general f o m

S, = b , ~ ~ + b ~ ~ f + b j s ? + ...

Coefficients bi are calculated by equating the powers of Sr of equations (2.54) and (2.55).

Thus, the following forms for b,, b2 and b3 are obtained

Equation (2.56) shows that b,, representing the small signal gain of the circuit with

feedback, is the small-signal gain of the amplifier divided by the loop gain at the frequency

of operation. Equation (2.57) shows that the effect of feedback is to reduce the second

order term in the power series by the cube of the loop gain. Equation (2.58) shows that: a)

the third order term is strongly attenuated by the fifth power of the loop gain; b) it is possi-

ble to cancel the third order term via the second order interaction represented by 2a: f .

The amount of harmonic distortion and intermodulation of a feedback system can

be evaluated based on the expressions for coefficients bi. For example, H D 2 for a given

input signal is

Similarly, IM2 is twice as large as HD2 for the same input signal levels.

CHAPTER 2: LOW NOISE, LOW D~STORT~ON ...

B JT nonlinear characteristics

The results obtained previously on distortion of nonlinear circuits are applied to

basic bipolar circuits in order to derive specific results for this circuits.

Distortion of the commonemitter stage is carried out for the configuration in fig.

2.17. The total collector cwrent is

where IA represents the bias current.

Fig. 2-17. Distonion in common-emitter BJT.

The series expansion of equation (2.60) yields

The coefficients

HD2 level is

ai are identified: a, = ( q i A ) / ( k T ) (small signal transconduc-

- ( 1 . Hence, for an ideal voltage dnven BJT, the a 3 - g k T A


As an example, if the collector peak current is 40% of the bias current, then HD2=10%.

IM3 is defined relative to the input voltage drive, vi, and it is

The BJT distortion analysis is extended by considering the emitter degeneration

resistor RE and finite source resistance RS. For this case, the following equation is valid

V i + VBIAS = VBE + lCRE = VBEQ + V B E + lBIASRE + iCRE - (2-64)

The bias portion of the input voltage is VBIAs = VBEp + ISIASRE . By subtracting the bias

from the total voltage, the signal voltage yields

vi = V B E + iCRE. (2.65)

In this configuration, RE is identified as negative feedback network and the other

entities of the circuit are identified as follows: Sc - V B E , Si = vi , So = i C , f = R E . The

BJT itself is the forward path and the power series can be written as

The power series for the ciosed loop system is

ic = b l v i + b z v f + b 3 v j + . . .

Now, the harmonic distortion levels can be calculated as foliows


An interesting design opportunîty is offered by equation (2.69): HD3 (as well as

l . The above analysis can now be extended by consid- IM3) c m be cancelled for RE = - 2gm

enng a finite source resistance Rs as depicted in fig. 2.18.

Fig. 2.18. Distortion analysis on BJT with finite source resistance.

The following equation is valid for this case

V i + Vms = VBE + lERE + IBRB .

Since this analysis is cmied out for the mid-frequencies range, where P = l , / l B

is assumed constant, equation (2.70) can be wntten

Equation (2.7 1) is similar with equation (2.64) if RE is replaced with RE + R B / $ .

Hence, the above analysis is aiso valid for the case with finite source resistance. For the

cornmon-emitter configuration, the effect of emitter degeneration and increased source

resistance is to improve the linearity of the stage. A useful design formula to be remem-

bered is the level of IM3 generated by the undegenerated BJT and by the BJT with emitter

degeneration and finite source resistance. From equation (2.63), the IM3 level of an unde- 2

while the IM3 level for a BJT with emitter degeneration generated BJTis IM3

and finite source resistance (RE8 = RE + R B / b ) is

Distorrion in BJT di'ereential pair

The following set of equations are valid for the differential pair of fig. 2.19

Fig. 2.19. Distortion in BJT differential pair.

By combining equations (2.73) and (2.74) and expanding the power series of the

exponential, the collector current of Ql yields

The signal collector current of QI is given by

1 ~ * E E By inspection, the coefficients a , , a2 and a, are a , - -- - 4 k T ' a2 = 0 ,

a = $(&)131EE . With theu coefficients, the IM2 equals zero, and IM3 for the unde-

generated differential pair becomes [2.12]

It is interesting to note that the IM3 level produced by the undegenerated differen-

Ual pair is hdf the IM3 level of the single BIT. This is due to the fact chat the same input

signal is developed across two base-emitter junctions in the case of the differential input,

and the amount of distonion is therefore reduced by half.

For the case of the degenerated differential pair, the following equations can be

written

Vi = "BEI - V ~ ~ ~ + l c ~ R ~ - l ~ ~ R ~ (2.78)

I C I -Ic2 = ZC,. (2.79)

Thus, equation (2.78) becomes

V; = VBEl - VBEI + 2iCl RE.

The distortion analysis on feedback circuits can be applied to equation (2.80), if the

circuit entities are properly identified: SE = VBEI - VBE2, Si = vi , So = iCl and

f = 2 R , .


The power series for the direct path without feedback is

iCl = a1sE+a2s~+a3s:+ ...

1 ~ I E E 3 where a , = ;F , a2 = 0 . a3 = '(A) 48 kT IEE.

The power series for the feedback circuit

i,, = bls i+b3s?

w here

The distortion levels for the degenerated differential pair can now be calculated.

Thus, IM2 is zero and IM3 is given by

It is interesting to compare the degenerated differential pair with the degenerated

single ended stage, where both are biased at the same current, Le. IEE in fig. 2.19 equals IA

in fig. 2.18. For large degeneration, the IM3 level of the single ended stage given in equa-

tion (2.72) becomes

CHAPTER 2: Low NOISE. LOW DISTORTION ...

For large degeneration, the IM3 of the differential pair becomes

It can be seen bat, for large degeneration, the IM3 level of the differential pair is

twice as large as the IM3 for the single ended stage biased at the same current.

2.4.2 High Frequency Distortion Analysis Using Volterra Series

The distortion analysis presented in the previous sub-section has limitations at high

frequencies, where parasitic inductances and capacitances become important circuit ele-

ments. The distortion analysis at high frequencies uses Volterra series, which uses com-

plex variables in the form of magnitude and phase, and thus provides a description for

circuit elements with memory.

The block diagram of fig. 2.20 is used to exemplify the use of Volterra series for

high frequency distortion analysis. The following equation is valid for S,

The transfer function is a linear complex function of the form

X u w ) = IX(jw)lexpj@ . (2.90)

If the input signal is of the form Si = S I cos(o, t ) + S2cos(ott) , then the output is

of the form

The short hand notation used for Volterra series of the form in equation (2.91) is

Sm = a , X(jo,)oSi + a2~( j0 , , job)os? + a3x(ja,, job. j a , ) o ~ ! + . - . - (2 .92)

where Si is the input signal in time domain and operator o means that each frequency com-

ponent in S r is multiplied by IX(ja,, job, ...)( and phase-shifted by the phase of

X(~O,, job, . . . ) .

/ Resistive

/ Linear frequency

nonlinearity dependent circuit

Fig. 2.20. BIock diagram used for illustration of Volterra series expansion.

The high frequency nonlinearities in the cornrnon emitter stage and the differen-

tial pair stage will be analyzed using Volterra series. The similarities with the results

obtained by conventional distortion analysis will become apparent, but some interesting

high frequency effects will be revealed. Thus, the effect of emitter inductive and capacitive

degeneration will be pointed out, and the high frequency intermodulation products will be

quantified.

The single ended stage with emitter degeneration 2, and source impedance Zb of

CHAPTER 2: Law NOISE, LOW DISTORTION ...

fig. 2.2 1 is first considered.

Fig. 2.21. Mode1 used for high frequency distortion analysis in single ended stage.

The following equation is valid for this configuration [2.14]

where ic is the collector signal current (collector current minus bias current) and iB is the d Q ~ dic displacement current through Cg given by iB = - dt = T~;IS . Thus

ig (s) = s T~ - ic(s) . (2.94)

The collector signal current is given by

i, = I, - IQ = I .[ exp ) - - ] = 1 ) + 2 [ V, + [ + . . ] , (2.95) VT

where v ~ k T / q .

Thus, equation (2.93) becomes


Equation (2.96) has the form

vS = a , v X + a t v ~ + a 3 v + + ...

where

In order to cornpute the Volterra coefficients Ci, we solve the following equation

v, = ~ ~ o v ~ + ~ ~ o v ~ + ~ ~ o v ~ + ... . (2.101)

Volterra coefficients Ci can now be cornputed by inserting equation (2.101) into

equation (2.97) and equatinp the corresponding coefficients for each power in usn.

vs = a i [C,ovS + c 2 o v ; + c 3 0 v S ] + a Z I C l o v S + c 2 0 v $ + C ~ D V : ] ~ + ... (2.102)

The following expressions are obtained for the Ci's


Finally, the Volterra coefficients Ai reiatting the output collecter current ic to the

input voltage vs are calculated from

iC = A ~ O V ~ + A ~ O ~ ~ + A ~ O V ~ + ... . (2.106)

Volterra coefficients Ai are calculated by inserting expression (2.106) into the

equation (2.95). The following expressions are obtained

The value for coefficient Al calculated in equation (2- 107) represents the small sig-

nai transconductance of the single ended stage.

The IM3 product at frequency (20, -ab) is caiculated by using Volterra coeffi-

CHAPTER 2: LOW NOISE. LOW DISTORTION ...

cients A j and Al. Typically, the frequency difference between wu and ab is small. so that

it is assumed that s = sa = s b . The two input signals used for the IM3 analysis are chosen to

provide equd outputs, i.e. lid = I A (s,)l v, = I A ( sb ) (v2 , where

vS = v 1 COS ( m a t ) + v2 COS ( m b f ) (2.1 10)

With these assumptions, the iM.3 level yields to

There are several important observations that can be made regarding equation

(2.1 1 1). First, the term [ 1 + s C j e ( Z b + 2 , ) ] provides the means of reducing, or even can-

celing the IM3 product for the narrow band of interest. This is tme if Zb and 2 , are induc-

tive and are chosen such that 0 2 ~ j e ( ~ b + Le) = - 1 . It was shown previously that the

optimum source impedance for minimum noise figure requires that the input capacitance of

the BJT be resonated out by Lb+Le. It can be seen now that the bipolar singleended stage

has the remarkable property that, by resonating the input capacitance with Lb+Le, both the

noise figure and the IM3 level are minimized.

If Zb and Ze are resistive. the terni [ 1 + sCje(Zb + Z , ) ] c m not be cancelled and the

IM3 product is larger than in case where inductive degeneration is used. The worst case

would be to use capacitive degeneration, because this would always increase the value of

this term.

The second observation regarding equation (2.111) concems the term

. The IM3 c m be lowered by increasing AI&&. In the limiting case

A , (sa - s,) + gm and the term cancels. However, increas-

43


ing AI(sa-sb) at low frequencies is only possible if Zb and Ze are inductive. if Zb and Ze are

resistive, AI(sa-sb) is always less than g, and the term can not be cancelled. The worst

case is again for capacitive degeneration. because in this case Zb(sa - sb), Ze(sa - s,) + - and A l (sa - sb) + O . From ihis discussion, it becomes again apparent that inductive

degeneration helps in reducing or even canceling the IM3 level.

The caiculation of lM3 for the differentiai pair stage follows a similar pattern as for

the single-ended stage. For the circuit in fig. 2.22, the following equation is valid

The Volterra coefficients Bi are defined as

4

Fig. 2.22. Mode1 used for high frequency distortion analysis in differential pair stage.

Using the same procedure descnbed for the singleended stage, coeficients Bi are

calculated to be [2.14]

CHAP"ïER 2: LOW NOISE, LOW DISTORnON ...

where gm = IEE/VT

The IM3 for the differential pair is then given by

Equation (2.1 16) shows that, sirnilarly with the single ended stage, the IM3 can be

reduced or cancelled by inductive degeneration. Also, for the differential pair, resistive

degeneration yields worse results in terms of IM3 levels and capacitive degeneration yields

the worst IM3 performance.

Comparing equation (2.1 16) with equation (2.1 1 l), it can be noticed that the IM3

level of the differential pair is twice as large as that of the single ended stage with the same

bias current (IQ=21EE)- Without degeneration, the IM3 of the single ended stage is twice as

large as that of the differential pair stage, independently on bias current. This result agrees

with the result previously obtained with the conventional distortion analysis at mid-fre-

quencies.


2.4.3 Distortion Andysis of RF Amplifiers with Adjustable Gain

Wide-band amplifiers with adjustable gain find numerous applications in commu-

nications. A typical application for adjustable gain amplifiers is the intermediate-fre-

quency (IF) amplifier that is part of radio receivers. The strength of the received signal at

the antenna varies over a wide range, while the base-band processing circuits require a sig-

nal that is confined to a certain level. The task of adapting the input signal to a constant

output level is given to the IF amplifier with adjustable gain. Ln addition to this primaq

function, the adjustable gain amplifier must meet stringe nt requirements in terms of linear-

ity and noise performance.

Fig. 2.23 presents a wide-band amplifier with adjustable gain. The dc control sig-

nal Vc is applied to the differential pair, while the high frequency signal iS is superimposed

on the bias current fA. If RE can be neglected ( R E = O ), then the output current Io contains

a portion of the input signal and the bias current, as can be verified 12-12] from the follow-

ing equation

This class of circuits provides a variable gain that is proportional to the exponen-

tial of the control voltage, or stated differently, a gain in decibels that is linearly propor-

tional to the control voltage.

Fig. 2.23. Wide-band amplifier with adjustable gain.

46

C w R 2: LOW NOISE, LOW DISTORTION ..,

The following equation is used as a starting point in the distortion analysis of this circuit

' B where R = R +-. B

From equation (2.1 18) it follows that

Because Io + IC2 = IA + iS . equation (2.1 19) becomes

Equation (2.120) is transcendental with respect to the independent variable is. In

analyzing the nonlinearity of the circuit in fig. 2.23, we make the observation that for

VpO, both transistors Ql and Q2 conduct equally. Hence, there is no distortion for the

case of 6dB attenuation, since the input signal is is passed through two identical cornmon

base stages. Also, in the case of Vc » O , there is no distortion. because the input signai is

passed through QI configured as common base stage. The attenuation corresponding to

this case is W.

In general, equation (2.120) shows that there is a large arnount of distortion gener-

ated for attenuation levels in excess of 6dB. This is shown by expanding equation (2.120)

in a power series

The signal current of QI is obtained by subtracting the quiescent current

lcQ = IA exp [ VC/ VT] exp [ ( fA R ) / VT] from the total current ICI. that is,

AssuMng IA R '< VT, which is reasonable for typical values of R and bias current,

equation (2.122) can be reduced to

The IM2 and IM3 levels can now be calculated from equation (2.123) and are

It can be concluded that for this class of circuits, the amount of distortion is propor-

tional to the amount of voltage drop across R = RE + r g / p , relative to VF Fig. 2.24 pre-

sents the total harmonic distortion of this circuit versus attenuation. It can be observed that

the circuit is very linear for ûdF3 and 6dB attenuation.

The linearity characteristic of this type of circuits is of a more general interest.

Indeed, this topology is widely used in Gilbert rnixerslmultipliea. where the input signal

(is in the previous treatment) is usually the RF signai fed to the bottom of the multiplier and

it is required that the circuit does not distort this signal.


A Attenuation [dB] -80 -40 10

> 1 Distortion [dB]

Fig. 2.24. Distortion level vs. attenuation for the circuit of fig. 2.23.

2.5 DESIGN OF A LOW NOISE AMPLIFIER WITH ADJUSTABLE GAIN FOR RADIO FREQUENCY APPLICATIONS

2.5.1 Design of the Low Noise Amplifier

The low noise, low distortion amplifier described in this chapter constitutes the lF

receiver amplifier of a monolithic transceiver for wireless communications [2.1], [2.15].

The typical applications of this transceiver are cellular telephony systems, such as GSM

900MHz and DCS 1800MHz. The requirements imposed on the IF amplifier, as part of a

radio receiver for cellular applications are:

- three selectable gain modes: 40dB,26dB and 16dB of voltage gain;

- noise figure less than 6dB at 1kR source resistance, in high gain mode;

- band width of 45OMHz;

- input PldB higher than 63mV in low gain modes.

- input resistance matched to 1 kQ .

Fig. 2.25 shows the block diagram of the IF amplifier designed to meet the require-

ments specified above.

CEiAPTER 2: LOW NOISE. LOW DISTORTION ...

Gain select u Fig- 2.25. Block diagram of the IF amplifier with adjustable gain.

The gain select block enables one of the foilowing gain modes:

1) 40dB of gain when A l is "ON", A2 is "OFF* and A3 is set for 20dB of gain;

2) 26dB of gain when A l is "Off ' , A2 is "ON" and A3 is set for 20dB of gain;

3) l6dB of gain when A l is "Off ' , A2 is " O N and A3 is set for lOdB of gain;

Fig. 2.26 presents the circuit implementation of the iF amplifier. The differential

pair Q1 and Q2 f o m amplifier A l . while the differential pair Q3 and Q4 f o m amplifier At.

The selection of one of the two amplifiers is done by turning odoff transistors Q5/Q6. The

doublet Q7, Q8, Q9, QlO forms amplifier A3. The gain of amplifier A3 can be adjusted by

changing the collector currents of transistors Q l l and QlZ. An important design aspect

that needs to be mentioned is that ail bias currents, i.e., the collector currents of Q5, Q6,

Q l l and Q12 are PTAT (proportional to absolute temperature). This is needed to compen-

sate for the negative temperature coefficient of the BJT transconductance.

The gain of amplifier A l is *c 1

A' = T~~ = 10.5 , which corresponds to

1 The bandwidth limitation of amplifier A l is given by the pole mpl = - ,

1 C i n where Cin is dominated by the base-ernitter capacitance of transistors Q7 and Q9. In order

C w R 2: LOW NOISE, LOW DISTORTION ...

to obtain a bandwidth higher than 450MH., the device size of Q7 and Q9 and the bias point

for these transistors will be chosen such that Ci,, 5 600fF .

47 1 @

Gain select

Fig. 2.26. IF amplifier with adjustable gain.

As can be seen in fig. 2.26, the input match is realized with resistor R, = 1 kR.

Although this is usually not the optimum solution for minimum noise figure, it has the

advantage, in this application, of providing a wide-band match for the entire IF band. At

the same time, the inductance values needed for matching at IF frequencies would be larger

than the values obtainable in monolithic inductors. The noise figure is given by

'6 + Re? F = 2 + 8 - -

4 +- gm - Rs [' + 1 +Ta ,] = 2.5 . Rs g m - Rs Bo IPO'w)l


which corresponds to Nfldi3]=4dBB The design values in equation (2.126) are: rb = 30R ,

g, = 2 l ( m A ) / V , RS = 1kR .

The gain of amplifier A2 is A2 = G 3 R l = 2 , which corresponds to

'T + *CS R~ A2[dB]=6dB. The same considerations for bandwidth apply for A2 and for A l . Indeed,

both amplifiers use the same collector load R I , connected across Gin- This circuit topology

was actually chosen with the purpose of providing constant bandwidth for different gain

settings. The input IP3 for arnplifierA2 is calculated by setting expression (2.1 16) equal to

one. Thus, IP3 results to be 700mVand, correspondingly, PldB equals 230mV.

The gain of amplifier A3 is [2.16]

where gmo is the corresponding transconductance of a simple differential pair having the

sarne bias current as the total bias current of the doublet and x is the ernitter ratio. For the

case where x=8 and the collector current of QI 1, QI2 is 1.3m.A, the amplifier gain is A3= 10

(or 20dB) and for the case where the collector current of QII , QI2 is 0.4mA, the amplifier

gain is A3=3.16 (or ICkfB). The advantage of using the doublet here resides in the fact that

the gain of A3 can be adjusted by changing the bias current, sirnilar to the case of a simple

differential pair [2.17]. However, the linearity of the doublet is much improved over the

linearity of the simple differential pair: the input PldB for a doublet with x=8 is

PldB=160mV, while for the differential pair PIdB=36mV. hnproved linearity is needed at

the input of A3, where the signal is afready amplified by A l or AZ. indeed, let us consider

an input signal with peak amplitude of 8OmV that is amplified by A2. In this case, the peak

voltage at the input of amplifier A3 is 160mV and will cause gain compression in this

amplifier. This will set the maximum peak voltage at the input of Al, which is lower than

the PIdB of A2.

C-R 2: LOW NOISE. LOW DISTORTION ...

The degeneration resistor value for A2 sets the voltage gain of this stage and is

obviously larger than needed to meet the o v e r d linearity performance. Also, the noise fig-

ure of A2 is larger than that of Al . However, this does not create any problem, since A2 is

turned on when the input signal is strong, hence the signal-to-noise ratio is large.

2.5.2 Simulation Results

The amplifier presented in fig. 2.26 was simulated with Tektronix-SPICE [2.19] in

order to veri@ and optimize the design.

The ac-gain versus frequency is shown in fig. 2.27. The three gain steps (40dB,

26dB and 16dB) are simulated to be constant over frequency up to 1SOMHz. The 3dB

bandwidth occurs around 4SOMHz for al1 three gain steps.

Table 2.1 presents the noise figure and the PldB of the IF amplifier as a function of

gain. The noise figure is 4dB for a gain of W B , as predicted by design. The noise figure

becomes worse for the lower gain modes. The increased input referred noise is due to the

degeneration resistor R2, as well as io the noise contribution of amplifier A3. which is

referred to the input through a stage with reduced gain (AL). As expected, the noise figure

is the worst for the lowest gain mode, because the input referred noise voltage of amplifier

A3 is inversely proportional with the square root of the bias current for this amplifier. The

PIdB occurs at 36mV peak for a gain of 40dB. This value is typical for a bipolar differen-

tial pair and there is no freedom in design regarding it. The value of PldB improves to

82mV for the lower gain modes. As explained eariier, the limitation in this case occurs at

the input of amplifier A3.


Fig. 2.27. Simulated ac-gain versus frequency. 3dB bandwidth is at 450MHz.

Table 2.1: Simulated noise figure and PldB

-

2.5.3 Measurement Results

Gain

The measurement results on the entire receiver, in which the iF amplifier is the

input stage, are surnmarized in Table 2.2 [2.1]

As can be seen in Table 2.2, the bandwidth is in excess of 4SOMHz for ail three gain

stages. The noise figure of 7dB for a gain of 4OdB in the iF amplifier represents the overd1

I 40dB L 1

1 6dB 26dB

C-R 2: LOW NOISE, LOW DISTORllON ...

noise figure of the receiver. Since the IF amplifier is followed by a down-conversion mixer

with a noise figure in excess of 25dB, it is reasonable to asses the noise figure of the IF

amplifier to be around 4dB, as simulated and calculated.

Table 2.2: Measureà values for noise figure, PldB and bandwidth

The measured PldB is close to simulations, showing that the fust stage that com-

presses the signal in the receive chah is the iF amplifier. A microphotograph of the IF

amplifier is presented in fig. 2.28.

In conclusion, the guidelines for low noise and low distortion design of radio fre-

quency circuits were explored. Important design rules, including rules based on the newly

developed noise mode1 for BR, were revealed. Since these resuIts are of general interest in

the design of radio frequency integrated circuits, they are used in al1 subsequent chapters.

A low noise and low distortion IF amplifier with adjustable gain was designed and imple-

mented using the principles outlined in this chapter.

Gain

NF [dB]

P ldB [mV]

3dB bandwidth W z l

1 6dB

20

80

475

26dB

17

80

470

40dB I

7

36

455


Fig. 2-28. Microphotograph of the IF amplifier.

REFERENCES

J. L. Tham, M. A. Margarit, B. Pregardier, C. D. Hull, R. Magoon, F. Carr."A 2.7V 900MHz.1 .%Hz Dual-Band Transceiver IC for Digital Wireless Commu- nication," lEEE Journal of Solid-Srare Circuits, vo1.34, no.3, pp.286-291, March 1999.

G. D. Vendelin. A. M. Pavio, Micrmvave Circuif Design Using Linear and Non- iinear Techniques, John Wiley & Sons, chapter 4, 1990.

D. O. Pederson, K. Mayaram, AnaZog Integrated Circuits for Comrnunicution: Principles, Simulation and Design, Kluwer Academic Publishers, chapter 2, 1991.

J. Fenk,"Highly Integrated RF-IC's for GSM and DECT Systems-A Status


Review," lEEE Transactions on Microwave Theory and Techniques, vol. 45, pp. 253 1-25339, December 1997.

T. D. Stetzler, 1. G. Post, J. H. Havens, M. Koyarna, "A 2.7-4.W Single Chip GSM Transceiver R F Integrated Circuit," IEEE Journal of Solid-State Circuits, vo1.30, no. 12, pp. 142 1 - 1429, December 1995.

E. Perea, R. Van de Plassche, "The Single-Chip Digital Mobile Radio: Does it Really Make Sense?," Proceedings of lSSCC99, pp. 1 22- 1 23, February 1999.

E. G. Nielsen, "Behavior of Noise Figure in Junction Transistors," Proc. IRE, Vol 45, no. 7, pp. 957-963, July 1957.

R. J. Hawkins, "Limitations of Nielsen's and Related Noise Equations Applied to Microwave Bipolar Transistors," Solid-State Electronics, Vol 20. pp. 19 1 - 196, March 1977.

M. J. Deen, "High Frequency Noise Modelling and the Scaling of the Noise Parameters of Polysilicon Emitter Bipolar Junction Transistors," Canadian Jour- nal of Physics, Vol. 74, pp. S 195-S 199 ( 1996)

T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cam- bridge University Press, chapter 1 1, 1998.

P. Wambacq, W. Sansen, Distortion Analysis of Analog Integruted Circuits, Kluwer Acadernic Publishers, chapter 4, 1998.

R. G. Meyer, Advanced lntegrated Circuits for Communicutions, College of Engineering, University of California Berkeley, 1994.

R. G. Meyer, A. K. Wong, "Blocking and Desensitization in RF Amplifers," IEEE Journal of Solid-State Circuits, vol. 30, no. 8. pp. 944-95 1, August 1995.


[2.14] K. L. Fong, R. G. Meyer, "High-Frequency Nonlinearity Analysis of Common- Emitter and Differential-Pair Transconductance Stages," IEEE Journal of Solid- State Circuits, vol. 33, no.4, pp. 548-555, April 1998.

12-15] J. L. Tham, M. A. Margarit, B. Pregardier, C. D. Hull, F. Cam, "A 2.7V 900MHz/1.9GHz Dual-Band Transceiver IC for Digital Wireless Communica- tion," Proceedings of CICC98, pp. 559-562, May 1998.

[2.16] B. Gilbert, "Aspects of Translinear Amplifier Design," Kluwer Academic Pub- lishers, pp. 257-290, 1996.

[2.17] M. Hauser, E. Klumperink, R. G. Meyer, W. Mack, "Variable-Gain, Variable- Transconductance and Multiplication Techniques: A Swvey," Kluwer Acadernic Publishers, pp. 29 1-322, 1996.

[2.18] M. J. Deen, "Analytical Modeling, Scaling and Bonding Pad Effects on the High Frequency Noise in Bipoîar Junction Transistors, "Proceedings of the 8th Asia Pacific Microwave Conference (APMC' 96), Ed. RSGupta, New Delhi, India, Invited Paper, pp. 55 1-556, ( 17-20 December 1996).

[2.19] ADS-TEKSPICE, User's Manual, Tektronix, 1994.

CHAPT'R 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

CHAPTER 3

MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

3.1 INTRODUCTION

This chapter focuses on the study of integrated LC Voltage-Controlled Oscillators

(VCO's) for high frequency applications. Recent circuit topologies are explored with the

intention of finding optimized design solutions in tetms of power consumption and phase

noise, together with high immunity to perturbations that are usually coupled through the

substrate. These are important feanires in the design of monolithic high frequency oscilla-

tors, especially when they are part of highly integrated systems.

An analysis on conditions for proper start-up of oscillation is carried out. This

leads to an optimum solution for damping parasitic modes of oscillation without signifi-

cantly degrading the phase noise performance of the oscillator. The solution was imple-

mented on a silicon LC VCO and the results are published.

3.2 REVIEW OF LITERATURE ON LC OSCILLATORS.

LC oscillators have k e n widely used in communications well before the advent of

monolithic integrated circuit technologies. Fundarnentals about this cIass of circuits are

extensively described in literature and the reader c m find a multitude of interesting aspects

on LC oscillators. Relevant information that synthesizes knowledge on LC oscillators can

be found, for example, in [3.1], 13 -21, [3.3] and [3.4].

The recent developments in monolithic technologies have further increased the

interest in high frequency LC oscillators that find applications in a large variety of commu-

nication technologies. Only a few years ago it seemed that the GHz range for oscillator

IC's was possible only in hybrid GaAs technologies. The past years have shown that,

59

C w R 3: MONOLïTHïC LC VOLTAGE-CONTROLLED OSCILLATORS

while GaAs moves to higher frequencies, the single-digit GHz range in conquered by bipo-

lar, and more recently, by CMOS technologies. Papers published in the 1 s t years report

the development of monolithic LC oscillators in the frequency range of 1.8-2GHz for

CMOS technologies, and higher than 4GHz for bipolar technologies [3.7], [3.10].

Along with the effort in achieving higher frequencies for monolithic LC oscillaton,

a parallel trend is to increase the integrability of radio frequency circuits with the intention

of providing increased functionality on a single chip. Recent papers report fully integrated

radio transceivers, which include LC oscillators, and there are already efforts in the devel-

opment of a singlechip radio, that integrates the radio transceiver, as well as the A/D con-

verters and the base-band DSP [3.8], [3.9].

3.3 LC OSCILLATOR TOPOLOGIES.

3.3.1 Single Ended and Difterential Topologies for Monolithic LC OscilIotors.

A general class of LC oscillators is presented in fig. 3.1. Impedances 2,. Z2, Z3 are

not specified yet. The loop equations for this circuit are written in order to derive the con-

ditions necessary for oscillation

vi = i i (Z2 + Z 3 ) + v + gmv Z2 (3.1)

Fig. 3.1. General LC oscillator.

CHA.PI'ER 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

For this circuit to osciiiate, the curent ii should be zero, even for v i a . This is pos-

sible only if the determinant of the system of equations (3.1) and (3.2) is zero, that is

A =

Expression (3.3) is equivalent to

If al1 three impedances Z,, Z2 and Z3 are real, then equation (3.4) has no solution.

Hence, al1 three impedances must be purely reactive. By sening Zi = r, and solving equa-

tion (3.4) for both the real and the imaginary parts, the following expressions are obtained

%(Z, +Z2+Z3) = O . (3-5)

Z1[(l +p)z2+z3] = 0 . (3.6)

For p real and positive, Z2 and Z3 must be of opposite signs and satisfy the equation

( 1 + P>Z2 = -Z3 . (3.7)

If equation (3.7) is inserted into equation ( 3 3 , the following expression is obtained

zi = pz*. (3.8)

It cm be concluded from equations (3.7) and (3.8) that ZI and Z2 are reactances of

the same type and 5 is of opposite type. if ZI and Zz are capacitances, then Z3 must be

inductance. In the case where the ground of the circuit is located between 2'' and Z3, the

oscillator is narned Colpitts. This circuit is presented in fig. 3.2. If the emitter is grounded,

the circuit becomes a Pierce oscillator. If 2, and Z2 are inductors and 5 is a capacitor, the

CHAFI'ER 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

circuit becomes a Hartley oscillator.

Fig. 3.2. Colpitts oscillator.

Equations (3.7) and (3.8) describe the necessq conditions for oscillation when the

components externai to the active element are assumed lossless. From these equations, it

appears that the conditions for oscillation are independent of the transistor input imped-

ance. This is a consequence of the assumption that the external impedances are purely

reactive. In a practical application the active element is needed to supply the energy dissi-

pated into lossy impedances and to provide energy to the load. From this perspective, the

analysis of oscillators should be approached by considering the active element as a means

of providing the negative resistance necessary to compensate the losses in the reactive cir-

cuit.

The anaiysis of LC osciliators, from the perspective of negative resistance, is pre-

sented for the Colpitts oscillator, although it can be carried out for any of the other topolo-

gies mentioned above. In order to asses the negative resistance, the input impedance of the

circuit in fig. 3.3 is derived. For this circuit, the steady-state loop equations are

vi = ii(XCI +XCZ) - i b ( X C I - PXCS) (3.9)

O = -ii(Xc,) + i,(X,, + r , ) . (3.10)

Fig. 3.3. Circuit with negative input resistance.

62

CHAPTER 3: MONOLïTHïC LC VOLTAGE-CONTROLLED OSCILLATORS

The input impedance is obtained by eliminating ib from these two equations

If Xcl << r, , which is a reasonable assumption at RF frequencies. the input hped-

ance becomes

Equation (3.12) shows that the input impedance into the circuit of fig. 3.3 consists

of a negative real part, (-g,)/(02~l c2) , in series with a capacitor (CI C,)/(Cl + C,) . A

series inductance L connected across the input will provide sustained oscillation if the

series resistance of the inductor equals the negative resistance provided by the active ele-

ment. This interpretation of the circuit provides the guidelines usefbl in osciilator design.

Thus, CI should be as large as possible such that X,, << r,. The value of CI includes the

base-ernitter capacitance of the transistor. Also, CI and C2 should be much larger than the

transistor output capacitances so that the transistor parasitic capacitances have a negligible

effect on the oscillator performance. However, the value of the senes resistance 3 of the

inductance limits the maximum value of the capacitances, since

Thus, the larger the values of the capacitances, the less input negative resistance is pro-

vided.

Fig. 3.4 presents an oscillator that is equivalent with the Colpitts discussed above,

but has the advantage of providing an additional degree of design f ~ e d o m by making Co

much smaller than CI and C2. Capacitors Cl and C2 can be used to satisfy the condition

63

CHAPTER 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

(3.13), while Co is used to adjust the desired frequency of oscillation, which is detennined

by the equation

o0L - (O~C~)-~ - (O~C~)-~ - (oOc2)-l = O . (3.14)

This circuit is known as the Clapp oscillator.

RFC

Fig. 3.4. Clapp oscillator.

The Pierce oscillator belongs to the same class of circuits as Colpitts and Clapp. It

can be seen in fig. 3.5 that this configuration results from the general configuration of fig.

3.1 with the emitter ac-grounded. This circuit has the benefit that the bias resistors do not

shunt the tuned circuit. Resistors connected across the resonator degrade the Q of the cir-

cuit and reduce the frequency stability of the oscillator, as weU as the phase noise perfor-

mance.

Fig. 3.5. Pierce oscillator.


tt will be shown in section 3.4 that LC oscillators have the tendency to oscillate

not only on the fundamental frequency, but also on higher tones that are present due to par-

asitic elements. The Pierce oscillator has a fundamental quality of damping the higher

tones, hence it is very unlikely that this circuit will osciilate parasiticaliy [3.11]. in order

to show this, the collector load impedance is calculated to be

1 where j X 1 = - 1

, jX , = - joCz

, jXL = j o L . RX represents the losses in the inductor. j oCl

At resonance, the following equation is valid

j X L + j X l + j X , = O . -

Thus, equation (3.15) becornes

It can be concluded from equation (3.17) that the collector load is resistive and it is

inversely proportional with the square of the frequency. Therefore, the ohmic losses will

prohibit this circuit from oscillating on higher tones. In a design using the Pierce oscillator,

the total collector loading will be given by ZL from equation (3.17). in parallel with the

transistor output resistance and the actual collector load.

A modified version of the Colpitts oscillator is obtained when the base is ac-

grounded. This circuit can be drawn as in fig. 3.6 in order to emphasize the positive feed-

back implemented with the capacitive divider CI and C2. The resonator for this oscillator

consists of the inductor L and capacitor C. The capacitive divider CI and Cz is used to

adjust the arnount of small signal loop gain, without influencing the oscillation frequency.

65

C-R 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

Fig. 3.6. Modified Colpitts osciilator for common base configuration.

For this circuit the smaii signal loop gain is

where n = Cl + c2 . The reflected loading of this circuit is significant, due to the reduced

input impedance into the common-base configuration. For a given g,& product, the small

signal loop gain is maximized if n=2. This consideration does not necessady apply to a

common emitter configuration, where the reflected loading is not significant and the small

signal loop gain is given by

An example of common emitter configuration with capacitive divider is presented

in fig. 3.7. Here. the 360" phase inversion is realized with the differential pair QI-Q2. The

reflected loading has a negligible effect on the small signal loop gain. Indeed, the reflected RL loading at the base of Q I is - << 2r,. The design variables for this configuration are n2

C m R 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

R,,, = rO2U + gm2/gml 1 = Zro2 (3 -23)

The total load, RL, is given by the output resistance of the differential pair in paral-

le1 with the resistive losses of the resonator and the actual load.

Fig. 3.7. Osc :illator with capacitive feedback in common emitter configuration.

The next approach following the circuit in fig. 3.7 is a hilly differential oscillator

presented in fig. 3.8. The advantage of this circuit is increased imrnunity to substrate noise

that can pull the oscillator to an undesired frequency. At the same time, due to its syrnrne-

try, the second harmonic generated is very low, as long as there is good matching for the

symrnetrical devices. Similar to the circuit in fig. 3.7, the fully differential oscillator per-

m i t ~ the choice of the small signai loop gain independently from the parameters of the res-

onator. This is a very important feature that allows for the optirnization of the oscillator

phase noise by means of optimizing the small signal loop gain. A detailed phase noise

analysis of this topology will be presented in chapter 4.

CHAITER 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

Fig. 3.8. Fully différentiai osciliator with capacitive feedback.

~ , R L The loop gain for the circuit in fig. 3.8 is Al = - n

, where g, is the small signal

transconductance at the on-set of oscillation, and g, = IEE/4VT In steady-state oscilla-

tion, the collector currents of QI and Q2 are square waves, unless there is any AGC mech-

anism to lirnit the oscillation amplitude and ici is given by

For this situation, the large signal transconductance G, is defined as the ratio of the

amplitude of the fundamental in ici to the amplitude of the input voltage and it is

From equations (3.24) and (3 .25), it follows that - Gm = - - ' T . It can be seen that the gm x vi

large signal transconductance goes to zero as the input voltage increases. This is a conse-

quence of the fact that the amplitude in the fundamental is limited by the bias current IEE

and the increase in input voltage has no effect on the fundamental of the output current.

For reliable oscillation start-up, the small signal loop gain is designed to have a value of at

least 3 [3.5]. Since the large signai loop gain is equal to unity, the input signal is designed

C-R 3: MONOLlTHlC LC VOLTAGE-CONTROLLED OSCILLATORS

G m from the relationship - = 3 . Hence, the input voltage should be vj=195mV. The desired gnr

input voltage value is determined by the capacitive ratio n.

3.3.2 Topologies for Voltage-Controlled Oscillators.

The oscillation frequency of a VCO is controllable by an extemal dc voltage. It is

desirable that the process of tuning the resonator do not affect the loop characteristics. In a

classic Colpitts oscillator, like the one depicted in fig. 3.2, any attempt to rn- the oscil-

lation frequency by changing the value of CI or C2, will affect the loop gain. This in turn

will affect the performance of the circuit in rems of oscillation amplitude, frequency sta-

bility and phase noise level. The CIapp oscillator in fig. 3.4 is a better choice, since it pro-

vides increased flexibility due to the presence of Co, which is used to modify the oscillation

frequency, while the loop gain is not affected. The topology using capacitive feedback

(fig. 3.6) appears to be the best candidate for a voltage controlled oscillator. The resonator

can be tuned via capacitor C, while maintaining the capacitive ratio n unaffected. This is

m e as long as the following relationship is verifîed

where Cp is the total parasitic capacitance across the resonator.

A single ended VCO is illustrated in fig. 3.9. Here diode D is used as a varactor

having the reverse-biased junction capacitance controllable by the dc voltage Vc.

The bypass capacitor in fig. 3.9. is very important in filtering the thermal noise gen-

erated by the source resistance R. If the filtering provided by the bypass capacitor is insuf-

ficient, the thermal noise of the source resistance modulates the resonator and causes

increased phase noise.

CHAPTER 3: MONOLïïWC LC VOLTAGE-CONTROLLED OSCTLLATORS

Fig. 3 -9. Single ended voltage-controlled oscillator.

A differential VCO is presented in fig. 3.10. The base-emitter reversed biased junc-

tion capacitance of transistors Q3 and Q4 is used to provide frequency tuning. Similar for

the single ended VCO, the capacitor C is essentid in filtenng the thermal noise generated

by the source resistance. The control voltage Vc needs to be less than VCc in order to main-

tain the base-ernitter junctions of Q3 and Q4 reversed biased.

T V r r

Fig. 3.10. Differential voltage-controlled oscillator.

The use of CMOS processes allows an interesting approach in the design of a dif-

ferential VCO. The CMOS VCO presented in fig. 3.1 1 uses the NMOS gate capacitance as

a varactor [3.10]. The advantage of using this type of varactor resides in the linearity of the

capacitance value versus control voltage. On the other hand, the resistive losses assoçiated

CEIAPTER 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

with the drain and source diffusions are fairly large, and they generate a low Q varactor.

This requires the presence of capacitors Cl and C2, which have to be chosen so that they

dorninate the tank's capacitance. However, the presence of Cl and C2 will reduce the

VCO's tuning range. This design benefits from the presence of high frequency PMOS

transistors, which have a cut-off fiequency only two to three times lower than that of

NMOS transistors. Hence, if PMOS transistors are designed to have two to three times the

width of the NMOS transistors, they will have similar performance. In this design, the

cross-coupled PMOS transistors enhance the negative resistance provided by the NMOS

differential pair. This increases the voltage swing across the resonator and thus improves

the phase noise. The presence of tapped inductors L, and L2 hirther improves the phase

noise. This effect will be discussed in chapter 4.

Fig. 3.1 I . Differential CMOS VCO.

The idea of enhancing the negative resistance provided by the active devices is

implemented in bipolar technologies as well. Unfortunately, the pnp transistor has usually

poor frequency performance, unless a complementary bipolar process is used. Therefore,

the bipolar implementations need to use npn transistors exclusively. Fig. 3.12 presents a

topology that combines the advantages of the balanced oscillator with the advantages of the

CHAP'ïER 3: MONOLITHIC LC VOLTAGE-CO~OLLED OSCILLATORS

differential Colpitts [3.12].

l resonator 1 tesonator 1

-L & a) balanced oscillator b) di fferential Col pins osciIlator

r resonator 1

c) enhanced Colpim B Q ~ oscillator I

Fig. 3.12. Enhanced differential Colpitts VCO.

The benefit of the combined device in fig. 3.12 c m be understood if we make the

remark that the collector currents of Q3 and Q4 provide enhanced charging and discharging

capability for capacitors C3 and C2. respectively. The balanced oscillator in fig. 3.12a)

provides a negative resistance of (-2/g,), which is superior to the negative resistance pro-

vided by the differential Colpitts in fig. 3.12b). On the other hand, the total capacitance

provided by the differential Colpitts to the resonator is smaller than the capacitance pro-

vided by the balanced oscillator. It is demonstrated anaiyticaily, and verïfied by simula-

tions that the enhanced Colpitts combines the advantages from the two topologies [3.12].

The important benefit for a voltage-controlled oscillator consists in the reduced capacitive

Ioading provided by the active device to the resonator. This allows for the design of a large

tuning range.


3.4 VOLTAGE-CONTROLLED OSCILLATOR START-UP

3.4.1 Oscillation Build-Up

The basic requirement for an oscillation build up is the existence of a pair of com-

plex conjugate poles pl,z, given by

pi , z = a W . (3 -27)

in the right half of the s-plane, that is, with a > O. The circuit is then unstable about its

operating point, and it can produce a growing sinusoidal signal

when subjected to an excitation, such as power supply mm on. y0 is determined by initial

conditions and the amplitude of the signal will continue to grow until it begins to limit due

to the non-linearities of the circuit.

Oscillation build-up behavior is described in a linear analysis by studying the pole

locations using either the feedback model or the negative resistance model presented in fig.

3.13. The feedback model will be presented shortly, while the focus will then be the pre-

sentation of the negative resistance model because of its simplicity and its natural exten-

sion to a steady-state oscillator behavior analysis as shown by Kurokawa C3.41.

a) Feedback model

Active circuit Resonator

4 b b) Negative-resistance model

Fig. 3.13. Harmonic Oscillator Models.

7 3

C-R 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCLLLATORS

In the feedback model in fig. 3.13a), the osciliator circuit is separated into the for-

ward and feedback paths. The poles of the circuit can be determined by the roots of the

characteristic equation,

1 - T(s) = O , (3 -29)

where T(s), the lwp gain is the product of the transfer functions of the forward and feed-

back paths, a(s)f(s). The following criteria is used as an indication that the circuit is unsta-

ble,

I T ( q l > 1 LT(oz) = O I 2 x n (n = 0,1,2, ...) (3 -30)

where o, denotes the frequency at which the total phase-shifi through the forward and

feedback paths is zero. Although this condition is necessary, it is, however, not sufficient to

ensure an oscillation build-up, especially if equation (3.30) is satisfied at multiple frequen-

cies [3.5].

In the negative-resistance model of fig. 3.13b), the oscillator circuit is separated

into a one-port active circuit and a one-port frequency determining circuit. Assuming that

the steady-state voltage across the active circuit is near-sinusoidal, the two ports are char-

acterized by their admittances Y,(s) and Y&s) , respectively. The characteristic equation

of the oscillator is given by the expression

YJs) + Y&s) = O . (3.3 1)

The frequency determining circuit is usually a linear, time-invariant resonant cir-

cuit, while the active circuit is operated under large signal conditions and is therefore non-

linear.

The following condition [3.6] has been used to indicate circuit instability,

C H . R 3: MONOLlTHIC LC VOLTAGE-CONTROLLED OSCILLATORS

where Ga = Re { Y, ) , Gf = Re { YI} , Ba = I m { Y,} and Bf = I m { Y/) are the respective

conductances and susceptances of Y, and Yf; a, denotes the frequency at which the total

reactive component equals zero. It cm be shown that expression (3.32) is not a sufficient

condition for oscillation build-up, especially if it is satisfied at multiple frequencies [3.5].

It cm be dernonstrated that there is another necessary condition, in addition to

(3.32.a) and (3.32.b), for a well-behaved oscillation. If the voltage across the active circuit

is near-sinusoidal, the active and frequency detedning circuit can be characterized by

their respective admittances Ya(s) and Yks) . The toplogy that is known to result in a

well-behaved oscillator is a parallel RLC resonator dnven by a voltage-controlled negative

resistance (VCNR). If it is assumed that the susceptance of the active circuit, B,(s), c m be

lumped into Ybs) and that the conductance of the active circuit. Ga, is frequency indepen-

dent, then the foliowing expression is denved for the total admittance

' . The derivative of this expression is always Y T ( u ) = Yo(m) + Y / o ) = 61- CT-- O - L,

positive, which leads to the third necessary condition that, together with conditions given

by equations (3.32.a) and (3.32.b), ensure the existence of a parallel resonance at a,, that is

The dual of conditions given by equations (3.32.a), (3.32.b) and (3.32.c) are valid

for a series RLC resonator driven by a current-controlled negative resistance circuit, where

conductances become resistances and susceptances become reactances.

CEiGPTER 3: MONOLI'MIC LC VOLTAGE-CONTROLLED OSCILLATORS

As a general criteria for proper start-up, conditions (3.30) and (3.32) are valid for

predicting oscillation start-ups if they are satisfied at one frequency only. Proper oscillator

start-up behavior may be further c o n f m e d with the Nyquist and root-locus analyses [3.6]

of equation (3.29). Root-locus analysis is particularly useful for additional insight of the

oscillator circuit operation such as the presence of multiple oscillations.

3.4.2 Oscillator Steady -State Behavior

While linear analysis is useful for analyzing oscillation start-up, it is no longer valid

as the oscillation continues to grow and the non-linearities of the circuit become important.

Non-linear anaiysis can be used to predict the oscillation amplitude and the harmonic con-

tent of the output signal. However. non-linear analysis of the oscillator behavior can be

simplified for high spectral purity LC oscillators, which exhibit a near sinusoidal ori l la-

tion [3.3], 13-41. It has k e n shown that for a steady-state oscillation with a near sinusoidal

voltage [3.4], the following conditions hold,

GJq,, A,) + C ' a , ) = 0 (3.33.a)

B,(a,, A,) + B ' a o ) = 0 . (3.33.b)

where o, is the steady-state oscillation frequency and A, is the steady-state oscillation

amplitude. The admittance of the active circuit, Y, = Ga + jBa , is generally a fbnction of

the oscillation frequency and the oscillation amplitude because of its non-linear nature. It

needs to be emphasized that in equations (3.33), Ga and Ba, the conductance and suscep-

tance of the active circuit are evaluated at the fundamental frequency o,. o-, & the fre-

quency at which the total phase-shift through the forward and feedback paths is zero, and

a,, the frequency at which the total susceptive component equals zero, are in general not

equal to a, . However, for resonant circuits with high Q's, c and a, are good approxima-

tions to the steady-state oscillation frequency.


For a senes RLC topology, where the current into the active circuit is nearly sinu-

soidal, the dual of equations (3.33) are vdid for the resistance and reactance.

3.43 Voltage-Controlled Oscillator Resonator Topologies

Reliable oscillators are realized by coupling the appropriate resonator with the

active circuit that provides the negative resistance necessary to overcome the resonator

losses. A parallel RLC resonator is properly coupled with an one-port active circuit, that

can be represented as a voltage-controïled negative resistance (VCNR)[3.5]. The emitter-

coupled pair with positive feedback in Fig- 3.14a) is an example. The normalized 1-V char- I 1 v

acteristic of the circuit with - = - b ' where b = - , is presented in Fig. 3.14b). IEE I + e "T

Fig. 3.14. a) ECP with positive feedback (Ieft) and b) 1-V characteristic of ECP (right).

Fig. 3.15 shows a typical VCNR topology with a varactor-tuned parallel RLC res-

onant circuit, where transconductor G represents the active circuit that overcomes the

losses in the resonant circuit. The varactor, C,, whose capacitance is a function of its

reverse bias voltage, is used to tune the resonant frequency of the tank. Capacitor Cc has a

value large enough to ac-couple the varactor to the parallel tank.

C m R 3: MONOLiTHIC LC VOLTAGE-CONTROLLED OSCILLATORS

Fig. 3.15. VCNR with varactor-tuned pardlel resonant tank.

Off-Chip Resonalors

The circuit in fig. 3.15 c m be used to model an oscillator for mid-ffequencies.

However, at higher operating frequencies, the package parasitics are on the same order as

the resonant tank components, and these parasitics need to be included in the oscillator

model. Parasitics are contributed not only by the active circuits package, but also by the

packaged varactor, where the lead and bond-wire inductances increase the equivalent

capacitance. The effect of these parasitics is to contribute undesired oscillation modes in

addition to the fundamental mode. These effects can be studied by applying the mot locus

method, or the start-up conditions described in equations (3.32).

The equivalent circuit of fig. 3.15, which includes the package parasitics of the var-

actor and the active circuit is shown in fig. 3.16. Inductance 1, models the package lead

and bond-wires of the varactor and r, models the resistive losses in the varactor. cb mod-

els the parasitic capacitances of the board, varactor and chip inductor 1 , . c,, and l2

model the parasitics associated with the package that contains the active circuit. The sum

of admittances is


where Y,(s) = G, = -(3 Gflo,)) for oscillation proper start-up. The following expres-

sion is valid for Yhs)

Fig. 3.16. Equivalent circuit of figure 3.15. with package parasitic.

The sum of admittances, Yds), is plotted in fig. 3.17. It can be seen in this plot that

there are two parallel resonances: the first one at 950MHz (desired) and the second at

5GHz (undesired). These resonances appear at the frequencies where conditions given by

equations (3.32) are satisfied.

The resonance at 5 GHz is due to the mode associated with 1 1 1 - Il [. I2 + (, II ((s - 1 l ) Il (s - 1" + -)))] that is generated by the presence of

S - C P

s C,

package inductances l2 and 1,. There is also a series resonance at around 10 GHz.

A study of poles location of the circuit can be carried out by plotting the roots of

equation (3.35). while varying the value of transconductance Ga. This study can provide

usefui information regarding the possible modes of oscillation during the start-up [3.13].

79

C w R 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCLLATORS

0.2

Re [YT(s)I8 IO [ohm-']

Fig. 3.17. Real and imaginary parts of the admittance of circuit in figure 3.16. Note that the real

part is multiplied 10 times its actual value.

In order to darnp the undesired oscillation mode of the circuit in fig. 3.16, a resistor

is added in series with inductance 12. The modified circuit is presented in fig. 3.18. The

analysis of resonant modes present in this circuit is carried out by studying the plots of the

real and imaginary parts of YT(s) [3.13], [3.14].

Fig. 3.1 8. Using the circuit shown in fig. 3.16, a damping resistor is added in series with package

parasitic inductance.

80

C w R 3: MONOLITHIC LC VOLTAGE-CONTROLLED OSCILLATORS

For the circuit in fig. 3.18 the sum of admittances is

Y ~ s ) = YJs) + Y/s) = Ga + Y/s)

with Ya(s) = Ga = -(3 - Gpa,)) . The expression for Y{s) becomes

The admittance plot in fig. 3.19. shows that resistor rz darnps the second parallel

mode that was previously present at 5GHz. The analysis of resonant modes is based on

conditions given by equations (3.32) that are applied to the real and imaginary parts of

YT(s) in Fig. 3.19. Specid care needs to be taken when choosing the value for resistor Q.

since an increase of its value degrades the phase noise performance of the oscillator. A

detailed analysis of the phase noise performance for this topology is presented in chapter 4,

where the effect of resistor rz is considered [3.14], [3.15].

Fig. 3.19. Red and imaginary parts of the admittance of circuit in Bg. 3.18.


In summary, the latest monolithic LC oscillator topologies were explored in order

to identiS high performance design solutions for circuits that provide a well behaved oscil-

lation and a low phase noise level. The design guidelines presented were applied to the

design of a monolithic VCO intended for wireless applications, where low phase noise and

low power consumption are strict requirements [3.14], [3.15]. The noise analysis for this

design is developed in chapter 4.

REFERENCES

D. O. Pederson, K. Mayaram, Analog Integrated Circiiits for Communications, Kluwer Academic Publishers, chapter 9, 199 1.

J. Smith, Modem Communication Circuits, McGraw-Hill, Inc., chapter 7, 1986.

K. K. Clarke, D. T. Hess, Communication Circuits: Analysis and Design, Addi- son Wesley, 197 1.

K. Kurokawa, "Some Characteristics of Broadband Negative Resistance Oscilla- tor Circuit," Bell System Technical Journal, pp. 937- 1955. July-August, 1969.

N. M. Nguyen, R. G. Meyer, "Start-up and Frequency Stability in High Fre- quency Oscillators," IEEE Journal of Solid-State Circuits, ~01.27, no. 5. pp. 8 10- 820, May 1992.

S. Maas, Nonlinear Microwave Circuits, Artec h House, Norwood, 1988.

A. Springer, R. Weigel, E. Kristan, P. Sehrig, J. Fenk, "Design and Performance of a Fully Integrated 4 GHz VCO with High Tuning Range for GSM/PCN Mobile Communication Systems," Proceedings of M m - S European Wireless Conference, pp. 287-29 1, 19%.


[3.8] J. L. Tham, M. A. Margarit, B. Pregardier, C. D. Hull, R. Magoon, F. Cam, "A 2.7V 900MHz/1.9GHz Dual-Band Transceiver IC for Digital Wireless Commu- nication," IEEE Journal of Solid-State Circuits, vo1.34, no.3, pp. 286-291, March 1999.

[3.9] E. Perea, R. Van de Plassche, "The Single-Chip Digital Mobile Radio: Does it Really Make Sense?," Proceedings of lSSCC99, pp. 122- 123, February 1999.

[3.10] T. 1. Ahrens, A. Hajimiri, T. H. Lee, "A 1.6GHz 0.5mW CMOS LC Low Phase Noise VCO Using Bond Wire inductances," International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 69-7 1, July 1997.

[3.11] R. G. Meyer, Advanced Integrated Circuits for Communications, College of Engineering, University of Califomia Berkeley, 1994.

[3.12] L. Hessen, E. Stikvoort, "An Enhanced Colpitts UHF Oscillator for TV Tuners, " Proceedings of ESSCIRC'98, pp. 158- 16 1, September 1998.

I3.131 J. L. Tham, "Integrated Radio Frequency LC Voltage-Controlled Oscillators," Electron ics Research Labora tory Mernorandum, College of Engineering, Uni- versity of Califomia, Berkeley, 1995.

[3.14] M. A. Margarit, J. L. Tham, R. G. Meyer, M. J. Deen, "A Low-Noise Low Power VCO with Automatic Amplitude Control for Wireless Applications," IEEEE Journal of Solid-State Circuits, vo1.34, no.6, pp. 76 1-77 1, June 1999.

[3.15] M. A. Margarit, J. L. Tham, M. J. Deen, R. G. Meyer, "Noise Analysis of a VCO with Automatic Amplitude Control," Proceedings of CICC99, pp. 38 1-384, May 1999.

CHAPTER 4: PHASE NOISE IN OSCILLATORS

CHAPTER 4

PHASE NOISE IN OSCILLATORS

4.1 INTRODUCTION

In this chapter, a noise analysis method is developed that considers the nonlinear

effects in oscillators. The linear analysis of phase noise will be explored first. Despite its

limitations, this analysis provides some good design guidelines that are usually required in

implementation of low noise LC oscillators. Good design exarnples that follow these

guidelines will be analyzed. The next section of this chapter will explore new develop-

ments on phase noise that consider the nonlinear effects in oscillators. This analysis will be

followed by design examples that reduce phase noise by using techniques specific to a non-

linear approach. The last section will present the design and nonlinear phase noise analysis

of an LC oscillator for wireless communications.

Early developments on this subject consider the effect of recirculated noise that is

shaped by the oscillator LC-resonant tank [4.1], [4.2]. However, by neglecting the inherent

nonlinearities present in an oscillator at steady-state operation, these developrnents can not

explain the phase noise in other types of oscillators, such as ring oscillators, nor can they

explain the effect of harmonic rnixing of low frequency noise components. In order to

address the problem of nonlinear behavior, the most recent developments start from the

state equations that can be used to describe any electric circuit. A mathematical develop-

ment of ihis problem was published by Kaertner [4.3]. His solution is suitable for a numer-

ical implementation, using algonthms that are specific to computer-aided design. Another

recently published development allows the circuit designer to obtain valuable information

regarding noise effects in nonlinear oscillators [4.4].

It is weil known that phase noise of an LC oscillator can be improved by increasing

CHAPTER 4: PHASE NOISE iN OSCILLATORS

the resonator Q andor by increasing the power into the resonator. Usually, reported works

on the differential VCO in fig. 4.1 focus on reducing the phase noise by means of improv-

ing the quality factor of the resonator. The original contribution of the present work con-

sists in the nonlinear phase noise analysis of the VCO in fig. 4.1. As a result of this work,

the effect of phase noise optimization, based on the capacitive feedback ratio n, is for the

first time reported in literatwe 14-51, [4.6]. It is demonstrated in the present work that opti-

mum feedback ratio n for minimum phase noise c m contradict the proper oscillation start-

up cnteria Therefore, an automatic amplitude control (AAC) loop was developed. This

AAC loop decouples the condition of optimal feedback ratio from the proper start-up con-

dition. The optimized VCO was irnplemented and charactcrized. The results obtained

with this design are compared in Table 4.1 with different implementations that were

recently pubfished. For better cornparison, a figure of merit defined as

F o M [ d B ] = 20log(freq) -phase - noise - lOlog(power) , is given in this table.

Fig. 4.1. Differential VCO with feedback ratio n = Cl + C2

Cl -

C w R 4: PHASE NOISE IN OSCILLATORS

Table 4.1: Cornparison of performance of monolithic VCO's.

Ref [4.7]

Ref [4.8]

Ref[4.9] 25GHzBJT

Ref [4.1 O] I2GHz BiCMOS -t-

Ref [4.11] 1 CMOS

Ref [4.12] ( 25GHr BIT

Ref [4.13] 1 25GHz B JT

NIA off-chip 1.2GHz

0.51 1 bond-wire 1 1 -6GHz

Phase noise Power at FoM

A=100kHz

SmW -106dBdHz 312dB

0.5mW -95dBcMz 312dB

24m W - 109dBcMz 3 10dB

2mW - 1 0 5 â B c H ~ 312dB

4.2 SMALL SIGNAL NOISE ANALYSIS IN OSCILLATORS.

4.2.1 Small Signal Noise Analysis in Oscillators.

N/A

N/A

Early developments on noise in oscillators were done independently by Leeson

[4.1] and Robins [4.2]. The inherent nonlinear nature of oscillators is discussed in these

developments. Indeed, if the oscillator had a u ~ t y small- signal b o p gain, then the oscil-

lation amplitude would never build up. Some nonlinear mechanism must be present to

reduce the small-signal loop gain once the oscillation has built up. The effect of nonlinear-

ities is found mainly in two frequency domains: one is the low frequency, the second is the

frequency range close to the oscillation frequency.

Low frequency noise sources, like l/fnoise, will mix against the carrier and gen-

erate components at an offset frequency Sfi from carrier, if the initial low frequency noise

source was at an absolute frequency 6f, . It is admitted in these linear developments that

off-chip

on-chip

-9SdBcMz

-105dBcMz

304dB

304dB

I.6GHz

4GHz

3mW

4.5mW

CHAPTER 4: PHASE NOISE IN OSCLLATORS

the low frequency noise mixing is neglected.

A noise source at frequency fosc + 6f2 close to the camier wili produce the image

at frequency fi, = 2foSC - CI,,, + 6 f2 ) = fosc - 6fi . This process where a smaii-signai

source mixes against the large signal source represented by the carrier is shown in fig. 4.2.

The analysis in [4.1] and 14-21 consider only noise sources that are close to the oscillation

frequency. Besides the simplifLing assumption of a linear oscillator, other assumptions in

this analysis are:

a) the loop gain of the linear oscillator at steady-state is close to unity; this assump-

tion is not more simpliQing than the assumption of linearity itself.

b) the output power of the oscillator consists of noise amplified by the positive

feedback and fdtered by the effective Q of the oscillator. This is a reasonable assumption,

since there is no signal present at the oscillator input, other than the recirculated output sig-

nai.

c) the total output admittance is matched to the input adrnittance of the active

device at resonance. Although this is a restriction used in the mathematicai denvation, it

does not impose the restriction of input matching to the final results.

Fig. 4.2. Mixing process of a noise source of frequency close to the carrier.

In order to better understand the benefits and limitations of the linear analysis, some

87

C m R 4: PHASE NOISE IN OSCILLATORS

steps of it are followed next. The circuit in fig. 4.3 is considered, where the feedback ratio

n is considered such as to provide matching

n2 = R,/Rt.

Fig. 4.3. Oscillator model,

Thus, at resonance V,,, = VinG(RL/2) . Due to the input match. the available

input noise voltage is

where F represents the amplifier noise figure. Since Vin = n + VoU, + VN, i n , the following

expression is obtained for V,,,

which is valid at resonance. For fiequencies close to resonance, equation (4.3) is written as

( v ~ , , , ) ~ ( c ( R L / 2 ) vN, - The output power is Po,, = - - and the input power is 4 RL[l - ~ ( ~ ~ / 2 ) n ] ~


vN. in -- Pin - Rin , such that the power gain becomes

G ~ ( R , / ~ ) ~ R , Gain =

R L [ l - G ( R , / z ) ~ ] ~ .

Since the steady-state loop gain is very close to unit . , Le. G ( R L / 2 ) n = 1 , equation

(4.5) shows that the power gain of the oscillator is very large and it can be regarded as

amplified noise in a very narrow band. Then, the input power is the input noise power den-

sity times the noise bandwidth

and the power gain can be written as

= out Gain =

f- \

By equating equation (4.5) with equation (4.7), and considering that

B e , = B [ 1 - C ( R L / 2 ) n J . where B is the bandwidth of the resonator, the following expres-

sions are obtained after some manipulations for the effective bandwidth and effective Q,

It FkTB - -B- - 2 Po,,

Q in equation (4.9) is the loaded quality factor of the resonator.

It is worth mentioning here that, in steady-state oscillation, when the loop gain is

almost unity, the effective bandwidth Be8becomes very narmw, while the effective quality

factor. Qep becomes very large. Since the output power is amplified noise, the output

C-R 4: PHASE NOISE IN OSCILLATORS

noise power density is

Next, the denvation focuses to offset frequencies large enough so that

4 Q : ~ 3 ' a 1 . For these frequencies, the ratio of noise density to output power becornes

after some manipulations

Although the denvation has led to equation (4. IO), which has the form of a low-

pass transfer function, the final expression (4.11) neglects the Low-pass corner frequency.

So far, there has not been any reported phase noise measurement that would confirm the

existence of a low-pass corner frequency. Rather, the phase noise level keeps on increasing

for the smallest frequency offset that can be observed. This phenornenon can not be

explained by the present analysis.

Considering that the output noise power density in equation (4.11) has the charac-

teristics of white noise, the phase noise density is half of the total noise density and the ratio

of phase noise density to output power is

This equation, derived with the Limiting assumption of white noise at oscillator out-

put, is the well-known Leeson's equation. It provides the quantitative description for the

ratio of single-side band noise density to carrier power. Limitations of this analysis consist

of the following,

CHAPTER 4: PHASE NOISE ïN OSCILLATORS

a) it can not predict up-conversion of low frequency noise signals, due to the

assurnption of a linear oscillator;

b) it assumes white noise sources only and therefore it has difficulties in predicting

the oscillator behavior in the presence of frequency dependent noise sources;

C) it gives no indication to the noise figure of the active element, which is different

from the noise figure of the same active device operating under iinear conditions; and

d) it can not predict the frequency translation of a noise component situated close to

the carrier at one sideband into the other sideband.

The outstanding contribution of these early developments consists in revealing the

important design parameters that need to be considered in optirnizing the phase noise per-

formance of LC oscillators. First, the phase noise is directly proportional to the noise figure

of the active device and inversely proportional to the square of the resonator Q. Second, the

phase noise is inversely proportional to the output power into the resonator and directly

proportional to the square of the oscillation frequency.

Another interesting perspective offered by the above analysis is in terms of reveal-

ing the trade-off that exists between the resonator loaded Q and the optimum source resis-

tance for minimum noise figure of the active device. It was demonstrated in chapter 2 of

this work that, for a bipolar transistor, a design can be implemented such that the optimum

source resistance for minimum noise figure is close to the impedance matching condition.

On the other hand, input impedance matching will reduce the loaded Q by a factor of two.

The other extreme case would be the one where Ri,, w n 2 ~ L , such that the resonator Q is

unaffected, but the noise figure is far from minimum. Unfortunately, the means for such

optirnization of the phase noise are not offered by this analysis. Section 4.4 of this work

CHAPmR 4: PHASE NOISE IN OSCILLATORS

will present this type of optimization implemented with techniques that are specific to

noise analysis in nonlinear circuits.

4.2.2 The Duality between Phase Noise in Frequency Domain and Time Jitter

Phase noise can be interpreted in time domain as a randorn phase associated with

the oscillation waveform. Let us consider the oscillator output of the fonn

v ( t ) = VCOS (wOt + ~ ( t ) ) - (4.13)

For this interpretation of phase noise, any amplitude modulation will be neglected,

and the demonstration will only fwus on the phase modulation. This assumption does not

significantly affect the final result, since AM to PM conversion in a real oscillator is negli-

gible as long as the amplitude modulation is small, as would be the case with AM caused

by noise.

A signai of angular frequency oo and amplitude V that is frequency modulated by

a harmonic signal of frequency a, has the representation

where Af is the peak frequency deviation and < p p = Af/f, is the peak phase deviation.

By expanding equation (4.14), the following expression is obtained

For a peak phase deviation much less than unity, Le. < p p u 1 , as would be the case

with phase modulation caused by noise, equation (4.15) becomes

V ( I ) = $cos (ao>) - %sin (mot) sin (o,t) fm 1

C m R 4: PHASE NOISE IN OSCLLATORS

VP cos(oor) - - [cos(wo + om)t + cos (ao - %)t ] 2

Equation (4.16) shows that a srnall phase deviation results in frequency compo-

nents on each side of the carrier and having the amplitude Vn = V<pp/2. Thus. the ratio of

the peak side-band amplitude to carrier amplitude is

and the power ratio is

This result is extended to the interpretation of the power spectral density of a signal

having constant amplitude and k i n g phase modulated with a small modulation index. If

the normaiized single-side band power spectral density is considered constant in a unit

bandwidth and at the angular frequency o,,, offset from the carrier, then it can be written as

PP,sss(~m) . Since the modulation process gives rise to symmetrical side bands, the

power in botb side bands is

In this interpretation, Po(mm) is the ratio of power density at mm angular fre-

quency offset to the carrier power [4.14]. The interpretation of phase noise as a phase

modulation performed on the oscillator carrier leads to a function of the form (cr)/o: . Although this development provides only an interpretation for phase noise, the inverse

dependency of normalized noise density with the square of the offset frequency is in agree-

ment with Leeson's formula. Fig. 4.4. represents the double-side band noise power den-


sity. It is worth mentioning that this development invokes a frequency modulation process,

which is nonlinear. However, this does not make any assumptions on the nonlinearity of

the oscillator itself. Therefore, this development c m not explain frequency conversion of

noise around harrnonics of oscillation in a satisfactory manner.

Fig. 4.4. Double-side band noise power density in oscillators.

4.2.3 Optimization of Oscillator Components for Minimal Phase Noise

Based on the iïnear analysis previously presented, optimization of phase noise per-

formance c m be achieved in several ways. The most direct one is to increase the output

power into the resonator. Unfortunately, this approach usually results in a design that is not

cornpetitive, especially for wireless applications. Another way is to use low noise active

devices that will provide low noise figure in the final design. However, the derivation

based on linear theory does not allow for a precise calculation of noise figure when the

active device is operated under large signal conditions. Therefore, the most efficient

method to improve the phase noise is to enhance the resonator Q. Recently published

designs that employ this technique and achieve very good phase noise performance will be

presented next.

Fig. 4.5 presents a fully integrated VCO implemented in bipolar technology that

operates at 4GHz r4.131. The current consumption is 1.5mA and the phase noise level is

CtlAPTËIR 4: PHASE NOISE IN OSCILLATORS

- 1 0 5 d B c ~ at 100kHz offset from a SOOMHz carrier. This phase noise level is achieved

after a three-stage frequency divider. The idea of improving the phase noise for this design

is to obtain an integrated resonator with as high a Q as possible. Since the VCO core oper-

ates at 4GHz, the tank capacitance is composed of the parasitics of the transistors, which

are -200fF and the parasitics of the monolithic inductor of approximately 1ûûfF. VCO

tuning is achieved by changing the transistors bias, which in tum, changes the devices par-

asitics. An important point to note here is that this VCO is probably very sensitive to sub-

strate noise, and this noise will FM-modulate the output via the device parasitic

capacitances, which are nonlinear. The monolithic inductor used for this design achieves a

Q of 6. It is reaiized with a rectanjylar aluminum loop. In order to reduce ohmk losses,

two identical loops in the second and third metal layer are connected in parallel using via

contacts. The equivalent circuit used to mode1 the monolithic inductor is presented in fig.

4.6. The element values are: L=3.25nH, RA,=3.62Q, Csm=104fF-, Rsm=380S), and

Fig. 4.5. Fully integrated &Hz VCO.

Fig. 4.6. Equivalent circuit mode1 for monolithic inductor used in the VCO of fig. 4.5.

CHAPTER 4: PHASE NOISE IN OSCLLATORS

A useful idea that is used to improve phase noise is to tap the resonator. By tapping

the resonator, the losses associated with the active devices appear only across a portion of

the tank, such that the total Ioss produced by the active devices is divided by the tapping

ratio. Additionally, it is possible that tapping ailows for the voltage swing in the resonator

to exceed the supply. This is a second advantage of the technique, because it increases the

power into the tank,

A recentiy published design [4.7] that makes use of the tapping technique is pre-

sented in fig. 4.7. The inductors used for this design are four bond wires. For each induc-

tor, a bond wire crosses from the bond pad to the package. The symmetrical inductor is

implemented similarly for the return path. Thus, symmetry for each pair of inductors is

preserved. Inductor LI has a value of approximately 5nH and L2 is approximately 4nH;

therefore, the tapping ratio is 1.8. Another advantage of the method is that the extra pack-

age capacitance is located at the centre of two symmetrical inductors, so it does not affect

the performance because the centre point is a virtual ground.

kcf ,g+-1 1 var V, var I

Fig. 4.7. CMOS VCO with tapped inductors. Tapping ratio is (1+L2)/L1.


The varactors for this design are implernented using NMOS gate capacitors oper-

ated near threshold. Losses in these capacitors are fairly large and they tend to degrade the

overall Q of the tank. Therefore, the authors [4.7] chose to design the tank such that the

NMOS capacitance is only a small part of the total capacitance. This reduces instead the

VCO tuning range.

Following the same idea of tapping the resonator, we make the remark that the

Clapp oscillator provides the benefit of coupling the transistor noise to the tank via a capac-

itive divider, as can be seen in fig. 4.8. The transistor noise is then coupled into the tank

with a ratio

RE

RFC

Fig. 4.8. Reduction of phase noise in a Clapp oscillator by tapping the resonator.

This will improve the phase noise by the sarne factor 113. The improvement in

phase noise is considerable in this case, since Co in a Clapp osciilator is chosen to be much

smaller than (C l C2)I(CI+C2), such as to detennine the oscillation frequency. The trade-off

in this case is the increased power required to ensure the high voltage swing across Co and

L.


More generally, it c m be concluded from [4.11] that the coupling of noise sources

into the resonator by a divide ratio of llp will improve the phase noise performance of the

circuit by times, independently of the inputs and outputs of the tank. This is a conse-

quence of the fact that phase noise is a ratio of noise density to the effective power into the

tank. As an illustration, the circuit in fig. 4.9 benefits from a phase noise reduction of -

Fig- 4.9. Technique of reducing phase noise by [C,:CJ. \

4.3 NONLINEAR NOISE ANALYSIS IN OSCILLATORS

4.3.1 Effécts of Nonlinearity in OsciMators

The quantitative description of phase noise presented so far is limited to predicting

shaping at oscillator output of white noise sources. It is known experimentally that llf low

frequency noise sources are shaped to a llf3 slope at the oscillator output. This effect, as

well as the corner frequency where the llf3 slope intersects the llf 2, cannot be predicted by

linear analysis. Empirically it was believed that this corner frequency coincides with the

corner frequency of the l/f noise source [4.1]. It will be demonstrated in section 4.4.2. that

these two frequencies do not coincide. However, this effect can only be described using a

nonlinear approach for phase noise in oscillators.

Another effect that is related to nonlinearities in oscil1ators is the frequency conver-

CHAP'ïER 4: PHASE NOISE IN OSCILLATORS

sion of noise components situated around harmonics of the carrier, including the dc com-

ponent. It is observed experimentally that an osciiiator presenting stronger harmonics has

worse phase noise performance, but the effect can not be quantified using a linear develop-

ment. Other effects related to nonlinearities in the active devices were observed to influ-

ence the phase noise performance. Some of these effects are:

1 ) changing the oscillator feedback ratio,

2) changing the operating point of active devices, or

3) apparent minor changes in the amplifier topology, such as providing better device

matching.

In a linear treatment al1 these effects were ernbedded in the global factor F, the amplifier

noise figure, but the designer had no means of controlling this factor in a desired way.

A rigorous mathematical treatment for phase noise in oscilIators is provided in

[4.3], and this can be the basis for a CAD application. On the other hand, a phase noise

model that accounts for nonlinearities would be a powerful tool providing the designer

with practicai information for optimizing the noise performance.

4.3.2 Noise Analysis Based on the State Space Approach

The recently published phase noise model of oscillators in [4.4] gives useful infor-

mation for better understanding of nonlinear processes in these circuits. A periodical func-

tion that represents the transfer function from any node of the circuit to the phase at the

output is defined. Since the process described by this function is linear time variant, the

above mentioned phase sensitivity function is dependent on both the launch time and the

observation time. Its periodicity allows for a decomposition in a Fourier series and the rms

value of the periodical function can be calculated by applying Parseval's relationship. The

rms value of the transfer function from each input node of the oscillator is cumulated to the

total phase noise. The practical importance of this approach is that it provides the designer

with creative means of exploring the oscillator sensitivity to phase noise.

C w R 4: PHASE NOISE iN OSCILLATORS

One exploratory methoci is the use of state space analysis. This is the basis of cir-

cuit simulators for transient analysis. The state vector for a linear time variant system is

described by the mauix equation

~ ( t ) = A(r) X(r) + B ( t ) (4.2 1)

where, unlike a linear time invariant system, matrices A and B are time dependent. For an

oscillator at steady-state, the state vector is periodical with periodicity T = (2n)/oo,

where oo is the angular frequency of oscillation. The state vector is usually described by

the voltages across the capaciton (vc's) and the currents (iL's) through the inductors

In order to derive the phase sensitivity function from any node of the system , an

excitation vector B(t) needs to be defined. It is

where i ( q represents the excitation current across capacitor Cl(t) and

~ ~ ~ ( r ) / + ~ rnax represents the excitation voltage in series with inductor Mt). A routine

c m be implemented in a SPICE simulator to determine the phase sensitivity transfer func-

tion from each node, while the oscillator is run in a transient simulation over one cycle.

Once the phase sensitivity function is detemùned, the excitation vector B(t) is applied,

where the values of the vector are replaced with the noise c m e n t or voltage that is present

at each node of the network. While this method is the most accurate, it still does not pro-

vide any information about noise sensitive points in the oscillator.

CHAPmR 4: PHASE NOISE IN OSCILLATORS

The method that provides such important and usehl information in the design pro-

cess as to which elements are the phase sensitive ones, is described next. A pulse test gen-

erator is placed consecutively for each of the noise generators in the circuit. Special

attention needs to be paid to ensure that the amount of injected charge is small enough so

that the phase response is a linear hinction of the excitation. This will also ensure that the

amplitude perturbation is very small and there is negligible AM to PM conversion. One

complete transient cycle needs to be pulsed with the test generator, and the sampling fre-

quency should be large enough to ensure that there are no aliasing errors. A detailed

description of the method is provided in section 4.4.2. This method provides the phase sen-

sitivity function as a periodic function that shows the sensitive nodes of the circuit, and the

time points over a cycle when they are the most sensitive. If the test generator is imple-

mented behaviorally, then the design optimization c m be iterative. Useful information is

derived from both the time dornain phase sensitivity functions and their harmonic content.

The harmonies are used for caiculation of the total phase noise by applying Parseval's rela-

tionship.

4.3.3 Techniques for Reduction of Phase Noise Generated by Nonlinearities

A method of reducing the phase noise level is to symmetrize the phase sensitivity

function for each node of the circuit. This has the effect of reducing its harrnonic content.

The VCO in fig. 4.7 makes use of this technique. PMOS transistors M3, M4 are configured

as active loads with positive feedback and they improve the syrnmetry of the phase sensi-

tivity functions at the drains of Ml and M2.

Exploring the phase sensitivity allows for optimization of the feedback ratio n of

the VCO in fig. 4.1. A detailed analysis of the optirnization process will be presented in

section 4.4.2. for a topology similar to the one in fig. 4.1, which in addition benefits from

having an AGC loop. The AGC loop not only provides an increased degree of freedom in

optirnizing the ratio n, but it also reduces the AM noise components within the loop band-


width.

The technique of sampling the collector shot noise of the ampliQing transistor and

feeding it back to the transistor base via an AGC loop was recentiy reported [4.16] to

reduce the phase noise level by as much as 4MB. The oscillator schematic is presented in

fig. 4.10. It is basically a Clapp configuration. The low frequency collector shot noise of

Q , is sarnpled by resistor R I , amplified by transistor Q2 and fed back to the base of QI.

There is a 180' phase inversion around this loop such that any increase in the collector shot

noise will reduce the base biasing point of QI. This noise caricellation technique is usefùl

for noise components of frequencies less than the AGC loop bandwidth. The reported

reduction in phase noise is 4ûdB at 1ûûkHz offset from carrier.

Fig. 4.10, VCO with noise-feedback cancellation.

4.4 DESIGN OF A LOW NOISE LOW POWER VCO WITH AUTOMATIC AMPLITUDE CONTROL FOR WIRELESS APPLICATIONS

4.4.1 Design of a High Frequency VCO with Automatic Amplitude Control

This work describes the analysis and irnplementation of a monolithic VCO with

automatic amplitude control (AAC) which is part of a one-chip transceiver dedicated for


dual-band cellular systems [4.5]. The VCO is capable of operating from 3ûûMHz to

1.2GHz using different resonators. The measured phase noise level is -1OodBcMz at

lûûkHz offset fiom a 8ûûMH. carrier.

The presentation starts with a description of the VCO and the AAC circuits with

emphasis on the critical aspects of the design. Section 4.4.2. presents the phase noise anal-

ysis of the circuit done in order to help identifj the important noise sources in the circuit.

Based on these results, the optimized design is discussed. In section 4.4.3., the experimen-

ta1 data is compared with simulations. The last section summarizes the conclusions drawn

from this anaiysis.

a. Practical design considerations.

A simplified block diagram of a VCO with integrated active circuitry and an exter-

na1 parallel resonator is presented in Fig. 4.1 1.a The actual resonator is cornposed of the

inductor LI and varactor CRl. Rp models the losses in the inductor, Cb the parasitic

capacitances of the inductor and the board, L2 the inductances of the bond wire and pack-

age lead and C, the parasitic capacitance of the transconductor. The transconductor G ,

dong with positive feedback capacitors Cl and C2, provides the negative resistance

needed to compensate for the losses in the tank. When the osciilator reaches steady state,

the loop gain equals one and the following relationship holds

where n = Cl + c2

Cl and G, is the large-signal transconductance.

To ensure proper start-up of the oscillator, the small-signal transconductance is typ-

ically chosen to be 3 to 4 times larger than the largesignal G, . This condition imposes a


design restriction on the feedback ratio n . As will be discussed later in this paragraph, the

value of n for optimum noise performance is different than that needed for proper start-up.

One approach to ensure proper oscillation start-up while maintaining the optimum feed-

back ratio n for noise performance is to implement an oscillator with AAC which forces

the transconductance to the value needed to provide constant oscillation amplitude.

The circuit in fig. 4.1 la) has more than one resonance mode, as becomes evident

when the equation for the total admittance of the circuit. Y,, seen by the transconductor is

written

where Cpl = C + Cl - C2 P c1+c2-

' , the fundamental parallel mode is given by Assurning sL, << - v

There is a second spurious mode associated with

which is due to the parasitic bond wire and package inductance L2. The addition of resistor

R, shown in fig. 4.1 1 b) damps the spurious oscillation mode and has negligible effect on

the fundamental mode f4.51. However, care needs to be taken in the design, since too large

a value of R, degrades the noise performance of the oscillator.


Fig. 4.1 1 . a) Sirnplified diapnm of a Voltage Controlled Oscillator.

Fig. 4.1 1 .b) Voltage Controlled Oscillator with damping resistor Rs.

6. Design of the VCO with AAC.

The schematic of a differential VCO with AAC is shown in fig. 4.12. The design

considerations discussed above are implemented here. L, and L, - in fig. 4.12 represent the

parasitic bond wire inductances. R I and R2 are used to damp the spurious oscillation

mode. Capacitors CI , C2 and C3, C4 provide positive feedback with ratio n as shown in

equation (4.24). where Cl = Cj and C2 = C, . In order to provide a wide frequency range

of operation, the value of these capacitors has to be minimized. However, their minimum 1 1

value is limited by requinng that xc,, u r, , in order to minimize the excess phase

shift at lower operating fkequencies.

CHA.TER 4: PHASE NOISE IN OSCLLATORS

Fig. 4.12. Schematic of the VCO with AAC.

The AAC function is perforrned by the following blocks in fig. 4.12: a high fre-

quency rectifier, a low-pass filter, a differential-to-single ended amplifier and a voltage ref-

erence. The output from the high frequency rectifier is low-pas filtered and provides the

inverting input of the differential amplifier a DC signal proportional to the oscillation

amplitude. This signal is compared with the reference voltage. With the use of replica bias

circuits for the voltage refereiice and the rectifier, the two DC voltages track very w e l over

process and temperature. R14 provides negative feedback for the differential amplifier in

order to maintain constant gain. R, is chosen to be larger than R I S , so that the sensing

input of the amplifier is initially negative with respect to the reference input.

The AAC circuit initially forces a large curent in transistor Q3 to ensure proper

start-up even when the small signal l w p gain of the VCO is as low as 1.5 times the steady


state loop gain. This aiiows the flexibility of optimizing the feedback ratio n for minimum

phase noise levels largely independent of considerations for proper oscillation start-up. in

steady-state operation the AAC loop forces the DC signal provided by the rectifier and the

low-pass filter at the sensing input to uack the reference level applied at the reference

input. This leads to the second advantage of using the AAC circuit of enabling the VCO to

provide constant output power independent of the resonator Q and temperature variations.

As will be discussed in section 4.4.2.. the low-pass filter provided by R , - C, is very

important in filtering the Low frequency noise generated by the AAC circuit.

4.4.2 VCO Phase Noise Analysis.

In the phase noise analysis of this design, the oscillator is regarded as a time-variant

system operating under large-signal conditions. The unit impulse response for excess phase

defined in [4.4] as the response of the phase of the oscillator to a unit impulse applied at a

node in the system is used in this analysis. The excess phase is then given by

w

Since the system is Ume variant, h&, 7) depends on both launch time 7 and

observation time t and it is periodic with respect to the launch time. By replacing i (r) in

equation (4.28) with the equivalent noise source of each individual node, the phase noise

contribution of each node can be calculated 14.151.

In order to explore the oscillator excess phase response, each node of the circuit

needs to be excited at evenly distributed time steps of the oscillation period. Due to the high

Q nature of the circuit, the excitation will induce nnging. Therefore, it is necessary to allow

for sufficient time for the system to settle before the next impulse is applied (Tse,,le). The

sequence in which the impulses are applied is shown in fig. 4.13a). The amount of injected


charge needs to be smali enough to ensure a linear phase response especiaily because

excessive ringing can produce AM - PM conversion errors. In this analysis, the linear

response of the excess phase to the injected charge has ken checked for each node of inter-

est.

A behavioral test generator (fig. 4.13b) was implemented to provide the automatic

time steps described above. The clock input of the first D flip-flop (DFF1) is connected to

the VCO output so that this fiip-flop is triggered by the positive edge of the oscillation sig-

nal. Capacitor Cs and current source I I generate a rarnp which starts from OV and reaches

1 V after time (M Tosc) > TSetfIe , where Tas, is the oscillation period and M is an integer

chosen such that the osciilation waveform has settled before the next pulse is applied.

The ramp generator is reset by the first positive-going zero crossing of the oscilla-

tion. The ramp is then compared in COMP 2 with a staircase voltage ( V, ) which is incre-

mented at each M oscillation periods. The magnitude of the voltage step of V2 needs to be

very accurate since it determines the time when the impulse is injected into the oscillator.

The voltage step is set to be ( V)'M , where N is the number of pulses to be injected. In

this way pulses are injected with a period equal to (M + h) T,,, (fig. 4.13a).

The time when V2 is incremented is not critical as long as it is done after the fust

oscillation period when the triggered ramp is compared with the staircase generator. Fig.

4.13~) shows the injection points into the oscillator. Current source Ibias is injected to sim- - 2 date the effect of the noise ibios generated by the bias generator and the AAC circuit. Cur- -

2 rent source Ic simulates the effect of the collector shot noise ic of transistor QI, voltage - source Vrb the effect of the noise voltage v2 generated by rb , and cumnt source I the

'b - Re,

effect of the resistive losses in the resonator, with a noise current . The noise densities

are as follows


Fig. 4.13. Sequence of pulses used to excite the oscillator. b) Block diagram of the behavioral test

generator; c) VCO test points for phase sensitivity to injected charge.

109


The second D flip-flop (DE 2) in fig. 4.13b) is used as a monoflop which generates

a pulse shown in fig. 4.14. The spectral energy of this pulse is dmost constant from DC to

25GHz which is sufficient for this design that uses a bipolar process with f, = 2SGHz.

Fig. 4.14. Impulse shape.

The collector shot noise of transistor Q, is evaluated at the peak of the collector cur- - 2

rent ( i,, ,, = 1.6mA ). The cyclostationarity of i, . which is due to the time-varying nature

of the collector current of QI, will be considered further in this analysis. The base resis-

tance rb of QI, is 8.6R. The losses in the resonant circuit are expressed by the equivalent

resistance Req. The total resistive loss in the resonator is calculated across the nodes "out"

and "outb (fig. 4.12) and it has the value 2 Req = 720R. The on-chip resistors R , and Rz

have the minimum vaiue required to damp the parasitic osciilation. The degradation in

phase noise at lOOkHz frequency offset fiom a 800MHz carrier due to these resistors is no 2 more than 0.5dB. The spectmm for ibias is simulated using small-signal SPICE analysis

and it is shown in fig. 4.15.

C-R 4: PHASE NOISE JN OSCILLATORS

Fig. 4.15. Tai1 cument noise spectnim.

The behavioral test generator was used to inject 64 pulses as shown in fig. 4.13a).

The VCO was run at 8ûûMHz while the test generator was applied. The number of sarnples

per period was chosen to be large enough in order to minimize aliasing effects. The excess

phase induced by each pulse, h&, s) , generates a periodic function with respect to the

launch phase of the pulses.

Fig. 4.16 shows the function ha, ,b,as (1, T) for curent pulses injected at the tail of

the emitter coupled pair. This function has a periodicity which is half the oscillation period.

In order to obtain more meaningful information on the phase sensitivity for perturbations in

the tail current of the VCO, the function ha, ,bis, (1.7) (fig. 4.16a) is plotted together with

the oscillation output waveform (fig. 4.16b). It can be seen that for perturbations injected

around the zero crossings and the peaks of the oscillation, the phase sensitivity is close to 2 i - 1

zero and it reaches its maxima for 7 - T ,,,, where i = 0, 1, ..., n.

C w R 4: PHASE NOISE LN OSCILLATORS

Fig. 4.16. a) VCO output waveform; b) Simulateci function ha, lb,ax(t, r) .

The SPectWm of ha, ,hius (t, r) is shown in fig. 4.17. As expected, there are harmon-

ics at multiples of double the oscillation frequency. The harmonics mix with the noise

around these frequencies and contribute to the total phase noise. For calculation of the

phase noise contribution from the tail current, the Fourier coefficients Ck of ha, g,a5(r, 5 ) . need to be computed. The phase noise contributed by the tail current is given by the sum of

the squares of the phase errors from each harmonic of h , ,bis, (t, r) [4.4] and is

2 where ibias(k, Ao)/(An is the noise density of the bias circuitry at Aw offset from the

k th harmonic of the oscillation frequency. In this analysis the sumrnation is performed

over the first five harmonics. Higher order harmonics have insignificant contribution to the

112


phase noise.

Fig. 4.17. Frequency spectmm of h 0, lbi_(" TI .

Of particular interest is the DC component. coefficient C o . The corner frequency

where the 1 / p region of the phase noise intersects the 1 /f2 region is given by

where o, ,f is the 1 /f comer frequency of the tail current noise. Since o /f is 200kHz,

equation (4.33) predicts a value for oc of 3kH:, which is in agreement with the phase

noise measurements. In order to lower oc, the comer frequency of the low-pass filter, set

by R - C7 * can be decreased by increasing C, .

A sirnilar analysis is carried out for the collector shot noise, the base resistance ther- - mal noise of QI and for the thermal noise i: . Thermal noise generated by the base biasing

c'7

CH-R 4: PHASE NOISE IN OSCILLATORS

resiston, Rq and R5 in fig. 4.12, is shunted by the relatively low irnpedance seen across

capacitors C, and C4 respectively at the frequencies of interest, and is therefore neglected.

While the noise spectral density of the base resistance and the parallel resistance of the res-

onator are assumed to be stationary, the effect of cyclostationarity needs to be considered

for the collector shot noise. For this, the unit impulse response function ha,, (t, r) is mul- C

tiplied by the collector current waveform and normalized to the collector peak current. To

account for the cyclostationarity of the collector shot noise, an effective periodic function

hoel+ I , 7) is defined

in the above equation i, ,, is the same as in equation (4.29). The functions

h o ) and ha, ,,(t, t) are shown in fig. 4.18. It cm be seen that the effect of cyclos-

tationarity is to reduce the coUector shot noise contribution. hocf-t, 7) has a p e n d equal

to the oscillation p e n d Again, in order to see the effect of this noise source, the oscillation

output waveform and the collector current of QI are plotted in the same figure. The func-

tion h@,,+t, r) reaches its maximum when the collector current is close to the peak and it

reaches the minimum when i, is around zero.

The plot of fig. 4.18b) shows the collector current going negative for a small frac-

tion of the oscillation period. This is due to the displacement current flowing through the

collector-base capacitance CI,. The intemal collector current which generates collector

shot noise does not go negative. This displacement current, however, is a negligible error in

the noise estimation when the total collector current is considered. The Fourier components

of hoeffir, t) show that the coilector shot noise is mixed mostly with the fxst and second

harmonies of the oscillation frequency to contribute to the total phase noise. However, the

collector shot noise of QI is the dominant noise contributor (as will be seen below) and an

optimization based on the feedback ratio n was performed. To do this, the ratio n was var-


ied and the rms value of haef - t , r) was calculated using Parseval's relation

2 . RMS(t, r)12 = 2 ~ : -

(continous line) and hae,$t, t) (dashed line).

The frequency spectrum of haeJ-t, r) is shown in fig. 4.19.


Fig. 4.19. Frequency spectmm of ho,,-kt, r) .

The simulations show that if the feedback ratio n is too low. h o e , t , T) increases

and so does the contribution to the total phase noise. This is due to the fact that the base-

emitter junctions of QI and Q2 are overdriven and although the function ha,, ( t , T) c

rernains unchanged, the collector cwrent approaches the fonn of a square wave, leading to

an increase in hoef/t, T) . For very large values of n the AAC circuit forces more bias cur-

rent into the VCO and both the collector shot noise of QI (equation (4.29)) and the taii

noise current (fig. 4.15) increase. Although the phase noise level does not degrade for val-

ues of n higher than 6, this comes at the expense of increased power consumption. The

phase noise Ievel achieved for a given power consumption can be used as a figure of merit

which is defined as

FoM = ( S / N ) [ d B c / H z j PDc[m W]

Both the phase noise level and the figure of merit as a hinction of the feedback ratio

n are shown in fig. 4.20. It c m be seen that the optimum feedback ratio for this design is

around 4.5. Using the optimum feedback ratio, the small signal loop gain is:

where Ibios = 1 -6mA .

Fig. 4.20. Phase noise (continuous line) and figure of merit (dashed line) versus feedback ratio.

This analysis shows that, with the use of the AAC circuit, phase noise optimization

(through chousing the optimal feedback ratio) can be accomplished independently while

ensuring proper oscillator start-up.

A sirnilar analysis was carried out for the thermal noise generated by the base resis-

tance of transistor Q1 and the equivalent resistance of the resonant tank. Table 4.2 gives the

contributions of various noise sources to the total phase noise of the VCO at IOOkHz offset

from a 800MHz carrier. These values are given as noise-to-signal ratios. The contribution

C-R 4: PHASE NOISE IN OSCXLLATORS

of the base resistance thermal noise is sirnulated to be less than 5% of the total phase noise.

The noise contributed by the resonator is more significant (the loaded Q of the resonant

tank is simulated to have a value of 16) with the dominant noise contributor k i n g the col-

lector shot noise.

Although the noise contribution from the tail current is not important at this offset

frequency, it becomes the major noise source at offset frequencies less than 3 k H z .

The factor of two for some of the noise sources in Table 4.2 accounts for noise

sources that are considered twice due to the circuit symmetry [4.15]. The sum of these val-

ues gives a noise-to-signal ratio of -106.2dBc/Hz.

Table 4.2: Noise contributors to total phase noise.

- Collecter shot noise i S / ~ f

A phase noise simulation was aiso carried out using SpectreRF as a comparison. It

cm be seen in fig. 4.2 1 that the results are within 2dB in the 1 /f2 region of the specuum.

SpectreRF predicts a phase noise level of - 108dBcMz at l û û W offset. However, the cur-

rent version of Spectre-RF did not predict the 1 /P region of the spectmm, which was cal-

culated in the above analysis and confirmed by measurements.

- 7

Noise from tank losses i i c q / A f

- 2 Tai1 curent noise ibiaS/A f

- 2

Noise from base resistance v,,/Af

2 - 0.816 - 10-Il 68%

2 - 0.256 - 10-l1

0.168 - 10-l1

21%

7%

2 - 0.05 - 10-1 l 4%


Fig. 4.21. Cornparison of the phase noise calculated with phase noise simulated in SpectreRF.

4.4.3 Measurement Results.

The VCO with AAC was fabricated in a bipolar process with f , = 25GHz . The

micro-photograph of the circuit is shown in fig. 4.22. The VCO can operate from 300MHz

up to 1.2GHz with different resonaton. The output specûum is shown in fig. 4.23. It c m be

seen that the second harmonic is 43dBc and the third harmonic is -58dBc. The effect of

quasilinear operation of the VCO made possible by the AAC loop is to reduce the level of

harmonic distonion. For a given resonator, the VCO with AAC reduces the third order har-

monic distortion by 6dB when compared to a VCO without AAC. The phase noise is

- 106dBc/Hz at lûûkHz offset for a carrier frequency of 800MH2, which is in agreement

with the analysis presented (fig. 4.24).

The VCO core consumes 1.6mA from a 2.7V power supply. The remaining circuits

used for the AAC (rectifier, voltage reference and amplifier) consume 0.25mA. If better

phase noise performance is desired, only the current consumption in the VCO core needs to

CIiAPTER 4: PHASE NOISE [N OSCILLATORS

be increased. while the consumption of the AAC circuits remains unchanged. However,

the optimization procedure described above needs to be reiterated, since the optimum feed-

back ratio could change.

Fig. 4.22. Photograph of the VCO with AAC.

D e l t o 1 [ T l l RBW 2 k H z R F A t t 30 aB -43 1 5 dB V8W 2 k H z M i r e r -20 d R n

-2 1 . 1 d& 1 . 0 1 853645 G H z 250 m¶ U n ; t d a n

Crnter 2.439329384 GHz 298.9704041 MHz/ Span 2.888704041 G H z

Fig. 4.23. VCO output spectrum.

120

C m R 4: PHASE NOISE IN OSCLLATORS

Fig. 4.24. Measured phase noise.

In conclusion. the work in this chapter explores the possibilities of developing a

low noise, low power VCO with capabiiities for wireless applications. An automatic ampli-

tude control circuit was irnplemented which allows the choice of the optimum oscillator

feedback ratio for noise performance without k i n g constrained by start-up considerations.

At the sarne time, the automatic amplitude control allows proper VCO operation for a wide

range of the resonator quality factor. A novel method was used to study the phase noise

performance of the VCO. The method predicts results which are close to the measurements

and allows the designer to obtain detailed information about the processes which contribute

to oscillator phase noise.


REFERENCES

D. B. Leeson, "A Simple Mode1 of Feedback Oscillator Noise Spectrum," Proc. IEEE, vol. 54, pp. 329-330, February 1966.

W. P. Robins, Phase Noise in Signal Sources (Theory and Applications), IEE Telecornmunications Series 9, 1969.

F. X. Kaertner, "Analysis of White and P Noise in Oscillators," International Journal of Circuit Theory and Applications, vol. 18, pp. 485-519, 1990.

A. Hajimiri, T. H. Lee, "A General Theory of Phase Noise in Electrical Oscilla- tors," IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, February 1998.

M. A. Margarit, J. L. Tharn, R. G. Meyer, M. J. Deen, "A Low-Noise Low Power VCO with Automatic Amplitude Control for Wireless Applications," IEEE Journal of Solid-State Circuits, VOL 34, no. 6, pp. 76 1-77 1, June 1999.

M. A. Margarit, J. L. Tham, M. J. Deen, R. G. Meyer, "Noise Analysis of a VCO with Automatic Amplitude Control," Proceedings of CICC99, pp. 38 1-384, May 1999.

T. Aiuens, A. Hajimiri, T. H. Lee, "A 1.6GHz OSmW CMOS LC Low Phase Noise VCO Using Bond Wire Inductance," International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 69-7 1, July 1997

J. Cranincks, M. Steyaert, "A 1.8GHz CMOS Low Phase Noise VCO with Pres- caler," IEEE Journal of Solid-Srate Circuits, vol. 30, no. 12, pp. 1474-1482, December 1995.

M. Steyaert, J. Cranincks, " 1.1GHz Oscillator Using Bondwire Inductance," Electronics Letters, vo1.30, no.3, pp. 244-245, February 1994.


[4.10 ] N. M. Nguyen, R. G. Meyer, "A 1.8GHz Monolithic LC VCO," IEEE Journal of Solid-State Circuits, vo1.27, no.3, pp. 444-450, March 1 992.

[4.11] J. Cranincks, M. Steyaert, "Low-Noise Voltage-Controlled Oscillators Using Enhanced LC Tanks," IEEE Trans. on Circuits and Sysrems II: Analog and Dig- ital Signal Processing, vo1.42, no. 12, pp. 794-804, December 1995.

[4.12] F. Piazza, Q. Huang, "A 12mW Triple-Conversion Receiver for GPS," ISSCC Dig. of Tech. Papers, pp. 286-287, February 1996.

14-13] A. Springer, R. Weigel, E. Kristan, P. Sehrig, J. Fenk, "Design and Performance of a Fully htegrated 4 GHz VCO with High Tuning Range for GSM/PCN Mobile Communication Systems", Proceedings of M'IT-S European Wîreless Conference, Amsterdam, pp- 287-29 1, September 1998.

[4.14] J. Smith, Modem Cornmunicarion Circuits, McGraw-Hill, Inc., chapter 7, 1986.

14.151 C. D. Hull, R. G. Meyer, "A Systematic Approach to the Analysis of Noise in Mixers." IEEE Trans. Circuits and Systems-1, vo1.40, no. 1 2, pp. 1 69- 176, December 1993.

14.161 U. L. Rohde, F. Hagemeyer, "Feedback Technique hnproves Oscillator Phase Noise." Microwaves and RF, pp. 6 1 -69, November 1998.

CmPTER 5: MONOLITHIC PHASE-LOCKED LOOPS ...

CHAPTER 5

MONOLITHIC PHASE-LOCK LOOPS FOR COMMUNICATIONS

APPLICATIONS

5.1 INTRODUCTION

Phase-lock techniques have been studied extensively in the past decades and there

are currently numerous areas which apply these techniques. Communications, industrial

automations and robotics are among the outstanding fields which apply phase-lock tech-

niques. The recent advances in microelectronics open remarkable opportunities to wireless

communications technologies. The PLL applications targeting this field have severe

requirements in terms of achieving very low phase noise levels and high spectral purity

with a limited power budget.

The original contribution of the work described here on phase-lock techniques

resides in the research and development of a special type of PLL, the Frequency Transla-

tional Loop (FIL), used in transmitters of wireless transceivers. The noise and linearity

performance of this implementation are such that it can be readily used in the highly

demanding wireless applications. such as GSM (Global Satellite for Mobile). In addition,

the analysis methodology for this new type of PLL is developed for the first time in this

work and there is no related published work for the analysis of the FïL.

5.2 REVIEW OF LITERATURE AND THEORY OF PHASE-LOCKED LOOPS.

5.2.1 Review of PLL Literature.

Since the early description of a PLL in 1932 [5.1], extensive research has been car-

ried out, and there are many important publications conceming theoretical aspects as well

as design issues.

CH-R 5: MONOLITHIC PHASE-LOCKED LOOPS ...

An outstanding work on phase-lock techniques applied to the design of radio

receivers is Blanchard's book [5.2], which provides a lot of usefùl numerical examples and

plots. Viterbi [5.3] has done advanced theoretical work on the nonlinear analysis of PLL's

and has introduced the concept of phase planes for nonlinear analysis. A very useful book

for PLL designers is written by Gardner [5.4]. Its usefulness resides in the clear and con-

cise theoretical presentation of the topic combined with good design examples and appli-

cations. Also, good design practice cm be acquired from the books by Best [5.5] and

Rohde [5.6]. A collection of useful PLL papers has been recently published by Razavi

[5.7]. It includes remarkable papen on al1 aspects of design: basic theory. building blocks,

modeling, genenc PLL's and clock recovery circuits.

Recent developments in monolithic technology allow for development of inte-

grated phase-locked loops which operate in a frequency range from bundreds of MHz to

more than 2GHz, while achieving remarkably low phase noise performance. In Table 5.1,

several PLL implementations are presented in terms of operating frequency, phase noise

level and power consumption.

Table 5.1: Cornparison of PLL performance

Ref [5.8]

Ref [5.9]

Ref 15.1 O]

Ref [5.11]

Operating frequenc y

Phase noise Process

2GHz

2GHz

900MHz

6GHz

25GHz Bipolar

25GHz Bipolar

25GHz B ipolar

12GHz BiCMOS

- 12OdBc/Hz@400KHz

- 120dBc/Hz@400KHz

- 120dBc/Hz@400KHz

-7SdBc/Hz@ 1 KHz

Tech. data

Power consump-

tion

0.8 p emitter width

NIA

NIA

0 . 8 ~ channel length

54mW

140mW

84mW

6ûmW

C m R 5: MONOLITHIC PHASE-LOCKED LOOPS ..,

5.2.2 Basic Theory of the Phase-Locked h p .

Several topics wiil be considered in this section which are intended to present the

basic principles of operation of a PLL.

The first topic regards the transfer function of the loop in locked condition and the

concepts of loop order and type will be introduced. Then the tracking, as well as the lock-

in and pull-out behaviour of the loop will be analyzed.

For deriving the basic transfer functions, the elementary loop of fig. 5.1 will be con-

sidered. The input signal has a phase ei(t ) and the VCO output has a phase output 8,(t) . For the following derivation it is assumed that the loop is lwked and its charactenstic can

be linearized

dû, / dt =K,v,

Fig. 5.1. Basic block diagram of a PLL.

The output voltage of the phase detector is

Vd = Kd(Bi - 0,) ,

where Kd is the phase detector gain. The loop filter transfer function is F(s) and the VCO

output frequency is

C m R 5: MONOLITHIC PHASE-LOCKED LOOPS ...

where Ko is the VCO sensitivity and v, is the VCO control voltage. By taking the Laplace

transforms we obtain

These equations are used to provide the loop vansfer function H ( s ) , given by

As will be seen later in this presentation, the phase error defined as 0, = e, - 0, is

an important parameter, which is always considered in the design of a locked bop. From

equation (5.6) we can derive the tram fer function of the phase error

Equations (5.6) and (5.7) are denved for a very general case, where no assumption is made

regarding the loop filter.

For F ( s ) = 1 , where the phase detector output drives the VCO directly, the

denominator of equation (5.6) is a first order polynomial in S. This loop is a first-order

PLL. The type of the loop is by definition a number equal with the number of ideal inte-

graton in the loop. For a first order loop there is one ideal integrator in the loop, the VCO.

Therefore, a fust-order loop is always a type one loop.

Let F(s) have a pole and a zero like in fig. 5.2. Then the denominator of equation

(5.6) is a second order polynomial in s, and the loops using this filters are called second

127

C-R 5: MONOLITHIC PHASE-LOCKED LOOPS ...

order loops. The passive filter in fig. 5.2a) employs a non- ideal integrator, therefore a loop

built with this filter is a second-order type one loop. The active filter of fig. 5.2b) employs

an ideal integrator, and the loop built with thîs fdter is a second-order type two hop.

Fig. 5.2. Filters used in second order loops.

In fig. 5.2. a) is a passive filter with the transfer hinction,

In fig. 5.2, b) is a active filter with the transfer function

K R , + 1 sT2 + 1 and for A very large F(s) = - = --

sCR, st I

For the passive filter the closed loop transfer function is

For the active filter the transfer function k o m e s

CHAPTER 5: MONOLKHIC PHASE-LOCKED LOOPS ...

Equations (5.10) and (5. I l ) can be rewritten as

where on is the natural frequency of the loop and 6 is the damping factor. The root locus

for equations (5.10a) and (5.1 la) describes a semicircle in the left half plane of radius O,,

and for a particular value of the damping factor, the complex conjugate mots f o m an angle

with the horizontal ax is y such that cos y = & . Thus, it is obvious that for c + O , the corn-

plex conjugate poles meet the jo axis and the loop is unstable (the loop is also called

underdamped). For & = 1 , the poles become real and the loop becomes heavily damped.

The error response of the loop is an important charactenstic of the loop. For a sec-

ond-order loop the error response is

The error response is plotted in fig. 5.3 for a damping factor c = 0.707. A high-

pass characteristic is obtained, which means that the loop tracks signals with frequency off-

set smaller than a,, but can not track signals of higher frequency.

The transfer function H ( s ) has a 3dB bandwidth 0 3 d e . By sening

1 H U W ) ~ = 0.5 and solving for o , we derive

CHAPTER 5: MONOLïïHIC PHASE-LOCKED LOOPS ...

112 0 3 d ~ = 0,,[2&~+ I + J(252+ 112+ 11 - (5.13)

Equation (5.13) is plotted in fig. 5.4 for typical values of c.

Frequency (dm,,)

Fig. 5.3. Error response of the locked loop.

Fig. 5.4. Three-decibel bandwidth of a second-order loop.

C w R 5: MONOLITHIC PHASE-LOCKED LOOPS ...

An important parameter related to the loop stability is the loop gain, K. The loop

gain K is the angular frequency for which the open loop gain becomes unity. This value is

found by solving the equation

Using the above definition, we derive the loop gain (using equation (5.9) with A very large)

for a second-order loop which employs an active filter

For loop stability considerations, the time constant 7, is designed such that

o - r2 D 1 at the frequency value which satisfies equation (5.15). Therefore, the solution

for equation (5.15) is

A similar derivation yields the same expression for the loop gain in a second-order

loop which employs a passive filter. From the Bode plot of fig. 5.5 it can be seen that the

loop stability cnteria is met if the phase lag is less than 180' at the frequency K. where the

loop gain is unity.

The dc loop gain is another loop parameter. It will be disscussed later that the

higher the dc loop gain, the better the tracking capability of the loop. The dc loop gain is

defined as the loop gain at zero frequency

K, = KdK,F(0) . (5.17)

C-R 5: MONOLiTHIC PHASE-LOCKED LOOPS ...

Fig. 5.5. Bode plot of a second order loop.

For a kt-order loop F(s) = 1 and the loop gain is equal to the dc loop gain. This

is not a desirable situation, because the dc loop gain needs to be as large as possible, but the

loop gain is usually dictated by different constraints, such as minirnization of noise.

For a second-order loop the parameters can be designed separately as can be seen

from the set of equations: K, = KdK,A and K = Kd K ~ T 2 = 1

b c k - i n Range and Tracking Per$ionnance of Phase-locked Loops. Linear behavior.

In order to study tracking performance of PLL's, the phase error 8, that results

from a specified input Bi is examined. A smdl phase error is considered a criteria of good

tracking performance. If the error becomes so large that the VCO skips cycles, the loop is

considered to have lost lock. The phase error is given by equation (5.7) is

132


The analysis here focuses on the steady-state error remaining after the transients -

have settled out. These errors are evaluated by means of the final value of Laplace trans-

forrn using

lim 8Jt) = lirn sf3Js) . t - + - s+O

Applying the final value theorem to the phase-error equation (5.18), the following

expression is obtained

Next, the tracking performance will be examined for three generai cases:

a) tracking performance when a phase step ABi is applied;

e,O) b) tracking performance when a frequency step Ami = 7 is applied; and

w;(t) O;(f) - C) tracking performance when a frequency ramp 6hi = - - - t

is applied. 2r2

In the case of a phase step, equation (5.20) together with Bi(s) = (ABi)/s yields

lim O,(!) = lirn s A 8 = o . t 3 = s -, 00 + K,&F(s))

This result shows that the loop will eventually track out any change of input phase.

There is no steady state error resulting from a step change of phase. This result is general


for any loop order provided that F ( 0 ) > O .

For a frequency step, Bi(s) = ( ~ o ) / s ~ . Using equation (5.20), we get

Am - AW lirn B,(r) = lirn

1 3 - r 4 O(S + KoKdF(s)) - KoKdF(0) .

The product KoKdF(0) is called the DC loop gain and is denoted Kv . The incoming sig-

nal is usuaiiy different than the free-running frequency of the VCO. The frequency differ- Am ence A o will cause a static phase error 0, = - . Kv

For a fnst-order loop, Kv = K,Kd = K. and the static phase error is large, causing

loss of track for a large frequency step. A second-order loop with active loop filter bas

K , = K,KdF(0) = K,KP and the static phase error can be almost zero for very large A . f2 For this loop, Kv P K = K K -, thus allowing for the static phase error to be minimized,

0 d f ,

while the loop gain K can independently be chosen to minimize the noise bandwidth.

Next, we assume that the input frequency is linearly changing with a rate A&

rad/sec2. Then the transformed input phase is B,(r) = A&/s~ and the static phase error

will grow without bound. However, for a second-order loop, an active filter can be used

such that the static phase error is negligible. Under this assurnption, an ideal integrator

with infinite Kv is an approximation for the loop filter. In reaiity. even though Kv is finite,

it is large enough to minimize the static phase error which occurs for a finite time. By using

equation (5.19) we c m derive the acceleration error, or the dynamic phase error for a sec-

ond order loop

Am A o 0, = Iim 0,(t) = lim - - -

t + - s - + o ( s 2 + 2 ~ o , s + o ~ ) 0; -

The dynamic phase error in a fmt order loop grows without bound. This means that

C-R 5: MONOLiTHïC PHASE-LOCKED LOOPS ...

a first-order loop c m not track a frequency rarnp. Instead a third order loop of third type

can track a frequency ramp without steady-state acceleration error. Due to this property,

third-order loops are usehil in tracking satellites and missiles, where the Doppler effect

causes the frequency to Vary Linearly.

In summary, a first-order loop can track a frequency step, but offers a poor compro-

mise with the loop gain and therefore with the noise bandwidth. A second-order loop c m

track a frequency ramp, which requires a large value for a,. This compromizes the noise

performance of the loop, because the noise bandwidth is proponional with CO,. In a third-

order loop, the frequency rarnp can be accornodated together with small noise bandwidth.

Nonlinear behavior.

The preceding derivation is based on the assumption that the phase error is suffi-

ciently small to allow for a linear behavior of the bop. This assumpiion is less useful as the

error increases untii the loop drops loses lock and the loop behaves nonlinearly.

An important parameter in a nonlinear analysis is the frequency range for which

the loop holds lock. The steady-state frequency liMt c m be derived from equation (5.22) Aw Am

8, = - . For a sinusoidal phase detector, the real expression should be sine, = -. K" Kv

Because the sine fünction can not exceed unity, the frequency step needs to be less than K, .

For a frequency step larger than Kv the loop loses lock. The hold-in range of the loop is

AuH = 4Kv. (5 -24)

Equation (5.24) shows that the hold-in range can be made arbitrarily large for a

second-order loop up to the point where the loop components will saturate.

(equation (5.23)). For a The dynamic error for a second-order loop is 8, = - 0,'

135

CEIAPTER 5: MONOLITHIC PHASE-LOCKED LOOPS ...

A& sinusoidal phase detector, the real expression for the phase error should be sine. = - 0; -

This sets the limit for the maximum permissible rate of change of input frequency to

The loop loses lock if the input frequency rate exceeds this limit. However, for

phase detectors with extended linear spans, the above limits are extended correspondingly.

For example, the limits shown in equations (5.24) and (5.25) are extended by a factor of 21t

when a sequential phase detector with a linear range of f 2x is used. It needs to be men-

tioned here that the transient error can be much larger than the steady-state error, and the

loop can be pulled out of lock on a transient basis by a signal chat could be tracked easily in

the steady state.

Most phase detectors are periodic and thus can not distinguish a phase step of

A8 + 2kx from one of Ag. Therefore, an ordinary loop does not lose lock when subjected

to a phase step of any magnitude.

A frequency step can break the lock. A first-order loop loses lock if the frequency

error exceeds the hold-in limit of equation (5.24). The transient performance of a second-

order loop is studied by Viterbi [5.3] by using a phase-plane portrait. The dynarnics of a

second-order loop is described by a pair of first-order, nonlinear differential equations in

the independent variable of time and the dependent variables of phase error 9,and fre-

quency error 0,. By eliminating the time variable between the two equations, a single sec-

ond-order, nonlinear differential equation that relates phase and frequency errors is

derived. The solutions of the second-order equation are in terms of 8;, versus 8,.

Based on Viterbi's results, there are interesting conclusions regarding the transient

behavior of a second-order lmp. First, we consider a loop with infinite dc gain. This loop

can never lose lock permanentiy. If a large frequency step is applied, the loop unlocks,

136


skips cycles and then locks up again. The phase error is a ringing oscillation for a number

of cycles corresponding to the number of cycles skipped. However, there is a frequency

step lirnit below which the loop does not skip cycles and remains in lock; this limit is

denoted the pull-out frequency, Ampo. The puil-out limits have been computed using the

results from Viterbi's approach. The computed results were empincally fitted with the

relationship [5.4]

for between 0.5 and 1.4.

5.2.3 Building Blocks for PLL's Used in Communications.

It was previously mentioned that phase-lock techniques are widely used in comrnu-

nications. An important and very recent application is in wireless transceivers, where a

PLL functions as frequency up-converter in the radio transrnitter. This type of application

presents the advantage over classical up-converter mixers in that it filters the out-band

noise generated by base-band circuits. The principle is illustrated in figure 5.6. The noise

present at the modulator output is filtered by the phase-locked loop for frequency offsets

from the RF carrier that are in excess of the loop bandwidth. This eliminates the need of

additionai filtering that is used in classical up-converters employing mixers. Elirnination

of additional filtering between the up-converter and power amplifier (PA) helps in reduc-

ing the power consumption, because the in-band insertion loss is typically 2-3dB for these

filters. This means that a classical up-converter would have to provide a modulated carrier

at the RF frequency that is 2-3dB larger than the carrier provided by a phase-locked up-

converter. Moreover, the reduced outband noise provided by this new architecture relaxes

the filtering requirement after the PA, which M e r reduces power consumption. This

class of PLL's is known as frequency translational loops (FïL) and their distinctive mark

consists in employing a mixer in the feedback path.

CHAPTER 5: MONOLITHIC PHASE-LOCKED LOOPS ...

In fig. 5.6, the 1 and Q represent quadrature base-band signals that need to be up-

converted first at an intermediate frequency (IF) and then at the output radio frequency

(RF). The output signal of the single-side band modulator contains the IF carrier modu-

lated by 1 and Q signals. The same signal will be preseni at the N input of the phase-fie-

quency detector when the loop is locked. Therefore, the output of the frequency

translationai loop contains the RF carrier modulated by 1 and Q signals.

i !

i Single-sidc band -

Loopmixer - m. rejeci I

l

Fig. 5.6. Frequency translational loop used in radio transmitters.

The design of a frequency translational loop based on the concept in fig. 5.6, as well

as the analysis of this circuit will be presented in section 5.4.

A different implementation of the sarne concept is presented in fig. 5.7 [5.9]. Here

the single-side band modulator is in the loop. The loop forces the RF-VCO to modulate its

frequency at RF+IQ, where IQ represents the frequency of the base-band signal. The out-

put signal of the RF-VCO is downconverted by the loop mixer at IF+IQ and used to mod-

ulate the base-band signal in the single-side band modulator. Therefore, the output of the

single-side band modulator is the unmodulated IF frequency. This enables the use of dif-

138

C H M R 5: MONOLITHIC PHASE-LOCKED LOOPS ...

ferent divide ratios for the N and R dividers and allows for increased flexibility in choosing

the IF and UHF frequencies of the transceiver. If dividers are needed at the N and R inputs

of the Fn in fig. 5.6, they must have the same divide ratios, since the modulation is

present at the phase-frequency detector inputs.

The FIL in fig. 5.7 has the same filtenng properties for noise at frequency offsets

larger than the loop bandwidth as the configuration in fig. 5.6. In typical applications for

wireless transceivers. the RF frequency is at - 900MHz and the UHF frequency at

- 1300MHz, while the IF is the difference between the first two frequencies. The N and R

divide ratios have typical values from 1 to 8, therefore the phase-frequency detector and

charge pump for these applications are required to run at freqwncies up to 400MHz.

1 Single-side band 1 L _ ~ ! 4 F " a - - - 1

Fig. 5.7. Frequency translational h o p with in-loop modulator.

The use of the loop mixer in FTL architectures allows fine frequency increments

that are required by channel spacing in a transceiver. For example, the channel spacing in a

GSM transceiver is 200kHz. The fine frequency increments are performed while the N and

R dividers have low values, which results in a larger loop bandwidth with fast lock-in.

C m R 5: MONOLlTHIC PHASE-LOCKED LOOPS ...

Typical loop bandwidths for F n ' s have values around 1 up to 2 MHz.

An implementation for the phase-frequency detector (PFD) that is ofken used in fre-

quency translational loops is presented in fig. 5.8 [5.6]. The PFD implementation for fre-

quency translational loops poses suingent requirements on the speed of the flip-flops and

logic gates, as the circuit needs to work at frequencies in excess of 4ûûMHz. One way to

increase the speed of the circuit in fig. 5.8 is to minimize the propagation delay through the

flip-flops and the AND gate. At the same the , the requirement for reduced dead-zone of

the PFD imposes fast rise and fall times for the logic circuits. A good compromise between

speed and power consumption is achieved by using ECL circuits. A PFD implementation

using fast ECL circuits configured as in fig. 5.8 is described in section 5.4.

- > U P Resetable ' D fiip-flop I

I r '

Resetable D fiipflop

" 1 " -

Fig. 5.8. Phase-frequency detector

The UP and DN outputs of the PFD usually drive a tri-state charge pump that has

the following States: it sources a constant current when UP is at logic level "high" and DN

is "low"; it sinks a constant current of the sarne magnitude when UP is "low" and DN is

"high"; it stays in high impedance mode for any other combination of logic levels for UP

and DN.

There are two challenges in the design of a charge pump for frequency translational


loops. The first one consists in the fact that the circuit needs to work at high frequencies,

sirnilar with the PFD. Fast rising and falling edges for the sink/source currents are required

in order to minimize the dead-zone. The second challenge is the fact that the value of the

sink/source currents need to be selectable in order to allow for constant loop gain when the

divide ratio N changes. The charge pump speed should be independent of the sink/source

current value.

A fast charge pump implemenied in CMOS technology is presented in fig. 5.9. The

idea here is to use current mirrors that are faster than conventional voltage switches. The

cument mirrors formed with transistors M l , M2 and M6 are always on, hence there is no

tum-on time required. Output transistors M5 and M9 are switched via transistors M3. M4

and M7, M8, respectively. However, transistors M3, M4, M7 and M8 are very fast, since

they are only required to switch a small amount of current represented by transients in par-

asitic capacitances.

Fig. 5.9. Fast CMOS charge purnp.

For selectable output cunents, transistors M5 and M9 in fig. 5.9 consists of several

devices in parallel. The number of parallel devices that are effectively connected to the

CgAPTER 5: MONOLITHIC PHASE-LOCKED LOOPS ...

current sources Ml , M2, M5 and M6, Mg, respectively, determine the charge pump output

current. However, for a fast response, the rnirroring ratio from M l to M5, or from M6 to

M9 should not exceed the unity for the highest value of the output current.

A design similar to the one in fig. 5.9 in bipolar technologies is usually not possible,

where the lateral pnp exhibits poor frequency performance. A charge pump design using

BiCMOS technology is presented in section 5.4. It will be seen that in a BiCMOS process,

the slow pnp can be replaced by a faster PMOS device.

Usually, fast charge purnps have poor device matching. This is the cause of

increased leakage current in the tri-state mode, which in tum generates increased spurs at

the reference frequency. Fortunately, this does not create problems for FTL applications,

where the reference frequency is the IF frequency divided by N. This frequency is of the

order of tens to hundreds of MHz and is strongly attenuated by the loop filter, which has

cut-off frequencies of a few MHz.

5.3. MODELING AND SIMULATION OF PHASE-LOCKED LOOPS.

5.3.1 Advanced Simulation Techniques.

Advanced simulation techniques that allow optirnization of transient behavior and

noise performance of high frequency analog circuits are currently available. Among these,

SpectreRF is a powerful simulation tool, which provides capabilities of high frequency

noise simulation. Phase-loçked lwps used in communications can be adequately simu-

lated and optimized using Spectre-RF.

Two important design aspects are considered in the optimization process of PLL's:

transient behavior, necessary to study the PLL dynarnic behavior, and large signal noise

analysis.

CIIAPTER 5: MONOLITHIC PHASE-LOCKED LOOPS ...

Transient behavior using SpectreRF's periodic steady-state analysis (PSS).

Periodic steady-state (PSS) analysis, utilizing a technique known as the Shooting

Newton Method, is used to directly compute the periodic steady-state response of a circuit.

It is a time domain method that operates by finding an initial condition that results in

steady-state. Shooting methods are iterative methods that start with a guess of the initial

condition for circuits operated with periodic signals. The circuit is evaluated for one period

starting from the initial condition, which is the DC soIution. The final state of the circuit is

computed dong with the sensitivity of the final state with respect to the initial state. The

non-periodicity and the sensitivities are used to compute a new initial condition. if the

final state is a linear function of the initial state, then the new condition wiii directly result

in periodicity. Otherwise, additionai iterations are needed [S. 121.

Shooting methods require fewer iterations if the final state of the circuit, after one

period, is a nearly-linear function of the initial state. This is generdy me even for circuits

that react in a nonlinear fashion for large stimuli (such as the clock or local oscillator)

applied to the circuit. Since the circuit is assumed to be periodic over the shooting interval,

the stimulus must also be periodic over the same interval. The shooting method integrates

over an integer number of periods of the stimulus, which rninirnizes the nodinearity in the

relationship between the initial state and the final state, and minimizes the number of iter-

ations needed for convergence. Typically, shooting methods need about five iterations on

a circuit and have little difficulty with the strongly nonlinear behavior that occurs within

the shooting interval. This is the strength of shooting methods over other steady-state

methods.

The shooting method consists of more steps as follows. The first step is the first

PSS iteration and is performed in a standard time domain (transient) simulation. The ini-

tial-time solution comes from the DC analysis and the simulator runs from r=O to

The second PSS iteration is between t = I / (PSS',,) and t = 2/( PSS',,) . As it

runs, the system saves al1 node voltages and branch currents in an admittance matrix. This

may require a significant arnount of memory and swap space to handle al1 of the nodes.

Once the second iteration is completed, the PSS algorithm compares al1 of the node

voltages and currents at the start and end of the shooting interval. Given that most circuits

will not have the same state (voltages and currents) at the end of the first iteration, the PSS

algorithm adjusts the state at t = 1 /(PSS/,,,,) so that on the second time the system will

have a closer match from begiming to end. The PSS algorithm deliberately saves the

admittance matrices, and so it has access to the time constants of the circuit. In addition,

because the voltages and currents at each time point are saved during simulation, the PSS

aigorithm has access to the waveforms in the circuit.

The program takes the last few data points at the end of the shooting interval and

glues them back to the beginning of the shooting interval. The last few data points are used

to adjust the slopes of the waveform at the beginning of the next iteration. In this way, the

data initiaiizes the numerical integration algorithms of the transient analysis to a new guess

that should be closer to the initial state of the final iteration. The simulation proceeds by

simulating one period at a time of the PSS fundamentai, readjusting the initial state until

the initial and final state match each other to within a small error term. At this point the

process stops.

Choosing the proper PSS fundamental frequency is essential for this simulation

method. One can always choose a very Iow frequency as the PSS fundamental, such that

this frequency is a divisor of al1 frequencies in the circuit. However, a higher fundamental

frequency yields a shorter simulation time. Fig. 5.10 illustrates a circuit with multiple fre-


quencies and it is used to demonstrate the proper choice of PSSfi,,& The RF is 900MHz,

the first IF is 15OM.z and the frrst LO is 1050M)fi. The second LO is 160MHz and the

second IF is 1OMHz. This yields a P SSfund of IOMHz.

RF Input Mixer 1 1 I5OMHz Mixer2 ! IOMHr output

1 PmMHz -1 1 1

Local Osc. 1 I I

Fig. 5.10. Selection of PSSlid as the highest cornmon multiple of al1 frequencies in the circuit.

Noise analysis using periodic noise (Pnoise).

Pnoise in SpectreRF is a two step process. In the first step, PSS is used to compute

the response to a large periodic signal such as a local oscillator. in the second step, which

is the actual Pnoise analysis, the resulting noise performance is computed. In periodic sys-

tems there are two effects that act to translate noise in frequency. First, for noise sources

such as shot noise that are bias dependent, the time-varying operation point acts to modu-

late these noise sources. Second, the transfer function from the noise source to the output is

also periodically time-varying, and so it acts to modulate the contribution of the noise

source to the output. Modulation has a multiplicative effect in the time domain, and so in

the frequency domain, the spectrum of the noise source is convolved with the spectmm of

the transfer function. The transfer function is periodic and has a discrete spectmm. The

convolution with a discrete spectrum involves a discrete number of scaling, translating and

summing operations. The final result of the analysis is the sum of the noise contributions


both up-converted and down-converted to the desired output frequency.

The Pnoise analysis is similar to the conventional noise analysis, except that it also

computes frequency conversion effects. This analysis can be used to compute the phase

noise of oscillators as well as the noise behavior of mixers, phase detectors and similar

switched circuits. The final result of the analysis is the sum of the noise contributions from

both the up-converted and down-converted output frequency specified.

For a given set of n integer numbers representing the sidebands kl, kz. ..., k,, the

small-signal noise source frequency at each sideband is cornputed as

6, = fou, + k - PSSlund, where f,, represents the output frequency. Thus, a positive kirep-

resents down-converted noise, while a negative ki represents up-converted noise. The fre-

quency conversion in Pnoise analysis is illustrated in fig. 5.1 1.

Pnoise analysis uses several steps as follows. A PSS anaiysis is run by SpectreRF

first. The periodically time-varying operating point is computed. A Pnoise simulation is

run after PSS completes. This analysis predicts al1 noise sources, utilizing small signal

sinusoidal signals. Since Pnoise is a small-signal analysis, the magnitude and phase of

each harmonic are linearly related to the magnitude and phase of the input signal.

5.3.2 Behavioral Models used in PLL Simulations.

The SpectreRF analysis methods previously descnbed are very useful, especially in

the large signal noise simulations of PLL's. For noise simulations one needs to include the

complete circuit which accounts for al1 physicd noise sources. The better the device noise

models, the more accurate the noise analysis will be. However, this analysis is time con-

suming and for large circuits c m keep a Sparcstation 20 busy for several hours. When the

dynarnic PLL behavior has to be optimized, there are fast simulation methods that can pro-

vide usehl and accurate results. These methods make use of behavioral models for the


PLL circuit components.

A Output

l I A

O j LO PSSfund harmonic

C i

PSS Andysis

Output

1 4

Input sideband ,

A A A Pnoise Analy sis

A A

Fig. 5.1 1. Frequency conversion performed in Pnoise analysis.

Standard behavioral building blocks are provided by any conventional SPICE sim-

ulator. Such behavioral blocks include, but are not Iimited to: cornparators, op-amps, logic

gates, samplers, mixers, voltage or curent-conuolled sources. Figs. 5.12 and 5.13 illus-

trate the use of some of these building blocks in order to build a phase-frequency detector

and a charge pump respectively. The PFD and charge pump, together with standard behav-

ioral filters and VCO's are then connected together to form a behavioral PLL, which can be

subjected to various input signais that provide the designer with useful information about

the loop dynamics.


Fig. 5.12. Behaviord phase-frequency detector.

Fig. 5.1 3. Behavioral charge pump.

148

C m R 5: MONOLiïHIC PHASE-LOCKED LOOPS ...

5.4 DESIGN AND SIMULATION OF A LOW NOISE HIGH SPECTRAL PURITY FREQUENCY TRANSLATIONAL LOOP FOR WIRELESS COMMUNICA- TIONS.

5.4.1 Design of the Frequency Translational Loop.

Frequency Translational Loops (FIL'S) are used in wireless communications due

to their good noise performance obtainable with relatively low power consumption. A loop

mixer performs a frequency up-conversion from the reference frequency that is fed to the

PLL input and the phase noise which accompanies a classic up-conversion is filtered by the

PLL [5.14].

a. Architecture of the FTL used in frequency up-conversion.

A block diagram of the FTL used in frequency up-conversion is presented in fig.

S. 14. The IF input is dnven with the constant envelope modulated signal which needs to be

up-converted to the transrnitter frequency (RFout on the block diagram of fig. 5.14). The

RF signal is fed back to the on-chip mixer and mixed with the local oscillator (Loin) sig-

nal. When the loop is locked, the mixer output signal tracks the IF input. The design of the

phase-frequency detector (PFD in fig. 5.14) allows the loop to lock on the "high side" or

"low side" of the LO signal. This means that, depending on the state of the switches in the

PFD path, the mixer output frequency c m be: IF=LO-RF ("high side") o r IF=RF-LO ("low

side"). This function is performed by swapping the UP and DN outputs of the phase-fre-

quency detector. The implementation of this function permits the utilization of an LO fre-

quency which can be chosen around the middle of the range from 900MHz to 1.9GHz,

thus allowing the usage of a single LO VCO for a dual-mode implementation like

GSMIDCS.


Fig. 5.14. Block diagnm of the Frequency Translational Lwp. The onchip components are

inside the dashed box.

The monolithic implementation of the F ï L contains the phase-frequency detector

and charge-pump, the mixer, LO and RF buffers and the low-pass filter following the

mixer. The loop filter and the VCO are off-chip components.

In the design of the Fiï, building blocks special consideration is given to the min-

imization of the "in-band spurs. We denote by "in-band spurs the low frequency mixing

products of harmonics of the LO and IF frequencies. The mixing of LO and IF harmonics

takes place in the phase-frequency detector and charge pump due to the inherently switch-

ing nature of these circuits. The low frequency mixing products are not attenuated by the

loop and they cause undesired frequency modulation of the VCO. Ideally, the generation

of these mixing products could be avoided if the PFDkharge pump were linear circuits, or

if the loop mixer was a linear multiplier generating a single product at the iF frequency.

C-R 5: MONOLïTHK PHASE-LOCKED LOOPS ...

However, the intensity of the spurs falling within the loop bandwidth can be reduced if

these are generated by higher order of the LO and IF harmonics. A detailed analysis of the

mechanism which generates these s p m is presented in section 5.4.2.

b. Building blocks of the FTL.

The building blocks of the FTL are: the phase-frequency detector and charge pump,

the RF buffer, the mixer and low-pass filter. These blocks wilI be presented next.

As can be seen on the block diagram of fig. 5.14, the PFD is implemented using a

pair of resetable D flip-flops with an AND gate which resets the flip-flops. The particular

irnplementation of the flip-flops and the AND gate uses very fast ECL techniques, since the

PFD needs to operate up to 450MHz. The schematic of the resetable D flip-flop is pre-

sented in fig. 5.15a). As can be seen it is a master-slave configuration which uses ECL

techniques. Transistors Q 1,Q2,Q3 and Q4 form the master portion of the latch and tran-

sistors QS,Q6,47 and Q8 form the slave. Transistors Q 15, Q 16, Q 17 and Q 18 are used to

reset the flip-flop. The voltage swings are 200mV and each flip-flop consumes 4 0 0 ~ A.

The propagation delay through the flip-flops and the gate is less than SOOps. This tirne

delay sets the minimum pulse width of the UPDN pulses generated by the PFD and it is

short enough to ensure proper operation up to 450MHr.

The charge pump schematic is presented in fig. 5.15b). Al1 switching transistors are

npn type since the charge pump is required to function at a maximum frequency of

450MHi. The circuit operates in current mode and the voltage swings are minimal.

PMOS transistors M 1, M2 and M3 are used as DC current sources and they do not limit the

speed of the circuit. When both inputs UP and DN are either high or low, the DC current

injected by M2 is equal to the collector current of Q6 and the output cunent Ion is zero.

When UP is high and DN is low, the collector current of 46 is twice as large as the drain


current of M2 and the charge pump sinks a current equal with Ibiss- m e n UP is low and

DN is high, the charge pump sources a current equd with Ibias- The leakage current of this

high speed charge pump is larger than the values usually obtainable in low speed charge

pumps, where a pair of NMOS-PMOS transistors is used for the output stage. However, the

spur generated at the reference frequency (IF in this application) by the leakage current is

strongly attenuated by the loop, which usuaily has a bandwidth of 1 -2MHz for GSM/DCS

applications, while the lowest IF frequency is 100MHz.

Fig. 5.1S.a) Schematic of the ECL resetable flip-flop.

The mixer and low-pas filter used in this design is presented in fig. 5.16. It is a

double-balanced Gilbert mixer with degeneration in the ernitters of transistors Q5 and Q6.

This degeneration extends the linearity of the RF input for signal swings up to 200mVpk.

The linearity of the mixer RF input is important, since it prevents the generation of

unwanted mixing products which cannot be rejected by the low-pass fdter following the


mixer. These unwanted rnixing products are fed into the phase-frequency detector and gen-

erate yet another set of intermodulation products of frequencies very close to the IF fre-

quency. If this situation takes place, the loop cannot attenuate products which are within

the loop bandwidth, i.e. at ftequencies around IF* 2 M H z and the F ï L circuit presents

unwanted spurious products at the output. The mixer bias current is 3mA. The low-pas

filter following the mixer uses on-chip inductors L 1 and L2 to reject the image frequency at

RF+LO. The attenuation of this filter is better than 45dB at frequencies higher than 2GHz .

Fig. 5.15.b) Schematic of the high speed charge pump.

Fig, 5.16. Schematic of the mixer and low-pass filter.

153

CHAPI'ER 5: MONOLITHIC PHASE-LOCKED LOOPS ...

The RF buffer is presented in fig. 5.17. In order to accommodate a wide range of

RF input power levels which are fed frorn the VCO, this bufier uses a doublet at the input

formed by transistors QI, 42, 4 3 , Q4. The automatic gain control (AGC) circuit imple-

mented around the doublet maintains a constant level at the buffer output, thus ensuring

that the linear range of the mixer RF input is not exceeded. The automatic gain control con-

sists of the envelope detector (transistors Q 12 and 413) and a gain stage (transistor Ml),

which controls the transconductance of transistors Q6 and 47.

Fig. 5.17. Schematic of the RF buffer with automatic amplitude control.

5.4.2 Analysis and Simulation of the Frequency Translational Loop.

In the analysis of the FIL circuit, two important aspects are considered: minirniza-

tion of the spurious level and reduction of the phase noise level generated. Both these cn-

teria need to be achieved with a minimum amount of power consumption.

For the analysis of the spectral purity of the FTL, the circuit of fig. 5.18a) was sim-

ulated using SpectreFW. The phase-frequency detector (PFD) is run at the IF frequency


and the conversion gain from PORT 1 to the output (OUT) is simulated. Simulations were

carrïed out for more IF frequencies in the range from 10MHz to 450MHz . The plot of fig.

5.18b) shows the conversion gain when IF=300MHz. The conversion gain has a variation

of less than 3dB over the entire IF frequency range. In fig. 5.18b) are shown the conver-

sion gains from any frequency fi, present at the PFD V input to DC at the loop filter out-

put, whereh is

f, = & - I F , (5.27)

and k = 1,2 ,..., N.

Fig. 5.18.a) Circuit used for the analysis o f spurious products.

Since this conversion gain is simulated for very narrow bands around the frequen-

cies f, , there is no attenuation introduced by the bop filter. Any spurious product which

is within these frequency bands is down-converted around zero frequency by the phase-fre-

quency detector. It can be seen in fig. S.18b) that the convergence gain is -6dB for

k = 1,2 (Le. for frequencies around the first harmonics of the IF) and it drops to -426B for

k = 20.

C W R 5: MONOLITHIC PHASE-LOCKED LOOPS ...

Fig. 5.18.b) PFD convergence gain from harmonics o f the IF to frequencies within the Imp band-

width: k is the order o f the harmonic of iF

For a mixer which is linearized at the RF input port, there are fewer mixing prod-

ucts which will be present at the V input of the phase-frequency detector. However, the

image frequency at RF+LO and harmonics of the LO need to be attenuated by the low-pass

filter following the mixer. A filter attenuation of around 45dB at frequencies higher than

2GHz ensures sufficient spurious rejection for applications such as GSM/DCS, since the

conversion gain of the PFD drops below -27dB for these frequencies, which are equal to at

least the 15th harmonic of the IF. Any mixing product which is still present around the

zero frequency at the loop filter level has the effect of frequency modulating the VCO

according to the equation

where Ko is the VCO sensitivity in [(rad)/( V s) ] and VSpUR is the spur amplitude in [VI.

For a spurious product at the loop filter level expressed in dB V , the frequency mod-


ulated spur present at the VCO output can be expressed relative to the RF carrier

where f is the frequency of the spurious product at the loop filter level.

The above analysis can be generalized for FIL topologies where a frequency divi-

sion is performec! in the feedback loop. For a division ratio n , the PFD convergence gain

needs to be evaluated at frequencies: fk = k - ( i F ) / n . This means that there will be n

times more harmonics in the plot of fig. 5.18b) and the convergence gain from these har-

monics to DC will fall on the envelope which interpolates the points on this plot. For these

situations, there are increased chances that a h m o n i c of the IF coincides with a lower

order harmonic of the LO, which is present at the PFD V input and the convergence gain

for these harmonics is high.

The noise contributions of the FTL building blocks to the phase noise at the RF out-

put are studied at two different injection points as depicted in fig. 5.19. If Si,, and Si are

the noise to carrier ratios at the two injection points, then the separate contribution of each

of them to the phase noise at the RF output is given by

and

Kd. KO ' F ~ w ) where Tua) = , Q is the quality factor of the VCO's resonator and a>o is

i w the carrier frequency.

157


ni rrcr n RF buf r u

Fig. 5.19. Noise contributions of the FïL building blocks to the phase noise at the RFoutput.

The nominator of equation (5.30) describes the phase noise of the VCO and it

reduces to Leeson's formula if Si,, is expressed as Si, a = ( k T F ) / C [5.13], where F is the

noise figure of the VCO's gain stage and C is the power of the carrier.

The total phase noise at the W output is the sum of S , a and So, b , assuming they

are generated by uncorrelated noise sources. It c m be seen from equation (5.30) that Si, a

is rejected for frequencies srnaller than the loop bandwidth (Le. for T u a ) > 1 ) and it fol-

lows the frequency dependency of the VCO's phase noise for frequencies larger than the

loop bandwidth, when 1 + T u o ) = 1 .

Equation (5.3 1) shows that Si, is passed unanenuated to the output for frequencies

smaller than the loop bandwidth, and it is multiplied by 1~(j0)1~ < i for frequencies larger

than the loop bandwidth [5.7].

The output noise of the phase-frequency detector and charge pump is simulated

using Spectre-RF, while these circuits are run open-bop at the IF frequency. The noise at

158

CH-R 5: MONOLITHIC PHASE-LOCKED LOOPS ...

the charge pump output is presented in fig. 5.20a). For the frequency domain from O H z to

1 MHz, which is the loop bandwidth for this application, the contribution of the PR) and

charge pump to the FTL phase noise is

= eiMs (5.32)

freq [Hz]

Fig. 5.20.a) Simulated output noise voltage of the PFD and charge pump. The PFD is run at an IF

frequency of 300MHz.

It is convenient to express 82, in equation (5.32) as the phase modulation pro-

duced by the noise voltage of the PFD and charge pump when driving the VCO. Thus. it

can be shown [S. 131 that el, is given by

where Af = Ko - V, is the peak frequency deviation produced by a dnving voltage V,, upon

a VCO of sensitivity Ko and f is the frequency offset from the carrier.


Using the noise value from fig. 5.20a) and an off-chip VCO with

Ko = ( 2 n - 30MHz) /V , the phase noise at 400kHz offset from the carrier yields

S,, b(j2x400kHz) = -121 ( d B c ) / ( H z ) . (5 -34)

For frequencies higher than 1 MHz, the noise contributed by the PFD and charge pump is

rejected by the loop.

The total output noise of the mixer, the RF and LO buffers contributes to the noise

spectrum Si,, . The impact of the noise generated by the mixer and buffers upon the FI'L

phase noise is assessed by simulating the noise figure, NFMix,,, at the R F buffer input,

while running the mixer at an LO frequency higher than 1 GHz. The simulation result is

presented in fig. 5.20b). It can be seen that the noise figure is less than 20dB for the IF fre-

quency range from 10 MHz to 400MHz . For frequencies below and above this range, the

noise figure increases mainly due to the signal attenuation introduced by the filter at the

mixer's output.

Fig. 5.20. b) Simuiated noise figure of the mixer and buffers. The mixer is mn at an LO frequency

of 1,lSGHz. The LO power is - 10dBm.

160

CEIAPTER 5: MONOLrlHIC PHASE-LOCKED LOOPS ...

The design goal is to determine the minimum level of the RF carrier required to

drive the RF bufier without degrading the FIL noise performance. For îhis purpose, the

phase noise level contributed by the mixer is calculated according to equation (5.3 1). For a

frequency offset of 20MHz from the carrier, equation (5.3 1) becomes

which can be expressed in dB as S, ,(dB) = Si, ,(dB) - 35dB . in order to achieve a total

output phase noise level of - loS(dBc) / (Hz) , the phase noise contributed by S, needs to ,

be S , &2n20MHz) 5 -168(dBc)/(Hz) , assuming that the VCO phase noise is no more

than -168(dBc)/(Hz) . Therefore, the noise-to-signal ratio at the PFD input is

Si, 5 -133(dBc)/(Hz) . Knowing that the RF buffer is matched to 50R at the input, the

minimum carrier power which does not degrade the F ïL noise performance is cdculated

from the equation

Si. , (dBc) / (Hz) = - 174(dBm)/(Hz) + NFMix,, - Cmin(dBm) (5.35)

which yields a value of -21 dBm for Cm,. The phase noise level conuibuted by the mixer

at offset frequencies smaller than the loop bandwidth is much smaller than the Ievel con-

tributed by the PFD and charge pump when Cm, = -21 dBrn . Overail, the mixer contri-

bution to the phase noise level is negligible if the power level driving the RF buffer is larger

than Cmi, .

5.4.3 Measurement Results.

The FïL was fabricated in a BiCMOS process with f, = I2GHz . The output spec-

tnim is presented in fig. 5.21. The "in-band spurious product at 4ûûWz offset from a

891.2MHz R F carrier is the rnixing product between the mixer's image frequency at

RF+LO and the 10th harmonic of IF. The measwement is in agreement with the spurious

analysis presented in section 5.4.2. The phase noise level measured at 4Oc)k.H~ offset from

161

CHAITER 5: MONOLITHK PHASE-LOCKED LOOPS ...

the carrier is presented in fig. 5.22. The measured value of -120(dSc)/(Hz) is in fair

agreement with the simulation. The phase noise level measured at 20MHt offset from the

carrier is -165(dBc)/(Hz) and it is dominated by the VCO's phase noise. The total

power consumption of the circuit is 54m W from a 2.7V power supply. The measured char-

acteristics recommend this design for use in GSM/DCS applications.

Fig. 5.21. Measured output spectrum. Two spurious products exist at WkHz offset from a

89 1.2MHz carrier. Here RF=891.2MHz; LO=1089.2MHz; IF=198MHz. Spunous products are at

2xLO- 1 1 xIF=400kHz.


Fig. 5.22. Measured output phase noise level is - 1 20dBclHz at 400kHz offset from a 900MHz car-

rier.

Fig. 5.23. Microphotopph of the Frequency Translational Loop.

163

C w R S: MONOLITHIC PHASE-LOCKED LOOPS ...

REFERENCES

164

H. de Bellescize, La Reception Synchrone, Onde Electr., vol. 11, pp. 230-240, June 1932.

A. Blanchard, Phase-Locked Loops: Application to Coherent Receiver Design, John Wiley & Sons, New York, 1976.

A. J. Viterbi, Principles of Coherent Communication, McGraw-Hill, New York, chapter 5, 1966.

F. Gardner, Phaselock Techniques, John Wiley & Sons, Inc., chapter 3, 1979.

R. E. Best, Phase-Lucked Loops, McGraw-Hill, chapter 3, 1984.

U. L. Rohde, Digital P U Frequency Synthesizers. Theory and Design, Prentice- Hall, hc., chapter 1, 1983.

B. Razavi, Monolithic Phase-Locked Laops and Clock Recovery Circuits, The Institute of Electrical and Electronics Engineers, Inc., 1996.

J. L. Tham, M. A. Margarit, B. Pregardier, C. D. Hull, R. Magoon, F. Cam, "A 2.7V 9ûûMHd1.9GHz Dual-Band Transceiver IC for Digital Wireless Commu- nication," IEEE Journal of Solid-State Circuits, vo1.34, no.3, pp. 286-291, March 1999.

G. Irvine, S. Herzinger, R. Schmidt, D. Kubetzko, J. Fenk, "An Up-Conversion Loop Transmitter IC for Digital Mobile Telephones," ISSCC98 Proceedings, pp. 344-365, February 1998.

T. Yamawaki et. al., "A 2.7-V GSM RF Transceiver IC," IEEE Journal of Solid- State Circuits, vo1.32, no. 12, pp. 2089-2096, December 1997.

[5.11] B. Razavi, J. J. Sung, "A 6GHz 60mW BiCMOS Phase-Locked Loop," lEEE Journal of Solid-State Circuits, vol. SC-29, pp. 1 560- 1 565, December 1994.

[5.12] J. Smith, Modern Communication Circuits, McGraw-Hill, Inc., chapter 9, 1986.

C5.131 Cadence, SpectreRF Training Manual, module 6, October 1997.

r5.141 M. A. Margarit, M. J. Deen, "A Low-Noise High Spectral Purity Frequency Translational Loop for Wireless Applications," submined for publication to IEEE Trans. on Microwave Theory and Techniques, 1999.

CHAPTER 6: CONCLUSIONS

CHAPTER 6

CONCLUSIONS

The main objective of this research work was to develop circuit techniques that

result in better noise and linearity performance for radio frequency components used in

communications. The design principles for low noise, low distortion in R.F. circuits were

studied. These principles are of general interest and they were followed throughout the

present work. A novel high frequency BJT noise mode1 was developed in the effort of

facilitating the noise analysis of R.F. circuits. Volterra series were used in the high fre-

quency distortion andysis of the comrnon emitter and differential stages. The results of this

andysis show that, at high frequency, inductive degeneration provides the best perfor-

mance in terms of linearity, while capacitive degeneration provides the worst performance.

Finaily, a low noise, low distortion amplifier with variable gain was designed, that follows

the above mentioned design principles.

Voltagecontrolled oscillators (VCO's) and PLL's, together with low noise ampli-

fiers are key cornponents used in a radio system. Therefore, other topics studied during this

work were low noise VCO's and low noise, high spectral purity PLL's used in communi-

cations.

Voltage-controlled osciliator topologies were investigated in detail. High perfor-

mance designs were identified that provide high immunity to substrate coupling, low phase

noise levels and low power consumption. Mechanisms that generate undesired oscillations

were investigated and design criteria for reliable oscillator start-up were denved. Based on

these findings, a VCO topology was chosen and implemented in monolithic bipolar tech-

nology with the purpose of achieving the minimum amount of power consumption for a

specified phase noise level.

A novel circuit technique employing automatic amplitude control was developed

for low noise and low power VCO design. The phase noise level of this design was opti-

mized by means of a newly developed noise analysis method, that accounts for nonlinear

processes in oscillators. It was demonstrated duRng this analysis that optimization of VCO

noise performance can be achieved not only by increasing the resonator quality factor, but

also by choosing an optimum capacitive feedback ratio, that helps rninimizing the noise

contribution of the active devices. The automatic amplitude control technique ensures reli-

able oscillator start-up, while the capacitive feedback ratio can be chosen soIely with the

purpose of improving the noise performance. At the same time, the automatic amplitude

control maintains the oscillator constant output power, independent on the quality factor of

the extemal resonator. Future research in this area should be carried out for developing low

phase noise designs for enhanced Colpitts oscillators of the type indicated in fig. 3.12.

Also, the noise anaiysis method developed in this work can be used in the optimization pro-

cess of any oscillator topology. This analysis method is useful in studying the excess phase

sensitivity for each node of the circuit. The goal in improving any oscillator noise perfor-

mance is then to obtain symmetrical excess phase sensitivity functions, since symmetrical

waveforms present the least amount of harmonies.

A low noise, high spectral purity frequency translational loop (FTL) was designed

and implemented dunng this work, together with the analysis method for mechanisms that

generate spunous products in FTL circuits. It was demonstrated that mixing products gen-

erated by the loop mixer are further mixed in the phase-frequency detector and generate

low frequency spurious products at the input of the loop filter. These low frequency prod-

ucts can not be filtered by the loop and they perturb the s p e c ~ a l purity performance of the

circuit. An analysis method was developed in this work that indicates the required amount

of image rejection at the mixer output when the overall spectral purity performance is pro-

vided. At the same time, the noise analysis of the circuit determines how much noise deg-

radation from the l w p mixer can be tolerated. It was demonstrated that the phase noise

C w R 6: CONCLUSIONS

level for offset frequencies smalier than the loop bandwidth is not influenced by the mixer,

as long as its noise figure is less than a predictable threshold value. Future research should

be carried out for the development of a FTL with in-loop modulation, based on the topol-

ogy in fig. 5.7. The analysis method for spurious products, that was developed during this

work, cm be applied to the FK with in-loop modulation.

Recomrnendations.

The research for future development of R. F. monolithic circuits for communica-

tions should focus on circuit techniques that can improve key parameters such as linearity

and noise, while reducing the amount of power consumption. The researcher should

irnprove continuously the analysis techniques, and should also keep abreast with the latest

advances in monolithic technologies. These technologies allow for the continuous devel-

opment of integrated circuits for communications.

In surnmary, in this work, radio frequency circuit techniques were developed that

achieve improved levels of noise and linearity performance for a minimum amount of

power consumption. New and innovative analysis methods were implemented that allow a

detailed investigation of circuits performance. This research creates the frame work for

future developments in the area of radio frequency monolithic circuits, such as VCO's and

PLL's used in communications.

APPENDm A: SPICE FILE USED FOR SIMULATIONS ...

APPENDIX A

SPICE FILE USED FOR SIMULATIONS OF THE HIGH

FREQUENCY B JT MODEL

1 . SPICE fde of the Gummel-Poon BJT model

.OPTION POST=l PROBE

v l 1 Oac 1

RB 1 2 261

Rpi 2 3 2.5k

Cpi 2 3 445f

R e 3 0 12

Gm 4 3 2 3 0.0385

Cmu 2 4 9f

Rc 4 O 77.7

.AC DEC 10 l0meg log

.PRINT AC vm(4) vp(4)

.probe ac vdb(4) vp(4)

.END

2. SPICE file of the new BJT model proposed in this work

.OPTION POST= 1 PROBE

APPENDIX A: SPICE FILE USED FOR SIMULATIONS ...

v l 1 0 a c 1

RB 12 261

Rpi 2 3 2Sk

Cpi 2 3 44Sf

C2 2 3 32.6f

R 2 22 171.4

CI 22 3 9f

R e 3 0 12

Gm 4 3 2 3 0.0385

Rc 4 O 77.7

.AC DEC 10 lOmeg IOg



.END

3. Spice file of a real BJT (transistor mode1 NN52 1 I I x - Canadian Microeleccronic Corpo- ration)

.OPTION POST=l PROBE

v l 1 Oac 1

Rin 1 0 10k

vcc 2 O dc 3

vee 6 O dc -3

APPENDm A: SPICE FILE USED FOR SIMULATIONS ...

.MODEL nn NPN IS=3. le- 18 Rb=26 1 Re= 12 BF= 103 C E = 1 Se - 14 Vm.8 MJE=û.267

+TF= 1 . 1 e- 1 1 UC=2.l e- 14 VJC=û.7 1 MJC=û.4

.AC DEC 10 lOmeg log



.END

radio frequency integrated circuits communications: design...

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