ramp/hasim status update joel emer michael adler angshuman parashar michael pellauer murali...
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RAMP/HAsim Status UpdateRAMP/HAsim Status Update
Joel EmerMichael AdlerAngshuman ParasharMichael PellauerMurali Vijayaraghavan
VSSAD GroupIntel
CSG Group, CSAILMIT
2
Infrastructure Update
• AWB Plug N Play– Hardware Language Support
• Bluespec, VHDL, Verilog– Software Language Support
• C++
• Build Procedure– Updated to scons
• Automatic Parallel Build– Common data types between hardware and software
• Common Platform
3
History and Motivation
XUP Model “Sim” ModelTop Level Wires BDPI
XUP BoardLEDs and Switches
(image source: xilinx.com)
Software SimulatorProcesses
(image source: intel.com)
4
History and Motivation
Platform Independent Model
XUP Front PanelTop Level Wires
“Sim” Front PanelBDPI
front_panel.writeLED()
Virtual Platform
XUP BoardLEDs and Switches
(image source: xilinx.com)
Software SimulatorProcesses
(image source: intel.com)
or
5
Virtual Platform
• Provide common set of functionalities across multiple physical platforms
• XUP Board• PCI-express Board• Intel FSB Socket• Bluesim/Vsim• BEE3
• Leverage Asim Plug N Play– Minimize module replacements/recoding while
moving across platforms
6
Virtual Platform
Communication Layer(s)
Device 1
Virtual Devices
Timing + Functional Modules
Virtual PlatformPlatform Interface
Physical Platform
Device 2Device 0
Soft Connections
ExeDecodeFetch
FuncModelControl
7
Virtual Platform on XUP
VGA
Virtual Devices
Virtual PlatformPlatform Interface
LEDsSwitches
MemoryFront Panel
VGA On-BoardMemory
Timing + Functional Modules
Soft Connections
ExeDecodeFetch
FuncModelControl
8
Virtual Platform on Simulator
UNIX Pipe Communication Layer
VGA
Virtual Devices
Virtual PlatformPlatform Interface
Bluesim
MemoryFront Panel
Pipe I/O
Timing + Functional Modules
Soft Connections
ExeDecodeFetch
FuncModelControl
9
Virtual Platform on PCIe System
Communication Layer(s)
VGA
Virtual Devices
Virtual PlatformPlatform Interface
PCIe-based Host System
MemoryFront Panel
Timing + Functional Modules
Soft Connections
ExeDecodeFetch
FuncModelControl
HostSoftware
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Communication with Host Software: Hybrid Modules
Communication Layers
ExecuteDecodeFetch
Func ModelControllerController
Decode
PCI Express
Communication Layers
ConsoleFront PanelFront Panel Console
FPGA Host
Hybrid Module
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Server- Accept Request- Send Response
Hybrid Module Communication: The Paradigm
FPGA Modules Software Modules
Communication Layers
ExecuteDecodeFetch
Func ModelController Controller
StartStopStep
StartStopStep
PrintAssertPrintEventPrintStat
PrintAssertPrintEventPrintStat
Decode
Client- Make Request- Accept Response
Client Server
Controller Controller
PCI Express
Communication Layers
HAsim Remote Request/Response (RRR)HAsim Remote Request/Response (RRR)
12
Server- Accept Request- Send Response
RRR Protocol StackFPGA Modules Software Modules
Kernel Driver
ExecuteDecodeFetch
Func ModelController
Low Level Driver
Controller
StartStopStep
StartStopStep
PrintAssertPrintEventPrintStat
PrintAssertPrintEventPrintStat
Decode
Client- Make Request- Accept Response
Client ServerRRR Protocol Stack RRR Protocol Stack
Key Issues
• Service IDs– Automatic
Assignment
• Request and Response Types
– Flexibility– Ease of Use
PCI Express
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RRR Specification Language// --------// typedefs// --------typedef MSG_CLASS { HOST: UINT8, FPGA: Bit#(8) };typedef STATUS { HOST: bool, FPGA: Bool };typedef UINT { HOST: UINT64, FPGA: Bit#(64) };
// --------------------------------------// create a new service called CONTROLLER// --------------------------------------service CONTROLLER{ // ------------------------------------------- // declare services provided by HOST partition // ------------------------------------------- server HOST <- FPGA; { method PrintMessage(in MSG_CLASS, out STATUS); method PrintStat(in MSG_CLASS); method PrintEvent(in MSG_CLASS); };
// ------------------------------------------- // declare services provided by FPGA partition // ------------------------------------------- server FPGA <- Host; { method Start(); method Stop(); method Step(in UINT); };};
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RRR Protocol StackFPGA Modules Software Modules
Kernel Driver
ExecuteDecodeFetch
Func ModelController
Low Level Driver
Controller
Decode
Hardware Channels
Channel IO
CSR DMA Interrupt
Channel IO
CSRInterrupt
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RRR Protocol StackFPGA Modules Software Modules
Kernel Driver
ExecuteDecodeFetch
Func ModelController
Low Level Driver
Controller
Decode
Hardware Channels
Channel IO
RRR Server RRR Client
CSR DMA Interrupt
Channel IO
RRR Server RRR Client
Channel 0 Channel 1 Channel 1 Channel 0
CSR
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RRR Protocol StackFPGA Modules Software Modules
Kernel Driver
ExecuteDecodeFetch
Func ModelController
Low Level Driver
Controller
Decode
Hardware Channels
Channel IO
RRR Server RRR Client
CSR DMA Interrupt
Channel IO
RRR Server RRR Client
Channel 0 Channel 1 Channel 1 Channel 0
CSR
SID 0 SID 1
RRRspecification
files0 0
1 1
rrr_service_ids.bsv
`define CONTROLLER_SERVICE_ID 0`define DECODE_SERVICE_ID 1`define MEMORY_SERVICE_ID 2`define NUM_SERVICES 3
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RRR Protocol StackFPGA Modules Software Modules
Kernel Driver
ExecuteDecodeFetch
Func ModelController
Low Level Driver
Controller
Decode
Hardware Channels
Channel IO
RRR Server RRR Client
CSR DMA Interrupt
Channel IO
RRR Server RRR Client
Channel 0 Channel 1 Channel 1 Channel 0
CSR
SID 0 SID 1
RRRspecification
files 0 0
1 1
Stub Stub
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RRR Protocol StackFPGA Modules Software Modules
Kernel Driver
ExecuteDecodeFetch
Func ModelController
Low Level Driver
Controller
Decode
Hardware Channels
Channel IO
RRR Server RRR Client
CSR DMA Interrupt
Channel IO
RRR Server RRR Client
Channel 0 Channel 1 Channel 1 Channel 0
CSR
SID 0 SID 1
0 0
1 1
Stub Stub
SID 1
Stub Stub
SID 0
19
Switching Physical PlatformsFPGA Modules Software Modules
Kernel Driver
ExecuteDecodeFetch
Func ModelController
Low Level Driver
Controller
Decode
Hardware Channels
Channel IO
RRR Server RRR Client
CSR DMA Interrupt
Channel IO
RRR Server RRR Client
Channel 0 Channel 1 Channel 1 Channel 0
CSR
SID 0 SID 1
0 0
1 1
Stub Stub
SID 1
Stub Stub
SID 0
20
PCIe-based Physical PlatformFPGA Modules Software Modules
Kernel Driver
ExecuteDecodeFetch
Func ModelController
Low Level Driver
Controller
Decode
Hardware Channels
Channel IO
RRR Server RRR Client
CSR DMA Interrupt
Channel IO
RRR Server RRR Client
Channel 0 Channel 1 Channel 1 Channel 0
CSR
SID 0 SID 1
0 0
1 1
Stub Stub
SID 1
Stub Stub
SID 0
21
Simulation Physical PlatformFPGA Modules Software Modules
UNIX inter-process communication
ExecuteDecodeFetch
Func ModelController
BDPI Layer
Controller
Decode
Channel IO
RRR Server RRR Client
Channel IO
RRR Server RRR Client
Channel 0 Channel 1 Channel 1 Channel 0
SID 0 SID 1
0 0
1 1
Stub Stub
SID 1
Stub Stub
SID 0
22
Dictionaries
// append to STATDEFS.bsh, STATDEFS.hdef STAT.BRANCHES_MISPREDICTED "mispredicted branches = ";
// append to EVENTDEFS.bsh, EVENTDEFS.hdef EVENT.SIM_FAILED "simulation failed";
// append to TRACEDEFS.bsh, TRACEDEFS.hdef TRACE.FETCH "fetch instruction %d"; // note: 1 paramdef TRACE.DECODE "decode inst %d into %d"; // note: 2 params
23
Infrastructure Summary
Channel IO
RRR Client + Server
FPGA Modules
Virtual Platform
Platform Interface
Channel IO
RRR Client + Server
Hardware Software
Software Modules
MemoryFront Panel
ExeDecodeFetch
FuncModelControl Decode
Front Panel Memory
24
Conclusion
• Virtual Platform– Multi-layered set of abstractions providing platform-
independent interfaces to platform-dependent devices
• Remote Request/Response– Part of the Virtual Platform hierarchy– Facilitates communication between multiple partitions of
hybrid modules– Tedious HDL plumbing code is auto-generated from
specification files
Backup Slides
26
Sample RRR Service Stub
Stub.txt
27
Outline
• History and Motivation
• Virtual Platforms
• Hybrid Modules and RRR
• Conclusion and Demo
28
Hybrid Modules
Channel IO
RRR Client + Server
FPGA Modules
Virtual Platform
Platform Interface
Channel IO
RRR Client + Server
Hardware Software
Software Modules
MemoryFront Panel
ExeDecodeFetch
FuncModelControl Decode
Front Panel Memory
HAsim Remote Request/Response (RRR)HAsim Remote Request/Response (RRR)
29
RRR: Intel FSB
Channel IO
RRR Client + Server
FPGA Modules
Virtual Platform
Platform Interface
Channel IO
RRR Client + Server
Hardware Software
Software Modules
MemoryFront Panel
FSB Driver
ExeDecodeFetch
FuncModelControl Decode
Front Panel Memory
30
RRR: Simulator
Channel IO
RRR Client + Server
FPGA Modules
Virtual Platform
Platform Interface
Channel IO
RRR Client + Server
Hardware Software
Software Modules
MemoryFront Panel
UNIX pipe
ExeDecodeFetch
FuncModelControl Decode
Front Panel Memory
31
Hybrid Modules
• Hybrid Modules– Primary points of communication between FPGA
and Host Software– Module functionality can be split between FPGA
and software
• How do partitions of a hybrid module communicate with each other?
32
Hybrid Modules (cont.)• Module definition
– hybrid_fetch_unit.awb%sources –t BSV –v PUBLIC hardware_fetch_unit.bsv%sources –t CPP –v PUBLIC software_fetch_unit.h%sources –t CPP –v PRIVATE software_fetch_unit.cpp
• Build process– Collects BSVs and generates “hardware” bitfile or
simulation binary– Collects CPPs and generates “software” binary
• Runtime– Software binary loads bitfile onto FPGA, or forks off
simulation “hardware” binary– Software Controller sends “start” RRR request to
Hardware Controller