Rapid silicon prototyping and production for RISC-V SoCs

5th RISC-V Workshop, Nov 29-30 2016Neil Hand, Codasip VP Marketing

Every new IoT application (and company) is different,

so why use a standard part?

Because until now it is all you had…

CHOICES TODAY ARE LIMITED FOR NEW DESIGN TEAMSStandard parts• Cheap and easy to get started• Poor production scaling• Limited differentiation

ASIC• Expensive to get started• Good production scaling• High level of differentiation

NEED TO SUPPORT RAPID EVOLUTION OF IOT DESIGNS

Phase 2Usability and cost

optimization• Expand the market

Phase 3Multi-function

integration• Deliver unique value

Phase 1Basic functionality

to market• Enable the software platform

Benefits from ASIC

WHAT IF? SOC DESIGN ON AN IOT BUDGET!

Custom Silicon

Mobile class ASICs

Off-the-Shelf Components

Mainstream ASICs

Mask set > $25MPrototypes > 6 monthsEDA tools > $10MBleeding-edge technologyHighly specialized resources

BOM Cost and/or Product Differentiation

Design Cost

IoT class ASICs

Mask set in $10K’sPrototypes in weeksEDA Tools <$100KMature technologyLimited specialized resources

RISC-V PLATFORM FROM SILICON TO INTELLIGENCE

An integrated platform that

• Keeps designers in control• Is easy to build and expand• Provides as much, or as little

help as you need• Supports low-cost MPW and

wafer scalingMPSC

FPGA Porting

RICH foundational IP Library

Advanced Debug, Analysis, optimization

Application optimizedRISC-V

LLVM

OpenCL

TensorFlow OpenCV

SYCL

STANDARDS BASED

IT BEGINS AT THE SILICON LEVEL

Spec RTL

Codasip Baysand UltraSoC

Implementation

FPGA Proto

Emulation MCSCASIC

MetalC

opyFPG

APort

UltraShuttle

METAL CONFIGURABLE STANDARD CELL (MCSC) ACCELERATES DESIGN AND PRODUCTION

• MCSC – 65nm and 40nm Technology• 600k to 4Million usable gates• 242 to 1250 IOs• 1Mbit to 70Mbit of memory• Including DCMs/PLLs• Package flexibility supporting up to 1760

Flip Chip BGA package• ASIC UltraShuttle offering

• RTL signoff• Low cost verification vehicle• Deliver 100 fully tested packaged

devices• 8 weeks from Tape out

MCSC- CoreLogic• MetalConfigurableStandardCell

• 500+StandardCellLibrary

• Multi-VtSupport

MCSC- Memory• MetalConfigurableRAM• SP/DP/SDP/ROM/FIFO• SupportFPGAFeatures+

MCSC- IO&PHY• MetalConfigurableIOBanks

• MetalConfigurableDDR/LVDSPHY

• 1.2vto3.3VIOStandards

• PHYcanbeAnywhere

Transceiver(Serdes)• 6.5&12.5Gbps• SupportsMulti-Protocol

• SoftMulti-ProtocolPCS

CoreDesignElements

MCSC- PLL• MetalConfigurablePLL• 6or9OutputProcessors• SupportDynamicFreq.&Phase

RichFamilyofIPCores

METALCOPYSEAMLESS FGPA TO ASIC CONVERSION

• Xpresso IP conversion tool• Makes untethering from FPGA easy

• Metal Configurable Standard Cell (MCSC) • Supporting 65nm and 40nm

• UltraShuttle• low risk silicon verification

• Proven RTL to working silicon methodology• Production ready - DFT, ATPG and BIST

LAYERING ON RISC-V

CODIX BERKELIUM PROCESSOR

∠ Codix Berkelium delivers RISC-V instruction-set compatibility, allowing users to leverage the rich ecosystem of software and tools becoming available, in addition to those provided by Codasip.

Processor Features• 3-stage 32 bit or 5-stage 32-bit or 64 bit• Support for standard extensions (A, C, F, etc.)• Configurable general purpose registers• Compiler or hardware-based hazard avoidance• Configurable interrupt support• Configurable branch Prediction unit• Configurable sleep mode support• Optional instruction and data cache• JTAG support with full debug support• Full custom extension support• Complete LLVM/GNU SDK including profiling,

emulation, etc

Registers

Min area constraint

Max freqconstraint

Gates Freq. Gates Freq.Codix –Bk3 1740 20901 54.6 33979 431.4Codix –Bk3C 1807 22364 54.6 36332 419.8Berkeley Chisel Zscale 2117 22335 59.2 33549 355.5Berkeley VScale 1864 20870 44.2 38921 339.6

EASY EXTENSIBILITYUpdated Model

Codix-Bk

by Codasipor

by Customer

Automatically generated SW and HW infrastructure

SDK

HDK

Application Driven Analysis

Specification Driven Analysis

Powerful tools simplifyIdentification of optimization

opportunities

Easy to update and configure processor

models

Complete development infrastructure that is optimized to, and understands,

your unique processor

The Codasip team required only days to implement WalnutDSA, a project that previously would have required as many as three calendar months [while improving performance].

Quantum-Resistant IoT Security on RISC-V, SecureRF

NEXT ADD DEBUG, BRING-UP, AND SOC ANALYSIS

System block

UltraSoC

UltraSoC Infrastructure

Byte Stream

Additional Monitors

Accelerator Graphics Security Engine

Custom Circuit

Processor

Processor Analytics Module

Bus Master/Slave

BusMonitor

Custom Circuit

Status monitor

Memory Controller

USB

USB Comm.

JTAG Control

System Interconnect

Supports subsystems with different power domains, clock domains

Portfolio of configurable modules, optimized for different system IP blocks

Flexible, scalable message fabric, easy to route

Debug & trace is transparent: does not impact system bus

Modules are protocol aware and “smart” with filter and trace

PROBLEMS ULTRASOC SOLVES

DDR3

Interconnect

DFI-PHY DRAM controller

Interconnect

RAMDMA-1

Peripheral Interconnect

USB MAC

Turbo

DSP

Processor

I$

D$

I TCM

D TCM

Processor

I$

D$

I TCM

D TCM

DSP

PHY

DMA-2

DSP

Timer

Radio IFRadio IF

FFT

Interconnect

Bus mon

Bus mon

Status mon

Status mon

Status mon

Status mon

Status m

on

UltraSoC Infrastructure

Debug Hub

UltraSoC IP

Security

Status m

on

Status m

on

Status m

on

BM

BM

SM SM

SM SM

SM

SM

SM SM

DebugHub

UltraSoCIP

UltraSoCInfrastructure

WhydosomeDMAtransferstaketoolong?

WhyistheCPUnotasfastasexpected?

Whatisgoingonwithmymemory

controller?

Whydoesthesystem

occasionallyhangor

deadlock?

WhyismyinterconnectslowerthanIexpected?

CanItrustsystemsecurity?

FINALLY WE NEED THE APPLICATION LAYER

• LLVM is the glue that holds the solution together

• Allows multiple vendors to collaborate easily

• Increases return on invest by allowing portability

Device-specific programming

Device-specific specification Device-specific testing and validation

Higher-level language enabler

SPIR/SPIR-V/HSAIL specs Conformance testsuites

C/C++-level programmingOpenCL/SYCL

specs Clsmith testsuite Conformance testsuites

Wide range of other testsuites

Graph programming

Validate graph models Validate the code using standard tools

Device-specific programming

Assembly language VHDL Device-specific C-like programming models

Higher-level language enabler

NVIDIA PTX*HSA OpenCL SPIRSPIR-V

C/C++-level programming

SYCL NVIDIA CUDA*HCC C++ AMPOpenCL

Graph programming

OpenCV OpenVX Halide VisionCpp TensorFlow Caffe

SUPPORTS A LAYEREDPROGRAMMING MODEL

• From machine learning to device control

• Program at any level you desire

• Each level/layer is well specified, tested and validated

* Not supported by Codeplay

MACHINE LEARNING à SILICON

• Open Standards benefit from clear specification, testing and validation per standard• Codeplay has products to deliver each layer• Flexible for evolution of standards, products, scaling and market demands

Device-specific programming••LLVM

Higher-level language enabler••OpenCL SPIR

C/C++-level programming••SYCL

Graph programming••TensorFlow••Caffe••OpenCV••VisionCpp

COMMON IDE INFRASTRUCTURE

20

Eclipse provides a common interface throughout the solution.

WHAT DOES IT MEAN FOR YOU?• Concept to silicon

in record time• Do in weeks what took

months

• Proven low-risk solution• We’ve done the work so

you don’t have to

• Based on open standards• Use only what you

want/needMPSC

FPGA Porting

RICH foundational IP Library

Advanced Debug, Analysis, optimization

Application optimizedRISC-V

LLVM

OpenCL

TensorFlow OpenCV

SYCL

WHAT’S NEXT• Testchip taping out very soon

• Will be available to interested parties• Also exploring general availability on dev-board

• Continuing to add more collaborators• Proactive R&D investment from all involved• Stay tuned for more announcements

• Aim is to provide a platform from prototype to scaling• De-risk RISC-V for any and every design

Thank You For Your Attention