rca engineer · uama engineer a technical journal published by the rca technical excellence center...

RCA EngineerVol 30 No .2 Mar./Apr. 1985

uama EngineerA technical journal published by theRCA Technical Excellence Center 0 13 Roszel Road 0 P. 0. Box 432 0 Princeton, NJ 08540-0432 0 Tacnet: 226-3090

RCA Engineer Staff

Tom King Editor

Mike Lynch Associate Editor

Louise Carr Art Editor

Mike Booth Composition Specialist

Maria Pragliola Secretary

Editorial Advisory Board

Tony Bianculli Manager, Engineering Information, TechnicalExcellence Center 0 Jay Brandinger Staff Vice -President, Sys-tems Engineering, RCA Laboratories 0 Jim Carnes DivisionVice -President, Engineering, Consumer Electronics Division0 John Christopher Vice -President, Technical Operations, RCA

Americom 0 Jim Feller Division Vice -President, Engineering,Government Systems Division 0 Mahlon Fisher Division Vice -President, Engineering, Video Component & Display Division Larry Gallace Director, Product Assurance, Solid StateDivision 0 Arch Luther Senior Staff Scientist, RCA Laboratories0 Howie Rosenthal Staff Vice -President, Engineering 0Bill Underwood Director, Technical Excellence Center 0Bill Webster Vice -President, RCA Laboratories

Consulting Editors

Ed Burke Administrator, Marketing Information and Commun-ications, Government Systems Division 0 Walt DennenManager, Naval Systems Department Communications andInformation, Missile and Surface Radaro John PhillipsDirector, Business Development, RCA Service Company

Cover design by Robert FredricksonAutomated Systems Division,Burlington, Mass.

0 To disseminate to RCA engineers technical information ofprofessional value 0 To publish in an appropriate mannerimportant technical developments at RCA, and the role of theengineer 0 To serve as a medium of interchange of technicalinformation among various groups at RCA 0 To create acommunity of engineering interest within the company bystressing the interrelated nature of all contributions 0 To helppublicize engineering achievements in a manner that willpromote the interests and reputation of RCA in theengineering field 0 To provide a convenient means by whichthe RCA engineer may review professional work beforeassociates and engineering management 0 To announceoutstanding and unusual achievements of RCA engineers ina manner most likely to enhance their prestige andprofessional status.

Automated testing: An essential part of RCA's futureWhen one considers that 30 years ago the prim-ary use of automated testing was for continuitytests of cable and wiring harnesses, the scopeof contemporary automated testing applicationsis most impressive. Automated testing hasspawned its own version of such disciplines asapplication software development, system archi-tecture, and test instrumentation. Automatedtesting is now integral to the manufacturing pro-cess-a check on the integrated circuit, theboard, the subassembly, and the final productbefore it reaches the customer. Product accep-tance, and therefore product sales, are a func-tion of testing integrity as well as fundamentaldesign. In the factory, automated test providesquality feedback in the near real-time. In thefield, automated testing cuts the downtime forfault detection, diagnosis and repair of complexsystems-systems that would be impossible tomaintain without automated testing.

Automated test engineers have known some-thing about their field that has been only recentlydiscovered by their fellow engineers: Automatedtesting is pervasive. There is no product, no dis-cipline, no technology that is not a tool or achallenge for automated test engineers. Theyapply operations analysis to model and optimizethe potential application. They call upon

advanced system development tools to build testlanguage compilers and operating systems fordistributed -architecture automated test equip-ment. Test applications range from consumerelectronics to turbine engines to laser designa-tors. The most promising near -term payoff in thefield of artificial intelligence is expert systemsapplied to diagnostics. As part of automatedtesting expert systems are on-line now, provid-ing diagnostic support to computer field engi-neers and monitoring power generating stations.

Automated testing is forever in transition, andthe watchword for 1985 appears to be "integra-tion." Testing functions are being integrated withthe prime system design so that monitoring anddiagnostics are built in. Testing functions arealso being integrated with the manufacturingand maintenance processes. The dividing linebetween operation and test, between prime andtest equipment becomes blurred and disap-pears. It's an exciting time to be working inautomated testing.

David M. PriestlyDirector, Automatic Test SystemsAutomated Systems

rnmai EngineerVol. 30 INo. 2 Mar. lApr. 1985

overview 4 ATE trends into the 90sO.T. Carver

software for test 9 Artificial intelligence concepts applied to ATE softwareD.A. Krieger

14 Automated flowchart generationM.G. Glenny IA.B. Wong

measurement 22 A laser measurement system for high -accuracy automated near -fieldprobe trackingT.D. Fuhr

IC testing & 29 Parametric testing of integrated circuits-an overviewanalysis W. A. Bosenberg IN. Goldsmith

34 A software system for the collection and analysis of electrical dataF.W. Brehm

40 Integrated circuit engineering analysis systemF. McCarty

47 Wafer electrical testing in the factory environmentW. Price

departments Patents, 521 Pen and Podium, 531 News and Highlights, 55

Copyright © 1985 RCA CorporationAll rights reserved

in this issue . . .

automated testing

Carver: "Built-in test and testability at the chip, board, subassembly,and system level will finally become a reality because they are neededin the manufacturing process."

4

AUTOMATEDLOGISTICS

Krieger: ".. . using Al concepts for guidance rather than as a frame-work, we proposed and developed a data flow network approach toLevel I (fault detection) vehicle diagnostics."

Glenny/Wong: "Automated flowchart generation is a computerizedprocess for creating a flowchart representation from the source code ofa program."

OFL TO DIGRAPH

CONVERTER

FORMATTEROUTPUT

GENERATOR

14 SYSTEM EXECUTIVE

9

NODE 2

ARC 2

Fuhr: "The automation of the laser measurement system makes itpossible to calibrate the scanner immediately prior to any antennascan . . ."

22

12

0

BOsenberg/Goldsmith: "The prime function of parametric testing inan integrated circuit manufacturing environment is to ensure that thecomplicated fabrication process used to produce the integrated circuithas been completed satisfactorily."

Brehm: "The goals of the system design are met by hiding the tricky,tedious, difficult, and error prone aspects from the experimenter."

McCarty: "Many factors were considered in making the decision topurchase an engineering analysis software package from a vendor."

Price: "There are many wafer parameters measured during process-ing, but WET measurements represent the result of all processing stepsand their complex interactions."

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ENGINEERINGANALYSIS

DATA BASE

47

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in future issues . . .

statistics in manufacturing30th anniversary issuecomputer graphics

O.T. Carver

ATE trends into the 90s

The two primary areas of change in the next generation of ATEwill be the user/maintainer's interaction with the system andthe ATE's integration within the parent application.

Automatic test systems now serve in twodistinct applications: testing as a part ofthe manufacturing process, and testing aspart of field service or a maintenanceprocess. Manufacturing test objectives areproduct quality and yield in a batch modeenvironment. Field service or maintenancetesting objectives are fault isolation as thefirst step in repair and return to operation.The service test environment is randomarrival of tested items by type. Manufac-turing test anticipates assembly faults suchas missing parts and solder splash shorts.Service test assumes that the item onceworked and problems are caused by failedcomponents.

The different test objectives and testenvironments have shaped two divergingautomatic test systems approaches. Manu-facturing tests incorporate in -circuit tech -

Abstract: There are two broad auto-matic testing applications (1) testingwithin the manufacturing process wherethe objective is product quality assurance,and (2) testing within the maintenanceprocess where the objective is to returnfailed items to operation. As ATE marketdrivers, these two applications have stimu-lated divergence in system design. But thedivergence will become convergence as aresult of what's happening in primeequipment design rather than by deliber-ate planning on the part of ATE develop-ers. Built-in test and testability at the chip,board subassembly, and system level willfinally become a reality because they areneeded in the manufacturing process.

a1985 RCA Corporation.Final manuscript received February 5, 1985.Reprint RE -30-2-1

niques, where a fixture provides test accessto nodes and circuit paths on the board.In -circuit tests are primarily static, andtest procedures are automatically derivedfrom circuit topography. Field service testsare aimed at operational faults and dependon functional tests that exercise the unitunder test (UUT) in almost the same waythe item is stressed in normal operation.Maintenance diagnostics require monthsto develop and validate. Manufacturingtesters incorporate test item handlers andsimple robotics to take advantage of through-put gains in the batch mode. Maintenancetesters are likely to involve instructedprobing by the ATE operator. Manufac-turing test programs are more likely to becoupled to CAD data; maintenance test-ing is likely to be coupled to the logisticsystem.

Both test approaches are being chal-lenged by higher operating speeds and thelonger test requirements of LSI/VLSI popu-lated boards and modules as more andmore functions are packaged in the samevolume. This means test functions becomemore removed from direct, or even im-plied, access through external ports.

Changes underwayThere is a pervasive change underway inprime equipment design that will put manu-facturing and maintenance on a conver-ging, rather than diverging, path. Designfor testability has long been a designatedsolution for problems of mismatch betweenthe test system and the tested item. If theprime designer would develop a test ap-proach and let that test approach shapethe design, the end product would reducethe need for complicated interface devices

and cumbersome test techniques that arenow developed after the fact by the ATEapplications test program designer. Thedesignated solution has failed because thereis a lack of real incentive for the primeequipment designer to help solve the main-tainer's problems.

Herein lies a basis for change. Withlarge scale integration and embedded micro -processing at lower and lower functionallevels, conventional test techniques are in-adequate for development and manufac-turing needs. In order to test the chip, testcapability is designed into the chip. Tento fifteen percent of the total chip area istypically assigned to test functions. Thispercentage of a chip with several hundredthousand transistors represents significanttest capability. More test functions on thechip means less test system complexity offthe chip-a good trade-off. Test capabili-ty at the lowest level, the chip, makes iteasier to provide built -in -test (BIT) at theprinted circuit board (PCB) and modulelevels. This is exactly the approach es-poused for years by test system develop-ers and test software designers. Testabilitywill become a reality because the incen-tive is payoff in design and manufacture.The benefit to service and maintenancetesting will be equally dramatic, althoughit comes as a gratuitous secondary effect.

Impact of BIT on ATE

As an indication of the BIT impact onATE, consider the experience with avi-onics on the Boeing 757/767 aircraft.' Ex-tensive BIT was introduced in the slatelectronics unit. Table I is a comparisonof application test program characteristicsfor the electronics unit with and without

4 RCA Engineer 30-2 Mar. / Apr. 1985

Table I. 757s1at electronics unit test pro-gram characteristics

Without BIT With BITNumber of tests 750 182Lines of ATLAS 9000 4500Run time (min.) 90 20Hours to produce 9400 2300

BIT. Test programs were written for thesame ATE. Note that the time to run thetests, a recurring maintenance cost, was re-duced by a factor of about 4 to 1, so thepayoff was not limited to the develop-ment cost.

There is another significant trend withpotential important ATE impact as a resultof the confluence of several other ideas.The trend is the winnowing of mainte-nance levels to service/repair operationsin the user location and maintenance oper-ations at a depot or factory. "Repair" inthis context can be as simple as pull andreplacement of plug-in modules or boards.In the military, each service has an inter-mediate level of maintenance, populatedby test and repair shops, supporting supply,inventory control and administration re-sources. There is growing incentive to elimi-nate or reduce the large investment andon -going logistics cost of supporting theintermediate maintenance function.

These evolutionary trends are illustratedin Fig. 1. Tester technology spans theATE architecture, subsystem implementa-tion, and test techniques. These will fuseinto a generic test configuration with in -circuit, functional, analog, digital, and hy-brid capabilities. It will be linked to func-tional levels above testing-assembly, testand rework, and field maintenance.

Off-line maintenance today is multilay-ered. The user recognizes a system pro-blem, perhaps aided by system self monito-ring, and performs first -level maintenance.This action may introduce a repairable,replaced item into a logistic channel on itsway to another maintenance level. Theuser's action could also be a call to anothermaintenance level for help. The repairableitem may itself be repaired by introducinganother repairable item into the queueawaiting maintenance at another, highermaintenance level.

Maintenance levels are populated withtesters, spare parts, repair benches, people,and procedures. They are very expensive.They are interconnected by logistic pipe-lines that are also very expensive-andthey leak. Hence the incentive to mergemaintenance levels and the appeal of aneffective built-in test that diagnoses to athird or fourth level.

1985 FUTURE

TEST TECHNOLOGY

MANUFACTURINGTEST

MANUFACTURINGTEST

GENERALTEST

OFF-LINE MAINTENANCE

USER MAINTENANCE

MULTI -LEVEL

INTERMEDIATELEVEL

MAINTENANCE

PRIME SYSTEMBIT

TO CHIP

ATE SELF MAINTENANCE

ALGORITHMICDIAGNOSTICS

INSTITUTIONAL TRAINING

HARDCOPY TECH MANU .

FIELD ENGINEERS

EMBEDDED EXPERTSYSTEMS AND

COMPUTER AIDEDINSTRUCTION

Fig. 1. Evolutionary trends in ATE.

ATE self maintenance, now an amal-gam of diagnostic software, technicians,technical manuals, and access to a fieldengineer, will evolve toward not only BITbut embedded expert systems and intelli-gent computer -aided training.

The DoD has a farsighted view of theinterrelation between test equipment, tech-nicians, repairables handling, expendablestransportation, etc., and the need for newtechnology in these areas. Under the nameof Logistics R &D, there are specifictechnology needs that are targeted andgiven priority in the allocation of resources.

A priority Air Force objective is thereduction or elimination of intermediate -level maintenance. A demonstration pro-ject, know as Pave Splinter, has beeninitiated. The approach is to incorporateadequate testability, BIT, and reliabilityimprovements in an avionics subsystem toeliminate the need for an intermediateshop's resources.

The mechanism for integrating the main-

tenance levels is elimination of the inter-mediate workload by reducing failure ratesand by embedding test functions in theprime system. Historically, failure rate im-provement has come from most of thenew technology thrusts, especially large-scale integration.

Integration also will occur in anotherdimension. As previously discussed, manu-facturing test software will become moreclosely coupled with CAD data. Test pro-grams will make use of circuit designtools and computer -generated data deve-loped during the design process. An anal-ogous trend can be expected in service/maintenance testing. Automatic test willbe linked with such functions as:

Workload scheduling. Incoming testitems will be bar-code scanned and en-tered into workload pool. The ATEwill maintain, through its internal sur-vey and monitor functions, a status ofits test capability in terms of specific

Carver ATE trends into the 90s 5

1985

MAINTENANCE FUNCTIONS

INCOMING INSPECTION

MAINTENANCEMANAGEMENT

TEST ANDDIAGNOSTICS

REPAIR/ALIGNMENT

SPARES INVENTORYAND ACQUISITION

POST REPAIRQUALITY ASSURANCE

FUTURE

AUTOMATEDLOGISTICS

Fig. 2. The future of ATE.

units under test (UUT) that it is pre-pared to test. For example, if one chan-nel of its dual pulse generator is notfunctional, the system monitor will scanthe UUT list and delete those unitsrequiring the dual channel pulse stimu-lus. The system monitor also tracks sta-tus of interface connection devices, ca-bles, and test application software. In-dividual UUT test time and status ofcurrent testing are also known. Trig-gered by the UUT identification readby the bar code scanner, an incrementof test workload will enter the systemand all the above information can beprovided to the maintenance manager.This information would be a basis forworkload assignment to test stations andto test operators. Decisions to batch,assign priorities, or tailor a test stationworkload to digital PCBs or rf unitscan be made and updated for greatestproductivity or for best response timeto the customer.

o Real-time inventory control. Auto-mated diagnosis provides the first indi-cation of a failed item. This informa-tion, networked electronically with theprocessor that tracks items in stock, candetermine whether a spare is availableand, if so, designate a spare to a specificrepair task and then update the sparesavailable inventory. As part of inven-tory control, replacement spares requi-sitions can be initiated, accumulated,

and parts can be ordered according tologistic stock rules.

Maintenance management. Automateddiagnosis can also provide repair man-hour estimates, examine a priority queue,and schedule repairs according to need,spare parts availability, and repair re-source availability. Maintenance historyfor each type of unit under test can betracked, along with ATE test stationstatus, and workload trends over timeversus prime system type. Projectionsof workload and test station availabilitycan be provided for a new mix of primesystems to be supported, answering suchquestions as "what happens to turn-around time if the number of systemsthat my test station supports is doubled?"ATE system software will be enhancedby expert systems that assist the opera-tor in system self -test and restore -to -service. These systems will be highlyinteractive, and will adapt to the in-creasing skills the user gains throughexperience. The resident expert systemwill "learn" from ATE failure history,with the knowledge base and inferencesystem updated and even tailored to theparent ATE.The integration of maintenance func-tions is illustrated in Fig. 2. As the tes-ter is seen today, it interacts with theoperator/maintainer, with the item undertest, the test software, the interface de-vice, and the instruction manuals. Its

Tom Carver holds a BSEE and an MEd,and has been involved in automatic testprograms at RCA since 1956. His programexperience includes the Multi -PurposeTest Equipment (MPTE), an early modular,general-purpose ATE built for the Army,fundamental studies to develop algorithmsfor automatic test point location, and sup-port for modeling tools used to evaluatealternative maintenance concepts. Currentprograms include Post Deployment Soft-ware Support for the AN/USM-410, longrange AN/USM-410 product improve-ments, and AI/ATE applications.

Mr. Carver has served on the AUTO-TESTCON Board of Directors, is amember of the IEEE Instrumentation andMeasurement Society AdministrativeCommittee, and a member of the NSIA-ATE Committee.

Contact him at:Automated System DivisionBurlington, Mass.Tacnet: 326-3241

function is constrained to test and diag-nosis. But the end objective is mainte-nance, and this involves all the func-tions just described. Today, these func-tions interact through manually generateddata transfers, largely on paper. In auto-mated logistics, the ATE will look morelike a maintenance subsystem, less likestand alone test equipment.Prime system technology that mightstress ATE capability will appear in fourareas:

(1) High-speed, high -density large-scaleintegration as typified by the DoD VHSICprogram.

(2) Millimeter wave radar and communi-cations systems. The frequency increasesare likely to come in three categories: 1)up to about 45 GHz, 2) from 45 to 100


GHz, and 3) beyond 100 GHz. There area number of systems in use or in devel-opment in the first category and prototyp-ing is underway in the other two.

(3) Complex modulation schemes dictatedby secure communications and frequencyspectrum crowding. These systems areoperational.

(4) Enhanced ATE capability into suchhybrid areas as electro-optics; ATE appli-cations will expand from current, rathermodest use in electro-optics test.

ConclusionThe differences between factory ATE andoff-line maintenance ATE will disappear.

Maintenance testers will support in -circuittest fixtures. Both types of ATE will de-pend on prime equipment BIT to simplifytest requirements.

Effective built-in test will be common-place, being "designed in" because of in-centives for effective testing during de-velopment and manufacture. In the field,ATE will merge and be used with theprime equipment as built-in maintenanceprocessors operating over a dedicated main-tenance bus that tracks status and diag-nostics down to the individual chip.

ATE will ride the fast -paced computertechnology horse, providing ATE con-trollers with more processing power atless cost in reduced space. This processingpower will be distributed into each func-

tional block. Architecture will continuethe trend toward distributed processingand the use of standard buses. The sys-tems will incorporate expert systems tosupplement conventional algorithmic diag-nostics. Embedded intelligent computeraided instruction will adapt to the needsand skill level of the individual operator.Technical manuals will disappear.

References

I. J.J. Seli, "Automatic Test System Response C IFuture Needs," Proceedings, 1984 Conference onSupporting Weapon System Technology Throughthe 1990's (August 14-16, 1984)

December 1984 issue of RCA Review availableSpecial issue: Microwave and Millimeter -wave Devices and CircuitsThis special issue of RCA Review contains someof the papers presented at the IEEE PrincetonSection Sarnoff Symposium on Microwave andMillimeter -wave Devices and Circuits held atRCA Laboratories on March 24, 1984. Thisannual symposium is gaining popularityamong researchers working in advanced mic-rowave technology, in both government andindustry.

Several papers describe advances of currentinterest in the application of millimeter -wavedevices and circuits. The use of power sources,the design of passive monolithic components,and a new look at high -resistivity silicon forconstructing monolithic millimeter -wave cir-cuits are discussed.

A method is presented for fabricating mono-lithic circuits in GaAs that eliminates the tradi-tional tradeoff between their thermal andelectrical properties. The remaining paperscover components specifically designed forsatellite communications systems, anotherarea in which microwave technology is impor-tant .

RCA Review is a technical journal publishedquarterly by RCA Laboratories in conjunctionwith the subsidiaries and divisions of RCA Cor-poration. A one-year subscription to RCAReview costs $12.00, and back issues are $5.00(employees get a 20 percent discount);reprints of individual papers are generallyavailable from the authors.

IntroductionM. Nowogrodzki and L. C. Upadhyayula

Advanced Applications and Solid -State Power Sourcesfor Millimeter -Wave SystemsGlenn R. Thoren

Millimeter -Wave Monolithic Passive Circuit ComponentsS. C. Binari, R. E. Neidert, G. Kelner, and J. B. Boos

Silicon Technology for Millimeter -Wave MonolithicCircuitsPaul J. Stabile and Arye Rosen

A GaAs Power FET Suitable for Monolithic Integration, withLaser -Processed Gate and Drain Via ConnectionsR. L. Camisa, G. C. Taylor, F. P. Cuomo, W. F. Reichert, andR. Brown

Advances in Design of Solid -State Power Amplifiers forSatellite CommunicationsB. R. Dornan, M. T. Cummings, and F. J. McGinty

Communication Receivers for Satellites-A ReviewH. B. Goldberg and S. S. Dhillon

A 14-GHz Cooled Low -Noise GaAs FET Amplifier forCommunication Satellite ApplicationG. R. Busacca, P. A. Goldgeier, H. B. Goldberg, M. Noyes,and A. Chuchra

20-GHz Lumped -Element GaAs FET Driver AmplifierShabbir S. Moochalla and Donald E. Aubert

Limiting Amplifier for Instantaneous Frequency Measur-ing SystemRobert E. Askew

Carver: ATE trends into the 90s 7

New book available:Frequency AllocationsThe newest edition of Fre-quency Allocations has justbeen published by the RCAFrequency Bureau. This attrac-tive pocket -sized book con-tains all international and U.S.allocations and regulations upto November 1984, includingthe results of the 1979 and1983 World and RegionalAdministrative RadioConferences.

This new edition features:

Worldwide allocations for allfrequencies between 9 kHzand 300 GHz. A world mapshows each of the ITURegions.

U.S. Government and non -Government allocationsprinted on studies of poten-tial radio interference.

Radio service assignmentslisted by Primary, Secondaryand Permitted uses in eachfrequency band.

A complete set of interna-tional, U.S. domestic, U.S.Government and U.S. non -Government footnotes thathelp explain or define thelimon certain allocations.

Other sections identify eachfrequency and wavelengthband, provide the title foreach FCC Rule Part, explainthe new emission designa-tions, and list all U.S. IVbroadcast channel frequen-cies, standard frequencies,and special industrial, scien-tific and medical frequencybands.

For the system design engineerand engineering manager, thisreference may be invaluable. Itis the only publication we haveseen that contains such oftenneeded information. Its smallsize and new flexible bindingare perfect for carrying in ajacket pocket or tucking awayin a briefcase.

RCA employees may pur-chase a copy of FrequencyAllocations for $4.00 (regularprice is $5.00) through Mrs.

Dora Mineo, RCA FrequencyBureau, One IndependenceWay, Princeton, N.J. Makechecks payable to RCA Corpo-ration. Non -RCA purchasersshould address Mrs. Mineo atP.O. Box 2023, Princeton, N.J.08540. For further informationabout placing companyorders or quantity orders (10 ormore), please call Mrs. Mineoat Tacnet 254-9566 or (609)734-9566.

Guide to the 215 -page frequency allocation table.

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letters.

Permitted Service is shownwith slash marks aroundcapital letters.

INTERNATIONAL TABLEANx

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D.A. Krieger

Artificial intelligence concepts appliedto ATE software

New user demands on ATE impel the diagnostic engineer toexplore new ways to overcome the limitations on conventionaldiagnostic software.

The STE-M 1 /FVS is a microprocessor -based, software -driven portable test set. It isdesigned to thoroughly test the functionaland operational integrity of the AbramsM I Tank and the Bradley Fighting Vehicle(BFV). When a problem in the vehicle isdetected it will be fault -isolated to the levelof a cable or line replaceable unit (LRU).

The present software provides what is, ineffect, an automated diagnostic flow chart.A subsystem test initially instructs themaintenance mechanic to configure thevehicle into a known state. Then it takes a

Abstract: There is growing interest indesigning ATE systems that are easier touse, more economical to program, andcapable of handling multiple faults in theunit under test (UUT). This has led us toexamine and combine a number of ad-vanced software concepts that enhance thediagnostic performance of our small port-able test set (STE-M1/FVS). The tech-niques and theories of artificial intelli-gence (AI) suggested much of our ap-proach, and the format of a data flownetwork was used to implement the toplevel test strategy. The data flow represen-tation satisfies the criteria for a good Alrepresentation, yet provides for efficientcomputation with a minimum of resources.This paper reports on an enhanced soft-ware development project completed atRCA Automated Systems.

©1985 RCA Corporation.Final manuscript received January 29,1985.Reprint RE -30-2-2

measurement and compares its value to apredefined set of limits. On the basis of thiscomparison, the test either continues itsLevel I fault detection task or branches intoLevel II fault isolation routines. Level Irefers to measurements made at the testconnectors of the vehicle, which serve nofunction other than test point connection.Level II refers to measurements made with"T" shaped adapter hook-ups, which per-mit the test set to trace signals that arepassed from an electronic box, through acable, to another electronic box or device.The unidirectional, tree traversing nature ofthe approach means that diagnosis stops atthe first isolated fault. Thus minor faults canmask the detection of major problems.

A corrective solution allows the Level Iprocess to continue as far as possible, col-lecting and storing pass/fail informationbut delaying Level II fault isolation pro-cedures until all the contextually relatedinformation has been collected.

Additionally, the present diagnostic soft-ware obscures diagnostic knowledge that isdispersed throughout a flow chart. Thismakes maintenance and modifications ofexisting software very difficult because themeaning of a particular piece of code liesdeeply buried in the entire structure of thetest. In general, flow charts do a good jobdescribing a program, but they are a poorrepresentation for diagnostic knowledge.The overall test strategy remains hidden bythe representation.

A clear representation is important forpractical, not simply for aesthetic reasons,because it enables the diagnostician to con-

figure and debug diagnostic knowledgerather than diagnostic programs. It facili-tates creative problem solving by humanbeings. One branch of AI deals with thedevelopment of knowledge -based expertsystems. These systems employ symbolicmanipulation (as opposed to standard nu-merical algorithms) to solve problems thatrequire uniquely human reasoning abilities.Since these systems manipulate symbolsinstead of numbers, the development ofpowerful new forms of knowledge repres-entation is critical to success. Patrick Win-ston,' a pioneer in this area, gives the fol-lowing list of desiderata for good repre-sentations:

They make important things explicit. They expose natural constraints. They are complete. They are concise. They are understandable. They facilitate computation. They suppress detail. Rarely -used

information is kept out of sight butis still accessible.

They are computable by existingprocedures.

With these things in mind, and using AIconcepts for guidance rather than as aframework, we proposed and developed aData Flow Network approach to Level I(fault detection) vehicle diagnostics. Thisapproach allows maximum vehicle infor-mation to be quickly collected and effi-ciently stored, deferring the Level II faultisolation process until all possible relevantvehicle information is collected. It also ful-

RCA Engineer 30-2 Mar. / Apr. 1985 9

A role for artificialintelligence in ATE

Research work in the artificialintelligence (Al) field has beenwidely reported on within the pasttwo years, but the practical appli-cations remain few and highlyspecialized. Do you really needexotic programing languagesencoded on machines with superspeed and untold memory banksfor practical uses of Al? Can youreally expand Al past the gameplaying stages, beyond the "if -then -else" rules implementationof an expert system? These arethe practical questions that needto be addressed when Al is beingdiscussed.

At RCA's vehicle test systemsengineering group, these are farmore than academic questions.Since the mid 1970s we havebuilt microprocessor test sets thatfault -diagnose Army vehicles,with portable "suitcase" hardware(simplified test equipment) thatthe Army mechanic carries up toor into the truck, jeep, or armoredvehicle. Our test systems facemany of the problems that arenow the focus of Al development.These test systems lack stimulusor means to manipulate vehicleand weapon system controls, andtherefore a constant dialoguewith the operator/mechanic isnecessary. This is accomplishedby using a terse, 40 -characterdisplay on a hand-held set com-municator. Expert troubleshootingdiagnostics are encoded in thetest set, and only "yes/no"responses are expected from themechanic observing vehicle con-ditions. The problems we expe-rience with field use and fieldacceptance of the test set appearto be suitable candidates for Alsolutions. What are these prob-

lems, and what have we learnedabout the potential for Al?

We know that our operators(mechanics) get bored followinglong sequences of terse mes-sages ("turn on turret power","press and hold palm switch").We realize that the test set tellsthem nothing at all about the pro-gress of the test until the veryend. Successful Al expert sys-tems all use (or have added) fea-tures to explain to the user whatthe system has concluded, what ithas done, and why. Those Al sys-tems interface with reasonablyskilled technical personnel, how-ever; we find it difficult to relatethe internal conditions of elec-tronic systems to mechanics whoare not proficient in readingschematics (or are not givenschematics).

We know that our diagnostictest logic was both designed andtested on the basis of singlefaults. Army vehicles are notalways repaired on the immediatedetection of failure conditions,because the vehicle may stillserve useful and needed func-tions. Testing in the presence ofmultiple faults creates severalproblems:

o Diagnostics valid with singlefaults may fail with multiplefaults.

o The mechanic may be confusedor frustrated by "finding" a dif-ferent fault than the one hewanted to fix.

o Discovery and then fixing faultsone at a time prolongs the over-all repair time. Most userswould like to find all faults withone pass.

o Conventional diagnostics canrarely continue to test after find-ing the first fault condition in thetest sequence, because subse-quent test logic relies on the

condition of the precedingresults.

The article by Dave Krieger de-scribes what we are doing to im-prove the format and content ofour programmed test logic, to im-prove the diagnostic accuracy ofthe test set, and enhance itsacceptance to the user. What hedescribes may not look like Al.But there is an Al influence, and itwas Al concepts that led us toour present position. We alsorealize the potential and need forfurther enhancements, and weexpect that Al will again provideinvaluable guidance.

When I look at his "depen-dency diagram" and "localexpert" modules, I realize thatnothing really new is embodied,only the means of representation.But what a difference that repre-sentation makes. Previous diag-nostic logic spread evaluation oftransfer functions throughout thetest. Krieger has brought theminto his local expert cluster. Hecan now represent the flowchartlogic at a higher level. This is anexcellent improvement for thedesigners and maintainers of thesoftware, and it may be especiallybeneficial for the test set opera-tor/ mechanic. For the first time,we may be able to tell the userwhat is happening in terms of"hand stations have malfunction",or "power distribution is OK",because of having clustered theevaluation of functions recogniz-able to the user.

More important, the test strat-egy is changed. Faults aredetected and noted (pass/failflags), but fault isolation is post-poned. The new style test isdesigned to continue testing afterthe detection of faults, and it con-tinues to evaluate the perfor-mance of "local expert" functions

fills most of the aforementioned criteria fora clear representation.

Data flowFigure 1 presents, in the most general terms,the conventions we adopted for our dataflow model. Basically, it is a directed graph.

Each node in the graph is an independentmodule of diagnostic logic that correspondsto the constellation of hardware that makesup a functional subsystem. This we call alocal expert. Whenever possible, it can testits designated subsystem independentlyfrom other local experts. The nodes areconnected to one another via arcs. After a

local expert executes, it sets its output arceither logic true or false depending, in part,on how far a set of subsystem measure-ments differ from the mode. The state ofthese arcs can enable or inhibit the execu-tion of other nodes (local experts). Refer-ring to Fig. 1, when node 1 executes, it setsarc 1 either logic true or false. If arc 1 is


until all permissable tests havebeen performed. At that time, theoperator/mechanic can be noti-fied of all malfunction conditions,although specific faulty replace-able components or cables maynot yet be isolated. Fault isolationcan continue at the operator'sdiscretion until all faulty compo-nents are pinpointed. This shouldplease users, because they canexercise decisions. In the future, Iexpect we will add intelligent gui-dance, advise users of the timeand resources they may need tomake the repairs, and even howto circumvent some of theproblems.

Krieger's implementation runson the same microprocessor testset that is currently fielded, usingthe same operating system,source code, and software devel-opment resources. Other than afew new measurement and stor-age constructs, the only thingnew is the organization and strat-egy. However, we realize that thenext steps may require significantaugmentations. A larger, graphicset communicator will be neededto convey more meaningfulinformation to the user. Morememory and faster execution maybe needed to search, hypothe-size, and even learn and adapt.New utilities will be needed tosupport the development, docu-mentation, and validation of thefuture enhancements.I suspect that when we bringsuch new concepts into practicalimplementation, we will oncemore look at the results and say,"but it's not really Al."

R. E. HartwellRCA Automated SystemsBurlington, Mass.

logic true and arc 2 from node 2 is logictrue, node 3 can execute. If arc 1 is logicfalse but arc 2 is logic true, node 3 is inhi-bited but node 4 is still enabled. Thus,regardless of the operational condition ofthe vehicle, all the logic that can executedoes. This yields maximum vehicle infor-mation during Level I testing. Figures 1 and

ARC INODES

NODE 1 NODE 3

- LOCAL EXPERT

- SMALL CHUNK- OF DIAGNOSTIC LOGICARC 2

NODE 2ARCS

- TRANSFERS INFORMATION FROM NODE TO NODE

- UNIDIRECTIONAL

- CLASSED BY DATA TYPENODE 4

- BOOLEAN

- INTERGER

- REAL

ARC 3 - ETC

Fig. 1. A generic data flow graph.

NODE 5

MEASUREMENTS - CAN BE REAL TIME ORSTORED IN MEMORY

PSEUDO -MEASUREMENTS - FROM OPERATOR QUERY

P/F NT* P/F NT* P/F NT*

PASS/FLAG FLAGS

* 3 STATES

- PASS

- FAIL

- NOT TESTED

* ALL FLAGS START OUT IN "NOT TESTED"

Fig. 2. The layout of a typical node.

2 show the conventions and terminologyadopted for our data flow representation.

After a node's logic executes, one or morepass/fail flags is set (not to be confused withan output arc). This reflects whether ahardware entity meets its performancerequirements or, in another sense, if itstransfer function (input to output) is satis-factory. These results are stored for later useby the fault isolation routines. The logicthat sets the output arcs determines if con-tinued testing along a network path is pos-sible in spite of a detected discrepancybetween the pass/fail limits and the measure-ment.

For example, if the potentiometer that

ARCS

PROVIDE ENABLE/DISABLE" INFORMATIONTO OTHER LOCAL EXPERTS

provides the speed reference signal to thetraverse servo is out of tolerance, its corres-ponding fail flag is set. However, anotherset of logic within the local expert deter-mines the state of its output arc. Basically,the local expert answers the question, "Isthe potentiometer so far out of adjustmentthat nothing can be learned about the rest ofthe servo?"

As the test proceeds, local experts exe-cute their diagnostic logic and put theirresults in logically encoded results registers(Fig. 4). At the end of the test, these regis-ters are examined by the test manager, thetop level of software, and a fault isolationstrategy is initiated. From symptoms and

Krieger: Artificial intelligence concepts applied to ATE software 11

MASTER

POWER

3001

TURRET

POWER

3002

TURRET

DRIVE

POWER

3003

ECA

HIGH

POWER

3004

.12 V DCTRAVERSE

POWER

3005

12 V DC

TRAVERSE

POWER

3006

15 VPROTECTION

3007

CHS

AZIMUTH

POT

3013

CHS

PALM

SWITCH

3010

GHS

AZIMUTHPOT

3014

GYRO

PHASE

POWER 0

3008

GYRO

PHASE

POWER

3009

OHS

R PALM

SWITCH

3011

OHS

L PALMSWITCH

3012

TRAVERSE

TACH

FULL RIGHT

3016

TRAVERSE

BRAKE

3015

TRAVERSE

TACH

NULL

3017

TRAVERSE

TECH

FULL LEFT

3018 FTRAVERSE

CURRENT

FULL HIGHT

3019

TRAVERSE

CURENT

NULL

3020

TRAVERSE

CURRENT

FULL LEFT

3021

TRAVERSE

GUN GYRO

FULL RIGHT

3022

Fig. 3. The data flow net for the Bradley Fighting Vehicle turret traverse subsystem.

measurements identified as present in thediagnostic situation, and those known to beabsent, the test manager derives a set ofconstraints. A constraint can be thought ofas a subset of the total vehicle situation thatmust or must not occur in the final diagnos-tic model of the failure.

When Level I data acquisition ends, thetest manager first looks at the arc informa-tion. An arc failure corresponds to somecatastrophic subsystem failure in the vehi-cle that prevents further testing along anetwork path. Typically, the mechanicwould want to fault isolate this problemfirst. Furthermore, the arc information isused to limit the search space to includeonly those subsystems whose correspond-ing local experts have fired.

Fault isolation

At this point all the pass/fail informationhas been logically encoded as a pattern oflogic ones and zeros in the pass/fail flagregister. A search for the physical cause(s)that led to this pattern involves generating abit pattern that has a known correspon-dence to a constellation of system faults (inother words, a hypothesis) and comparingit to the fault signature residing in the flag

register until a match is found.As AI helped guide the choice of repre-

sentation, the "generate and test" paradigmused by many AI programs provides theconceptual framework for fault isolation.'In our system a "hypothesis" is generated inthe form of a bit mask. It is tested by com-paring it to the bit configuration in the flagregisters. The crude representation at thepseudo assembler level is necessitated bythe physical and temporal constraints of asmall portable test set and its real-timemission.

Issues involved in the creation of a goodhypothesis generator include completeness,non -redundancy, and ordering. In our repre-sentation a complete hypothesis generatorwould simply be a binary counter thatwould generate every possible bit configu-ration and its known correlative of hard-ware failures. Obviously, for all but themost trivial systems, this is not practical ordesirable. In lieu of completeness, at thisearly point in the implementation, wesettled for a default mode that selectivelyvectors to presently fielded and validatedfault isolation routines if no pattern matchis found. This assures that for the worstcase, our system will perform as well as thesystem presently fielded. It also allows us toincrementally add and reorder smarter and

TRAVERSE

GUN GYRONULL

3023

TRAVERSE

GUN GYRO

FULL LEFT

3024

faster hypotheses while still producing im-proved and fieldable software.

The order in which hypotheses are calledand tested can present a complex problem.Our implementation employs a technique,well known in the AI field, called contextlimiting. This technique is used to limit thecombinatorial explosion inherent in rulebased expert systems. We use it in its mostbasic form, to partition knowledge intocontext related subsets. Ordering of hypo-theses within each of these subsets is drivenby our customers' priorities. Their need forspeed and ease of operator interactiondirects us to test for and eliminate thosecandidate faults involving the least operatorinteractions. Thus, our first group of hypo-theses would immediately lead to a diag-nostic conclusion, faulting an LRU or acable. Our second group would involveone cable disconnect, our third group mightinvolve two cable disconnects, a specialcable hook-up, and so on.

It is also conceivable to include thosehypotheses that correspond to known recur-ring faults, or faults that resist conventionaldiagnostic solutions. The power and flexi-bility of this approach are built into the dataflow representation. Optimum implemen-tations are system dependent and remain tobe studied.


PASS/FAIL FLAG REGISTERS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

L

ILOCS 11-161

LOC I I

3001A MASTER POWER

3002A TURRET POWER

30028 TURRET POWER

3003A TURRET DRIVE POWER

30038 TURRET DRIVE POWER

3004A ECA HIGH POWER

3007A +15V PROTECTION

30078 +15V PROTECTION

3005A +12V DC TRAVERSE

3005A -12V OC TRAVERSE

301IA GHS PALM SWITCH

3011B GHS PALM SWITCH

3010A CHS PALM SWITCH

30108 CHS PALM SWITCH

3008 0 GYRO PHASE POWER

3009 90 GYRO PHASE POWER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LOC 12

L 30I7A TACH NULL

30178 TACH NULL

30I6A TACH F.R.

30168 TACH F.R.

30I8A TACH F.L.

30188 TACH F.L.

3023A GYRO NULL

30238 GYRO NULL

3022A GYRO F.R.

30228 GYRO F.R.

3024A GYRO F.L.

30248 GYRO F.L.

3015A TRAV. BRAKE

NOT USED

NOT USED

NOT USED

Fig. 4. Results registers. The local experts execute their diagnostic logic and store the results here.

Representation of the turrettraverse testThe data flow representation makes the toplevel test strategy explicit. Figure 3 showsthe data flow net for the BFV Turret Tra-verse subsystem. The necessary power sup-plies are first tested, in parallel where possi-ble. Next the handstation signals that provideenable and velocity reference signals to theservo are examined. The servo states aredesignated full right (FR), null and full left(FL). These reflect the handstation posi-tions that result in clockwise, no rotation,and counterclockwise rotation, respectively.In each of these states, the servo torque andspeed outputs (armature current, tachome-ter, and gyro) are examined for their steady-state and transient response. The net pro-vides a simple and concise statement of thetest strategy that is easily modified whennew discoveries are made.

Figure 4 shows a portion of a logicallyencoded result register. The entire diagnos-tic situation is efficiently stored in a fewcontiguous sixteen -bit memory locations.The system allows for very fast, very effi-cient retrieval and computation at assemblylanguage speeds. Furthermore, this repres-entation is language -independent. The entirenetwork was implemented using the con-ventional diagnostic flow charts languageused by the STE product line since itsinception. Extensions to the language wereadded to enable the convenient storage andrecall of measurements and flags. There isno reason that all the modules need be

written in the same language. Any combi-nation supported by the system software ispossible.

ConclusionThe study of AI reveals new tools, newconcepts and new ways of dealing with oldproblems. We have chosen from this fieldselectively and pragmatically, adapting ideasand concepts that enhance the diagnosticmission of our test set. We have chosen adata flow network for representing diag-nostic knowledge because it fulfills thecriteria for a clear representation. The teststrategy is explicit and concise. Constraintsare made explicit by clearly showing thedependence and independence betweenlocal experts. Data is collected and storedso as to facilitate fast, efficient computation.Some powerful new extensions were addedto the diagnostic flow chart language thatmade possible the efficient collection andstorage of vehicle data. With these exten-sions, the existing test procedures were eas-ily adapted to the new representation.

References

I. Winston, P.H., Artificial Intelligence, Addision Wes-ley (1984).

2. Burr and Feigenbaum, Ed., The Handbook of Artifi-cial Intelligence, Heuris Technical Press (1982).

3. Petty and Edgar, "Location of Multiple Faults byDiagnostic Expert Systems," Proceedings of the SPIESymposium on Applications of Artificial Intelligence(May 1984).

4. Measures, Can, Shriver, "A Distributed Operating

System Kernal Based on Data Flow Principles," Pro-ceedings of the IEEE Computer Society InternationalConference (September 1982).

David Krieger is a Senior Member, Tech-nical Staff at RCA Automated SystemsDivision in Burlington, Massachusetts.Since joining RCA in 1983 he has workedon a variety of software projects. He isinterested in applying techniques fromartificial intelligence and database man-agement to problems encountered in ATEand logistics support, and is currentlypursuing a Masters Degree in ComputerEngineering at Boston University.Contact him at:Automated Systems DivisionBurlington, Mass.Tacnet: 326-3553

Krieger: Artificial intelligence concepts applied to ATE software 13

M.G. Glenny 'A.B. Wong

Automated flowchart generation

The Flowchart Generator for DFL (FCG) automaticallygenerates flowcharts by transforming DFL source code into itsgraphical representation.

Flowcharts have long been associatedwith computer programming and are con-sidered an integral part of the programmingprocess. They are the graphical represen-tation of a programming language, facili-tating comprehension of the control flow ofa program.

One language that relies heavily on thisconcept is RCA's Diagnostic flowchartLanguage (DFL). DFL, initially developedas an internal research project at RCA, wasdesigned specifically for testing vehicle sys-tems with the Simplified Test Equipmentfor the Army's Abrams MI tank and Brad-ley Fighting Vehicle System (STE-M I /FVS:see Fig. 1 and the DFL sidebar). Applica-tion engineers use flowcharts to developdiagnostic tests for isolating problems inthese vehicles. The flowcharts are thenconverted to DFL source code that is even-tually compiled into object code for thetarget test set. Figure 2 exemplifies the cor-

Abstract: Automated flowchart genera-tion is a computerized process for creatinga flowchart representation from thesource code of a program. The systemautomatically converts each logical con-struct of a particular language into itsequivalent flowchart representation. Oncethe source code is converted into a flow-chart forma4 the flowchart can be dis-played or plotted on a suitable graphicsdisplay device.

a1985 RCA Corporation.Final manuscript received February 8, 1985.Reprint RE -30-2-3

Fig. 1. Simplified test equipment for the Abrams M1 tank and the Bradley FightingVehicle System.

relation between the flowcharts and DFLsource code. Note that since the flowchartcontains both procedural and programminginformation, its purpose is twofold; it servesas a development tool for application engi-neers, and as the final documentation ofthe code.

As with any software based product, thediagnostic tests for isolating faults in a vehi-cle are continually evolving. Improvementsto current tests and additional diagnosticlogic reflecting the manufacturer's modifi-cations to the vehicles are constantly beingdeveloped. This results in frequent modifi-cations to the DFL source code and to thecorresponding flowcharts. While the codeis directly edited by the application engi-

neers, the flowcharts are controlled docu-ments and must be changed by the draftingdepartment. Therefore, engineers must notonly edit the code, but must prepare engi-neering change notices for drafting andverify each updated flowchart page forevery change made to the code. This con-straint on modifying flowcharts producestime delays that prevent the flowchartsfrom reflecting the most recent cncIP updates.In addition, as expected with two represen-tations of each diagnostic test, configurationmanagement is difficult.

Many of these problems can be alle-viated through automated flowchart genera-tion. Automated flowchart generation is acomputerized process for creating a flow -


chart representation from the source codeof a program. The system automaticallyconverts each logical construct of a particu-lar language into its equivalent flowchartrepresentation. Once the source code isconverted into a flowchart format, theflowchart can be displayed or plotted on asuitable graphics display device.

The Flowchart Generator for DFL(FCG) automatically generates flowchartsby transforming DFL source code into itsgraphical representation. Once plotted, theflowchart pages are complete and availa-ble for distribution. Since these pages areproduced directly from the DFL sourcecode, the flowchart matches the code ex-actly, an obvious advantage. Another bene-fit of the flowchart generator is the reduc-tion of configuration management pro-blems. Since only the DFL source codemust be controlled, tracking code modifi-cations is facilitated. Lastly, the flowchartgenerator increases the productivity of theapplication engineer. By reducing timespent on preparing change notificationsand verifying drafting changes, engineersmay concentrate more on the diagnosticlogic of tests.

System overviewThe DFL flowchart generator system logi-cally consists of three concentric levels, asdepicted in Fig. 3a. The innermost levelportrays the kernel of functions for manipu-lating elements of the flowchart representa-tion that are stored in the form of a directedgraph (digraph). A digraph is the naturalchoice for the system's internal representa-tion of a DFL test. Not only is graph theorywell understood and the functions easilycreated, but every DFL test may readilyform a directed graph. The concept of adirected graph is discussed below in furtherdetail. The middle level contains threemajor subsystems that convert the inputDFL source code into a directed graph,format the directed graph contents intoflowchart pages, and produce graphicaldisplay data from the formatted directedgraph. The outer level contains the systemexecutive, which controls the operation ofthe entire flowchart generator.

The flow of data between the three sub-systems (the DFL-to-digraph converter, theformatter, and the output generator) is illus-trated in Figure 3b. The DFL-to-digraphconverter accepts DFL source code asinput and creates a directed graph with anode for each shape. The nodes are anno-tated with information such as shape, typeand text. The formatter assigns page and

Comments

\..T1542.TW THIS PROGRAM CHECKS CABLE 2W105

. REVISED 800328 VEF.. SHRINK B 800617 R.W. CARON/P. SILVIA Fault message for user

DIAGNOSTIC MESSAGES

1: 'EXCITER. 3W107 2W107.2W105' ..STARTER CKTACTION MESSAGES Tells user which cable to connect1: 'ECU J1' +--LIMIT PAIRS -

Defines range to GO condition

1: 100.2000 ..ACCEPTABLE RESISTANCE

MEASUREMENT WORDSThese symbols fell the

1: STIM. KEYO.J2.PIN 40. 1993UAcompiler about hardwaremeasurements

2: MEASDIFFA. KEYO.J2.PIN 40.J2,PIN 75.7.970/4000 OHMS3: STIM. KEYO.J2.PIN 75,-4VACTION WORDS

1: NULL....v..."0"denotes GLOBAL action message

2: 051.022,07.0449,0546.1.G544,G467:1,3.2:1-0--__ Limit pair pointer3: :082

A:of:don 2G Go branch

...--NOGO branch3: 3.END

TEST HEADERS

1542,1

DIAGNOSTIC WORDS Measurement word pointer

COMMENTS ON THE FLOWCHART ARE DELIMITED BY A LEFT BRACKET. THE SYMBOL IN THE

FLOWCHART MAP TO THE FOLLOWING DFL CONSTRUCTS.

= ACTION MESSAGE

CD = MEASUREMENT WORD

0 = DIAGNOSTIC WORD

= LIMIT PAIR

0 = TEST HEADER

/-7/ r DIAGNOSTIC MESSAGE

Fig. 2a. Correlation between DFL source code and flowchart symbols.

location positions to the various flowchartshapes contained in this directed graph. Itdetermines what information fits on a flow-chart page and where this information islocated on the page. The output generatorconstructs flowchart shapes from the infor-mation found in each node of the directedgraph. A separate graphics library is used inthis latter step.

Resources

The DFL flowchart generator system isimplemented on a Digital Equipment Cor-poration (DEC) VAX 11/780. Displaydevices include a Nicolet Zeta 822 plotterand a DEC VT125 graphics terminal.

The majority of the system is written inVAX -11 Pascal. The graphics functionsare provided by Precision Visuals ExtendedDI -3000 graphics package. Miscellaneousroutines are provided by DEC VMS RunTime Library and System Services.

Data structureAll the major subsystems of the FlowchartGenerator operate on the system's internaldata structure (the directed graph). A di-rected graph consists of a set of nodes and a

set of directed arcs that connect the nodes.The nodes contain application -specific infor-mation and the directed arcs specify rela-tions (or adjacencies) between nodes. Forexample, consider the simple directed graphin Fig. 4. Pictured are a set of nodes A, B, C,D, and a set of arcs (A,B) (A,C) (B,D)(C,B) (D,A). Each ordered pair denotes adirected arc from the first element to thesecond. The directed arcs limit the move-ment between the nodes; starting at node Aand traversing to node D, the directed arcsforce node B to be visited. A path is asequence of arcs from one node to another.A cycle is a path from a node to itself. InFig. 4, a cyclic path consists of the arcs(A,B) (B,D) (D,A).

Directed graphs have many applications.For example, procedural information is

easily represented by a directed graph.Consider the simple process of frosting acake. If Fig. 4 depicts this process, theneach node describes a state in the frostingprocess (or step in the procedure), andeach arc signifies a transition betweenstates. We can define the nodes in Fig. 4as follows:

o Node A-the initial state of having anunfrosted cake and the basic ingredientsto make the frosting.

Glenny/Wong: Automated flowchart generation 15

ATTEMPT TO ENTER INTO

SUBROUTINE 1542 ASA MAIN TEST

/NO SUCH TESTPUSH STOP AND CLEAR

(SUBROUTINECALL FROM MAIN

PROGRAM

SUB 1542 CANNOT BE

CALLED BY OPERATOR USING

SET COM. IT IS EVOKED

FROM A MAIN TEST PROGRAM

MASTER POWER

BE SURE IT IS OFF

DISCONNECT

2WIO5P5 - - ECU 33

REMOVE CX304.

CX307 AND ECU J1

CONNECT C1BJ2 ICX3041 TO

2WI05P5 (CA2051

STIM.KEY O. J2

PIN 40.

1993 UA((

STIM.KEY O. J2

PIN 75-4V

IKEY 0.

DIFFA.

KEY O. J2. PIN 40.J2. PIN 75. 7.9711/

4000 OHMS

PASS

CIB

RESET

GLOBAL ACTION MESSAGE PAIR

G51 AND G22


G7 AND G449

GLOBAL ACTION MESSAGE

G546 AND LOCAL ACTION MESSAGE I


G544 AND 6467

APPLY 1 993 MA

STIMULUS TO PIN 40

L ON J2 CONNECTOR OF CIB

' APPLY -4V STIMULUS

- TO PIN 75 ON J2

CONNECTOR OF CIBLOC DIFFERENTIAL MEASUREMENTON J2 CONNECTOR PIN 40 W/RPIN 75 WITHAPPLIED STIMULI

CONVERSION CONST. 7 97V PER 4000P

FAIL 17/ FAULTY EXCITER. 3W1072W107. 2W105 154202

CLEAR APPLIED

STIMULI

END // SUBROUTINE

RETURN

DIAGNOSTIC WORD

MI

Fig. 2b Manually drawn flowchart. Comments are shown within brackets to theright of the flowchart map.

o Node B-combining the ingredients, suchas butter, sugar, and vanilla, to make thefrosting.

o Node C-obtaining chocolate to add tothe frosting mix.

o Node D-placing the frosting on thecake.

Then, if we want to make a chocolatefrosted cake, the nodes would be visited in

the order: A, C, B, D . If a plain frosted cakeis desired, the visitation order would be: A,B, D. The arc from Node D to Node A mayrepresent that, once eaten, we must frostanother cake.

A DFL diagnostic test can be consideredas a procedure, and thus be represented as adirected graph. Each node can be a state,such as displaying a message (action mes-

(-----DFL TO DIGRAPH

CONVERTER

DIRECTED

GRAPH

UTILITIES

FORMATTER

SYSTEM EXECUTIVE

OUTPUT /GENERATOR

Fig. 3a. DFL flowchart generator sys-tem configuration.

sage), making a measurement (measure-ment word), or making a decision (limitspair). This is the precise reason for choosingthe directed graph as the system's internaldata structure. Each node in the graph con-tains information such as the type of shape,the text within the shape and the position ofthe shape on the page. Arcs are delineatedby associating pointers with each node.These pointers denote the parents and thepossible children of a particular node. Thenode having no parent nodes is defined asthe root of the digraph, and is equivalent tothe beginning of a DFL test. A node havingno descendants is defined as a leaf node,and usually represents the diagnostic termi-nation (message) of a DFL test.

Directed graph utilitiesThe graph utilities perform all operationson the directed graph data structure. In-cluded are functions to create nodes, createarcs between nodes, modify the contents ofa node, retrieve nodes, delete nodes, anddelete arcs. Another utility provides themeans of traversing a directed graph via adepth -first search. A depth -first search visitsall the nodes by starting at the root of thegraph and searching "downwards" fromthe current node until a leaf node or pre-viously visited node is reached. The searchthen backtracks to a node having a branchnot previously taken and continues search-ing "downwards" until another leaf node orpreviously visited node is reached. Thisprocess continues until all nodes in thegraph are visited or until the desired node isfound. An example of a depth -first searchon a directed graph is given in Fig. 5.

The digraph utilities are easily adapted toother applications requiring a similar inter -

16 RCA Engineer 30-2 Mar. / Apr 1985

INPUT DFL

SOURCE CODEOFL TO

DIGRAPH

CONVERTER

INITIALDIRECTED GRAPH

DATA STRUCTUREr FORMATTER

DIRECTED GRAPH

ANNOTATED WITH

LOCATION INFORMATION

Fig. 3b. Data flow diagram of the flowchart generator.

nal data structure. This capability resultsfrom the technique, known as data hiding,used in developing the utilities. Data hidingis the method of creating a set of functionsthat allows manipulation of the system'sdata structure without specific knowledgeof the implementation of that data struc-ture. One advantage of this method is thesimplicity in using these functions to accessthe data structure. For example, suppose anew digraph node is needed. A new node iscreated by invoking a single function thatcreates the node and annotates it with thespecified information. Since all functionsare perceived at this higher level, the workof creating new dynamic records, adding toarray elements, and updating pointers ishidden from the program invoking thefunction. Another advantage is the ease ofmaintenance of the internal data structure.To modify the data structure, only the per-tinent directed graph utilities need bechanged; the subsystems using the graphutilities are unaffected. Therefore, data hi-ding is a powerful yet simple techniqueof layering the complexities of the system.Since each layer uses only the one beneathit to carry out some desired function, theentire system is logically designed, easilymaintained, and portable.

DFL-to-digraph converterThe DFL-to-digraph converter (DDC) trans-forms the DFL source code of a diagnostictest to a directed graph representation. Allthe various sections of the DFL source code(action messages, measurement words, lim-its pairs, etc.) are converted into a sequenceof directed graph nodes linked by appro-priately ordered arcs. The DDC translatessome of the source code into a more infor-mative representation. For example, withthe aid of external data tables, the sourcecode of a measurement word is translatedto contain information concerning the actualvehicle subsystem being tested.

Besides source code translation, the DDCpermits implementation of flowchart shapecomments. A new section added to theDFL source code allows the programmerto specify a comment for any flowchartshape. The DDC processes the new section

PLOT

OUTPUT FILE

GENERATOR

by matching the input comment with thedirected graph node representing the appro-priate flowchart shape.

The processing performed by the DDCuses LR( I) parsers and the associated se-mantic action routines (see sidebar on par-sers). These parsers generate flowchartshapes in the appropriate sequence whiletranslating portions of the DFL sourcecode into text for the flowchart shapes. Aparser generator program automaticallycreates the parse tables from DFL codesyntax tables specified in Backus-NaurForm (BNF). These parse tables are thenused by the LR parsers to process theDFL source code. This method of pro-cessing greatly reduces program mainte-nance, since any change in the DFL syn-tax simply requires the parser generatorprogram to automatically produce newparse tables.

FormatterThe formatter constructs a flowchart byefficiently allocating positions on pages forshapes, represented by the digraph nodes,according to established DFL flowchartingstandards. The formatter traverses the di-rected graph using a modified depth -firstsearch. It first processes the True Go Path(TGP) of the DFL test, formatting these

A DEPTH -FIRST SEARCH STARTING ATROOT NODE A YIELDS THE FOLLOWING

VISITATION ORDER:

A. B. E. F. C. G. H. 0.1

Fig. 5. Depth -first search example.

Fig. 4. Example of a directed graph.

shapes, lines and text onto the first pages.The formatter then deals with each faultpath branching from the True Go Path. Asit traverses the digraph, the formatter deter-mines which shapes fit onto the currentpage by consulting a bit map image of theoccupied areas. If the shape fits in the cur-rent position, the coordinates and pagenumber are assigned to the node, the posi-tion on the page is updated, and processingof the graph continues. If the shape collideswith another, the formatter decides whetherto move down the current column, tryanother column, or start another page. Theformatter not only traverses the digraph,but adds to it under certain circumstances.For example, if a branch to another pageoccurs, an off -page connector and associatedlines must be added to the flowchart and

- DOWNWARDS SEARCHBACKTRACK


ParsersAssociated with every language is a set of grammaror syntax rules for all possible sentences in that lan-guage. A standard method for specifying the gram-mar rules of formal programming languages is inBackus-Naur Form (BNF). Each rule is composed oftwo symbol types; terminals and nonterminals. Ter-minals are the basic symbols that form "sentences"of a language, and are analogous to dictionarywords such as dog, cat, boy, and run. Nonterminalsare special symbols that represent sets of terminalsymbols. For example, nonterminals might be asentence, verb, or arithmetic expression. In BNF,nonterminals are denoted by enclosing them withinthe symbols "<" and ">". All other symbols in agrammar rule (or grammar production) are assumedto be terminals.

Using a finite set of terminals and nonterminals,the syntax of most programming languages can bespecified by a context -free grammar. A grammar iscalled context -free if every construct of the lan-guage's grammar can be expressed in Backus-NaurForm. A context -free grammar for a langauge is val-uable because it provides a precise, easy to under-stand syntax specification for the language. Anexample of a grammar in BNF is the following. Con-sider the sentence "The big dog ran after the ball."The following are grammar productions to specifythis sentence.

1. <sentence> ::= <subject> <predicate>2. <subject> ::= <article> <adjective> <noun>3. <article> ::= the4. <adjective> ::= big5. <noun> ::= dog6. <predicate> ::= <verb> <object>7. <verb> ::= ran8. <object> ::= <preposition> <article> <noun>9. <preposition> ::= after

10. <noun> ::= ball

Note that the nonterminal "<noun>" is defined aseither "ball" or "dog". Another possible sentence thatcan be formed with these productions is "The bigball ran after the dog." Both sentences are valid interms of syntax, but vary in meaning. Thus, we cansee that although a grammar can ensure syntacti-cally correct sentences, it does nothing to ensurethat each sentence has a valid meaning.

Once a context -free grammar for a language hasbeen defined, an efficient parser can be constructedfor that particular grammar. A parser is a softwaretool used to recognize grammar rules (or produc-tions) within the input to the parser. This allows theparser to ensure that the input follows the grammarrules of the parser's target language. For example,if we have the sentence "The big dog ran after theball," a parser could be used to check the syntax ofthis sentence; it would ensure that the adjective"big" modifies some noun, in this case "dog." One ofthe most common uses for a parser is in a compilerfor programming languages such as FORTRAN orPascal. The parser ensures that the user's programfollows the syntax rules of the language and at thesame time generates the machine code for the pro-gram. When a portion of the input being checkedmatches a grammar rule, the parser evokes thefunction associated with that rule to generatemachine code representing the input. These func-tions are called semantic action routines becausethey give meaning to a particular grammar rule. Forexample, once the Pascal statement "A : = 5"matches one of the grammar rules for the Pascallanguage, the parser would use a function to gener-ate the machine code equivalent of this statement.

Many types of parsers can be constructed. Thetype of parser is based upon the grammar specifica-tion of the language for which the parser is targeted.One of the more common parsers is a LR(1) (Left -to -right scan of the input, rightmost derivation) type. Itoperates upon a class of grammars known as LRtype grammars. It is beyond the scope of this paperto go into the details of LR grammars and LR(k) typeparsers. For more information on LR grammars,consult The Theory of Parsing, Translation, andCompiling by Aho and Ullman. Since most lan-guages can be easily specified by an LR grammar, itmakes the choice of a LR parser the most logical toimplement a syntax checking program for a particu-lar language. All parsers achieve the same goal ofchecking the input for syntactical correctness; theyvary only in the means and efficiency of checkingthe input.

Principles of Compiler Design by Aho and Ullmanand Compiler Design Theory by Lewis, Rosenkrantz,and Stearns are excellent texts on the theory behindparsers and compilers.

hence the digraph. Note that this shape doesnot correspond to any DFL code but is anartifact of the formatting step.

The structure of a flowchart page iscrucial to the operation of the formatter.A flowchart page is mapped into a Carte-sian coordinate system, the lower leftcorner defined as the origin (see Fig. 6).This allows for precise specification of the

current position and the location of shapes,lines, and text. This coordinate system isthen partitioned into columns. There arefour main flowchart columns that maycontain shapes, lines and comment text.To the side of each main column is a con-tinuation column, reserved for connectinglines between shapes in different columns.This representation allows for production

of a flowchart page that conforms to esta-blished DFL flowcharting practices.

The formatter constructs a data struc-ture known as the page -object list. Thislist is a collection of pointers ordered bypage number. Each pointer begins anotherlist containing graph node pointers. Thedigraph nodes pointed to on a list arethose nodes formatted on that particular


page. The purpose of the list is to increasethe efficiency of the output device. Sincethe formatter uses a modified depth -firstsearch algorithm to traverse the graph, alldigraph nodes formatted onto a certainpage are impossible to locate without du-plicating the decisions made by the for-matter. The page -object list alleviates thisproblem by allowing the output generatorto easily access the digraph nodes format-ted in a column, from the top to the bot-tom of each column, for each flowchartpage.

Output generatorThe output generator produces the graph-ics display data for the lines and text thatcompose the information contained on aflowchart page. It scans the page -objectlist to access the digraph nodes represent-ing the flowchart shapes. For each shapeencountered, the output generator evokesfunctions in the graphics library to creategraphics display data for the lines andtext. The graphics display data may begenerated in two formats: a device -spe-cific file, and a device -independent meta -

C TEST )1542

NO SUCH TESTPUSH STOP AND CLEAR/

MAXIMUM YCOORDINATE

ORIGIN

FLOWCHART COLUMN

CONTINUATION COLUMN

Fig. 6. Flowchart page structure. The coordinate system is partitioned into fourmain columns and five continuation columns.

file. The device -specific file stores a flow-chart page in a standard C -size (17 by 22inch) format. The metafile allows the storedgraphical image to be viewed on displaydevices through a metafile translator for a

/ MASTER POWERBE SURE IT IS OFF.

/ TGLOBAL ACTION MESSAGEPAIR G51 AND G22

i

/DISCONNECT GLOBAL ACTION MESSAGE2W105 <--> ECU J3

I 4-PAIR G7 AND G449

I GLOBAL ACTIN MESSAGE/ REMOVE CX304 AND-- G546 AND LOCAL ACTIONADAPTER AT ECU J1

MESSAGE 1

ZTO 2W105P5 (CA608)CONNECT C1 BJ2 (CX304) fGLOBAL ACTION MESSAGE

PAIR G544 AND G467

INFORMCABLE

CONNECTCX205

I( STIMTNB -TJ2

57

401933UA/

fu---.

- SPECIAL FLOWCHART- GENERATOR MEASUREMENT

WORD

APPLY 1.993 MA STIMULUSTO PIN 40 ON J2 CONNECTOROF CIB

Fig. 7. An example of a computer -generated flowchart.

N -r-STIM

75-4V

TNB-TJ299

I

AD-MEASTNB-TJ2

57. 99

40. 75

PASS

3

( CIE.

RESET

MAXIMUM XCOORDINATE

specific device, such as a DEC VT125graphics terminal. At the user's option,either file format can be specified. A sim-ple example of a computer generated flow-chart plot is shown in Fig. 7.

APPLY -4V STULUS TO PIN75 ON J2 CONNECTOR OF CIB

DC DIFFERENTIALMEASUREMENT ON J2CONNECTOR PIN 40 WITHRESPECT TO PIN 75 WITHAPPLIED STIMULICONVERSION CONST. = 7.97VPER 4000 OHMS

FAIL

/ NO FAULTS FOUND

/FAULTYEXCITER .3W107

2W107 2W105 154202

DIAGNOSTIC MESSAGE M1

CLEAR APPLIED STIMULI-

//- -ISUBROUTINE RETURN

Glenny/Wongs Automated flowchart generation 19

DFL

The Army's M1 tank containsnumerous electrical, mechanicaland hydraulic subsystems thatare tested with the STE-M1 /FVStest set. If assembly languagecode was used to program thetest set for this vehicle, nearlyone megabyte of memory wouldbe required. The high cost ofbuilding a test set containing thismuch EPROM (erasable pro-grammable read only memory),and the problems with managingthe assembly code for all tests,spurred an internal researcheffort at RCA to develop acalled Diagnostic Flowchart Lan-guage (DFL). DFL's object code isinterpreted in the target test -set

system. Its use in applicationtests has reduced the memoryrequirements of application codeby a factor of five over the equi-valent assembly language imple-mentation of the tests. Moreover,with DFL, application engineersno longer need detailed know-ledge of the measurement systemhardware or the operating systemof the test set. This decreases thetime an applications engineerspends programming a test,thereby increasing the time avail-able for developing the diagnos-tics of the test.

Since each DFL test representsa logical flow of control for testinga subsystem of the vehicle, appli-cation tests are defined using a

standard flowcharting method.Most diagnostic tests contain aTrue Go Path. Completing theTrue Go Path signifies that thesubsystem under test is opera-tional. If a problem is detectedwhile traversing the True Go Path,a branch into a fault path occurs.In the fault path, the problem isisolated to a line replaceable unitof the vehicle or a connectingcable within the subsystem. Oncethe flowchart for a diagnostic testis developed, it is implemented inDFL. Since the constructs of DFLclosely follow the structure of theflowchart, the task of coding thetest is simple. Figure 2 highlightsthe correlation of a diagnosticflowchart and the DFL code.

Arthur Wong is a Member of the Techni-cal Staff of Vehicle Test Systems Engi-neering at RCA Automated Systems. Hereceived a Bachelor of Science in Compu-ter and Systems Engineering in 1982 anda Master of Engineering in Computer andSystems Engineering in 1983 from Rens-selaer Polytechnic Institute. Since joiningRCA in 1983, he has worked on developingsoftware utilities to aid the diagnostic testprogramming effort.

Contact him at:Automated Systems DivisionBurlington, Mass.Tacnet: 326-5299

Mark G. Glenny, since joining VehicleTest Systems Engineering at RCA Auto-mated Systems in 1982, has developeddiagnostic test programs for Army vehi-cles. As a Member of the Technical Staff,he is now involved in the FCG and SGCprojects. He has a Bachelor of Sciencedegree in computer engineering fromBoston Unversity and looks forward toreceiving his Masters of Science in Com-puter Engineering from Boston Universityin 1986.Contact him at:Automated Systems DivisionBurlington, Mass.Tacnet: 326-5264

Plotmaker

The plotmaker is a separate utility thatallows the user to generate A -size (8 1/2 by11 inch) plots on the Nicolet Zeta plotter.The flexibility of the metafile translator sys-tem simplifies this process. Once the flow-chart generator creates a metafile for a DFLtest, the plotmaker uses the metafile transla-tor to produce a graphics image that isscaled and translated to the desired size.

Future trends

An upcoming extension to the flowchartgenerator is the STE Graphic CompilerSystem (SGC). This system will allow theuser to graphically edit a diagnostic test.The flowchart of the test will be displayedon a graphics terminal and may be editedby manipulating flowchart shapes, linesand text. Once the flowchart has beenedited, DFL source code will be generateddirectly from the new flowchart. The graphutilities created for the DFL flowchartgenerator form the foundation of the STEGraphic Compiler. The output generatorportion of the flowchart generator will beused by the SGC to produce flowchartplots. Both the FCG and SGC systems areillustrated in Fig. 8.

Summary

Automated flowchart generation of DFLprovides many advantages, including en-hanced configuration management, in-creased productivity, and improved code


documentation. The flowchart generatorfor DFL signifies the beginning of theautomation of the rote tasks of applica-tion engineers, freeing more time for diag-nostic development of tests. Eventually, acomputer aided software engineering sys-tem will provide the complete environ-ment for application programming.

ReferencesI. Aho, A. and Ullman, J., Principles of Compiler

Design, Addison-Wesley, Reading, Mass. (1977).2. Aho, A. and Ullman, J., The Theory of Parsing,

Translation and Compiling, Prentice -Hall, Engle-wood Cliffs, N.J. (1973).

3. Lewis, P., Rosenkrantz, D., Stearns, R., CompilerDesing Theory, Addison-Wesley, Reading, Mass.(1976).

4. Munk, G. and Heffernan, J., "Using Software Toolsto Enhance Engineering Productivity", RCA Engi-neer, Vol. 28, No. I, (January/February 1983).

EDITING

COMMANDS-'

POSSIBLEPREVIOUSLY

CREATED /FLOWCHART

FILE

GRAPHICS

TERMINAL

If

GRAPHICS

EDITOR

DFL SOURCE CODE

UDEL

FLOWCHART GENERATOR

JDIRECTED GRAPH

KERNELUTILITIES

OUTPUT

GENERATOR

OFL

CODE

GENERATOR

IFLOWCHART PLOTS AND EDITOR FILE

DFL

---> SOURCECODE

KEY TO DATA FLOW

-' SGC ONLY

FCG ONLY

FCG/SCG BOTH

Fig. 8. STE graphic compiler/flowchart generator system diagram.

DO WE HAVE YOUR CORRECT ADDRESS?

If not, please return the mailing label from the back cover and write your new address below.Mail to: Robin Bernheim, RCA Engineer, 13 Roszel Rd., P.O. Box 432, Princeton, N.J. 08540-0432

Name Code

Street or Bldg.

City, State and ZIP Code, or Plant

*Please indicate the code letter(s) that appear next to your name on the mailing label.


T.D. Fuhr

A laser measurement system for high -accuracy,automated near -field probe tracking

Unprecedented levels of accuracy and calibration speed for anear -field antenna scanner are achieved by a unique, auto-mated, laser -based interferometric measurement system.

Missile and Surface Radar's new, sec-ond -generation near -field antenna test facil-ity employs a 12 -degree -of -freedom lasermeasurement system to produce the state ofthe art in accuracy and automation in thetesting and alignment of phased array radarantennas. The results obtained with thismeasurement system, which contains morethan 70 optical and electro-optical ele-ments, represent an unprecedented level ofaccuracy for a near -field test facility. Thelasers measure all scanner motions andprovide information to calculate the posi-tion of an rf probe over a scan plane of 20 X26 feet to a measured accuracy of 0.0034inch RMS radial error over the entire scan-ning area. The mechanical calibration pro-vided by the scanner laser measurementsystem is a highly automated, computer -controlled process requiring one operatorand 15 to 45 minutes, depending on the

Abstract: A 12 -axis laser measurementsystem, the first of its kind provides RCAMoorestown's new near -field antenna testfacility with the state of the art in me-chanical measurement accuracy neededfor testing the next generation of lowersidelobe phased -array radars.

01985 RCA Corporation.Final manuscript received December 27, 1984Reprint RE -30-2-4

selected scan scenario. In contrast, a man-ual scanner calibration would require ap-proximately one week of effort for threetrained personnel. The automation of thelaser measurement system makes it possibleto calibrate the scanner immediately priorto any antenna scan, thereby greatly reduc-ing the risk of physical change to thescanner between the time of calibration andthe time of the scan.

This paper describes the rationale forand the implementation of this laser cali-bration system, the operational proof ofthe system, and its measured accuracyperformance. The positional accuracy ofthe scanner obtained through the laserinterferometers and the rapid, automatedscanner calibration is making possible near -field testing of the new generation of lowsidelobe antennas.

To achieve the lower sidelobes fromthese new antennas, the several thousandactive phase shifters in the array must beresolved and adjusted to an rf phase errorof less than one degree RMS. The posi-tional accuracy requirements of the scannerare dictated by the needs of these newarrays.

In near -field testing, the phased -arrayantenna is placed in an environmentallycontrolled indoor facility. The antenna re-ceives rf signals from a probe locatedapproximately 10 inches from the arrayface. Ideally, the probe moves parallel to

the array face, both vertically and horiz-ontally, along an imaginary two-dimen-sional planar grid, and if data is obtainedat uniformly spaced intersection points.The phase and amplitude of the signalreceived by the antenna from the rf probeare digitized and transmitted to computersthat collect and reduce the data.

Ideally, the rf probe must be preciselypositioned at each intersection point alongthe grid. If the signal transmitted from the rfprobe to the array is not measured at theexact intersection points, errors result in thenear -field measurements that could pos-sibly be a source of false sidelobe indications.

Scanner and laser architectureSince the rf probe must scan horizontallyalong the X axis and vertically along the Yaxis (Figs. 1 and 2), the scanner is config-ured to provide these motions. The scannerconsists of a triangular cross-section steeltower, 24 feet tall, riding horizontally onThompson recirculating linear ball bear-ings and Thompson hardened and ground2 -inch diameter steel shafts. The primaryhorizontal (X) rail is 35 feet long.

A small carriage containing the if probetravels vertically on 3/4 -inch diameterThompson shafts over the full height of thetower, passing in front of the antenna face.The primary horizontal (X) rail is alignedstraight to within 0.003 inch in the vertical

22 RCA Engineer 30-2 Mar. / Apr 1985

Fig.1. The scanner positions the rfprobe, which extends from the probecarriage, in front of the face of thephased -array antenna during a near -field test scan.

Eg. 3. The 12 -degree -of -freedom lasermeasurement system, run from the fivelaser transducers on the fixed opticalbench, measures all motions of thescanner. Scanner optics can also beseen on the tower shelf and at the topof the probe carriage. The carriagestraightness reflectors, including thetwo `fixed reflectors used for roll anglesensing, are located in the tower shelfsubplate housing.

plane and 0.004 inch in the transverseplane. The primary vertical ( Y) rail is

straightened to 0.004 inch in both orthogo-nal planes. The secondary rails, which areessentially followers, are made parallel to

SECONDARY Y RAIL

CARRIAGE OPTICS SUPPORT

ROD END BEARING

PRIMARY X RAIL

LINEARBEARING

78.62

ROD ENDBEARING

PRIMARYY RAIL

RF PROBECARRIAGE

SECONDARY X RAIL

25.2

8.65

RF PROBE TIP

TO244.1

z

TOWER MOUNTEDOPTICAL BENCH

FIXED OPTICALBENCH

Fig. 2. Scanner arrangements of near -field test facility (dimensions are given ininches).

their associated primary rails to within0.004 inch in the vertical plane and 0.032inch in the transverse plane. All straightnessmeasurements are made with Hewlett-Packard long-range straightness interfero-meters and an HP 5526A laser transducerand display.

The mechanical accuracy of the scannerin positioning the probe tip over the scanplane is derived from the straightness andparallelism of the rails. However, the ac-curacy obtained from this stringent me-chanical alignment is not sufficient to meetthe formidable 0.004 -inch RMS errorprobe positioning specification in each ofthe three axes (0.007 -inch RMS radialerror). To obtain this required accuracy,the rf phase data is corrected post -scan,based on the distance between the actuallocation of the probe as measured by thelasers (Fig. 3) and the ideal probe posi-

tion on the imaginary uniform planar grid.Because the probe is the if radiation

source of the near -field test system, a uni-que measurement scheme was needed totrack its position. Optical elements couldnot be placed at the probe tip since theywould disturb the if field. This constrainteliminated any approach of directly track-ing the probe tip position. In the final sys-tem, the probe tip position is calculatedfrom data obtained by measuring all mo-tions of the tower and carriage: 12 de-grees of freedom plus an initial orthogo-nality error.

It is known from Newtonian mechan-ics that a rigid body contains 6 degrees offreedom in three-dimsenional space, andthat all motions are a combination oftranslation along and rotation about eachaxis. The scanner can be considered a sys-tem of two independent rigid bodies, there-

Fuhr A laser measurement system 23

/ 4 IL'

t:40

*

10101e 5 10110

50 4) %.

.1101611

LEGENDu LR - LINEAR INTERFEROMETER REFLECTORAl AR ,ANGULAR NTERFEROMETER REFLECTORSI SR,STRAIGHTNESS NTERFEROMETER REFLECT°,USA, VERTICAL STRAIGHTNESS ADAPTORB,BEAM BENDERS50% BEAM SPLITTERSO, OPTICAL SQUAREHD, LASER SOURCERECEIVERS 1121 LABELLED WITH PARAMETER MEASURE,IFSHUTTER BLADES B PLACES

Fig. 4. Arrangement of the laser optics for the near -field scanner.

fore possessing 12 degrees of freedom.The laser system is configured to measurethe 12 degrees of freedom present in thesystem. Using this information, it is possi-ble to define the position of the probe tipin three-dimensional space.

Both tower and carriage motions arefully measured by the same basic laserinterferometer architecture (see Fig. 4).One linear interferometer measures themotion of the body along its direction oftravel. Two long-range straightness inter-ferometers measure small displacementsorthogonal to the direction of travel. Athird straightness interferometer is presentto allow the derivation of the roll angle,which is the rotation about the axis oftravel or, in the case of laser interferome-try, about the beam axis. Two angle inter-

ferometers measure the remaining twoangular displacements of the body. Alllaser optical components in the systemare manufactured by Hewlett-Packard andare a custom combination of elementsfrom their 5501 and 5526 series of optics.A more detailed explanation of the laseroptics and theory can be found in refer-ence 1.

In the automated calibration of the scan-ner, the tower and carriage displacementsare measured in separate runs. From thisinformation, the probe displacement errorsfrom the ideal rf measurement grid aredetermined. The calibration scenario usesthe same dynamic conditions of scannermotion as are encountered in actual anten-na scanning. The tower is stepped alongthe horizontal X rails at equal intervals

under computer -commanded servo control,holding a steady position while data fromthe six tower measurement interferome-ters is sampled and averaged to smoothany random noise caused by local ther-mal effects in the anechoic chamber. Thecarriage displacement data is taken "onthe fly" as the carriage moves vertically atits scan speed. The data sampling processis timed by the computer to occur at theproper Y location. A Perkin-Elmer 3250mainframe computer is used as the systemcontroller. In all scanner motions, the Xand Y linear interferometers provide thedata for positional feedback in the servocontrol. The horizontal hold/vertical scandata collection scheme of the laser cali-bration process is consistent with the actualantenna scan patterns.


H ROLL02-D, 1D

LZ

Ki X

TRUE ROLL MEASURED ANGLE PARALLELISM ERROR

Di, D2 = STRAIGHTNESS READINGSFROM INTERFEROMETERS

= ANGLE COUPLING CORRECTIONTERM

L2 = REFLECTOR BASELINE

K, = PARALLELISM CONSTANT

X = LINEAR DISTANCE TRAVELEDBY INTERFEROMETERS

Fig. 5. Laser roll angle sensing with straightedge misalignment.

WOLLASTONPRISM

(STRAIGHTNESS INTERFOROMETERIfi

TWO -FREQUENCY LASERBEAM

2

f

STRAIGHTNESS REFERENCEANGULAR BISECTOR OFPLANE MIRROR ASSEMBLY

(

PLANE MIRRORREFLECTOR

Fig. 6. Straightness interferometer.2 A Wollaston prism splits a laser beam into itstwo frequencies, fl and f2 . An assembly containing two slightly angled planemirrors then reflects the beams back through the prism. The phases of the twobeams interfere with each other, thus providing data on optical path changes.

Roll angle sensingAll scanner parameters are measured di-rectly by the interferometers except forthe two roll angles. At present, no inter-ferometer exists that is capable of directlysensing a roll angle. To resolve this prob-lem, the system uses data from two iden-tical, displaced straightness systems (seeFig. 4) to mathematically derive the towerand carriage roll angles. The basic rollangle measurement configuration utilizingthe two straightness interferometers is

shown in Fig. 5. The reference straight-edge, which defines the line of zero dis-placement, is optically determined by theperpendicular bisector of the two slightlyangled mirrors constituting the HP straight-

ness reflector. The angle of these mirrorsis matched to the divergence angle of theWollaston prism that constitutes the HPstraightness interferometer (Fig. 6).

It is possible, and highly probable, thatin the alignment of a straightness meas-urement system there will be a smalldegree of angular misalignment (on theorder of microradians) between the opti-cal straightedge and the interferometer lineof travel. This phenomenon causes a slopein the straightness data directly propor-tional to the degree of angular misalign-ment. Since two straightness systems areused to indirectly measure the roll angle,there will be two different slopes corrupt-ing the roll angle data. This non -paralle-

lism of the two reference straightedgescauses an artificial roll angle to be includedin the data, proportional to the angularmisalignment of the straightedges and thelinear displacement of the interferometersalong the line of travel. It is necessary toassess the parallelism in the measurementplane of these two straightedges in orderto obtain a usable, common reference forthe roll angle measurements.

A precision gravity level is used in con-junction with the two roll -angle straight-ness systems in order to determine theparallelism of the straightedges. This levelis used to sense the true tower roll angle.The misalignment of the straightedges isdetermined mathematically by using thedata from the level measurement, fromthe two straightness interferometers, andfrom a linear interferometer.

The misalignment is expressed in theform of a constant K in units of inversedistance. This constant is then multipliedby the linear distance traveled to obtainthe artificial roll angle in radians. Thisquantity is then subtracted from the rollangle calculated from the straightness inter-ferometer data to yield a value for theactual roll angle. A Federal Products elec-tronic differential level on the one arcse-cond resolution scale was used in thisapplication in the system, and an HP85minicomputer was employed for acquisi-tion of laser data.

The tower roll angle is derived from data

Fuhr: A laser measurement system 25

obtained by the A Yt and A Ye straight-ness interferometers. The parallelism of theassociated reflector straightedges is deter-mined with the reflectors in their final posi-tions on the fixed bench. The parallelism ofthe carriage roll angle reflectors, however,must be determined in a special setupbefore they can be placed into the system.

These two straightness reflectors are at-tached to a rigid housing that allows forindependent reflector motion to facilitatethe initial alignment. In this initial align-ment, the reflector straightedges are ori-ented horizontally in a temporary setupon the optical bench. This allows the useof the gravity level on the tower to mea-sure a true roll angle, and the measure-ment of carriage reflector parallelism isthen made in the same manner as thetower reflectors.

After this parallelism has been deter-mined, no further independent adjustmentsto the reflectors are allowed, ensuring thatthe relative orientation of the reflectors isnot disturbed. When the carriage reflectorhousing is placed in its final position on asubplate under the optical shelf, the onlyadjustments to the pre -aligned reflectororientation are made by common motionof the entire housing. This restriction pre-sents a uniquely difficult alignment task:the alignment of a vertical straightnesssystem without adjustment to the straight-ness reflector; this alignment was achievedin the assembly of the scanner.

Remote probe trackingThree benchmarks are established on thescanner to provide physical and mathe-matical reference points. The center of theX axis linear retroreflector is designated asthe tower benchmark. Similarly, the cen-ter of the Y axis linear retroreflector be-comes the carriage benchmark. The thirdbenchmark is established at the center ofthe probe tip aperture, whose position inthree-dimensional space is to be definedusing displacements of the other two bench-marks as measured by the lasers.

Since lasers are an incremental mea-surement tool, a reference zero must be

established. All lasers are set to zero withthe tower and carriage in their mechani-cal stow position, and all laser measure-ments are made with respect to this stowposition.

Gross displacements of the tower andcarriage measured by the linear optics nowbecome, by definition, linear displacementsof the tower and carriage benchmarks.With the scanner in stow, precision lengthvectors between the three benchmarks aredetermined to assess the effects on probetip motion of tower and carriage rotationsobtained from the angle interferometersand the calculated roll angle. Small ortho-gonal displacements, measured by straight-ness interferometers, are treated as mea-surements made remote from a benchmarkand are compensated for angle couplingeffects, necessitating measurement of an-other series of vector lengths from thestraightness interferometers to the appro-priate benchmark. Any orthogonality errorbetween the X and Y primary rails ismeasured using an optical square and istreated as an X axis displacement of theprobe dependent upon the Y position ofthe carriage.

The position of the probe tip in three-dimensional space can be defined by amatrix equation (Fig. 7) that combines theprobe displacement effects. Because of thepost -scan data correction scheme, the accu-racy of this probe position equation becomesthe accuracy of the scanner.

Scanner verificationThe proof of the probe position equationand scanner accuracy derives from thetreatment of the tower and carriage asrigid bodies undergoing independent mo-tions that contribute to the probe tip dis-placement. Probe motion is induced bythese independent tower and carriage mo-tions, all of which are measured by theinternal scanner lasers. Since tower andcarriage motions are independent, theireffects on probe motion can be measuredindependently.

Both tower and carriage can cause theprobe tip to move in three-dimensional

space, resulting in six possible contribu-tions to probe tip displacement. Thesecontributions are designated XXv, Y, and Z where the variable givesthe direction of probe motion and thesubscript denotes tower (x) or carriage(y) contribution. Once the differences be-tween measured and calculated values ofthese displacements are determined, a Aprefix is added to each of these terms todenote error in probe tip position calcu-lated from that measured: AX A Y AZ,AX AY, and AZ These are the final sixscanner verification paths listed in Table I.

All measurements of probe tip displace-ment due to tower motions are performedwith the carriage in stow position ( Y=0 )and all carriage dependent probe motionsare measured with the tower in stow posi-tion (X = 0). Two further verificationpaths, AX,' and AZ,' have been includedas additional checks on the algorithm withthe carriage displace from the zero posi-tion ( Y > 0) to assess the effects of thisparameter on the probe position equation.In all cases, all lasers are reset to zerowith the tower and carriage stowed.

During the verification a dummy probewas installed on the carriage and laser opti-cal elements were mounted at positions ap-proximating the final rf probe tip location.These elements were used in conjunctionwith an external Hewlett-Packard 5526Alaser and appropriate straightness and lin-ear components to determine displacementsat the dummy probe tip. Displacementinformation from the scanner lasers wasacquired, and the scanner was positionedunder computer control.

The position of the dummy probe tipalong the appropriate axis was calculatedfrom this internal scanner laser data at spec-ified grid points over the scan plane. Thisposition was compared with measuredvalues of probe tip displacement obtainedfrom the external 5526A system and enteredmanually through a terminal keyboard. Agranularity of 0.9 inch was used over the 26feet of X travel, yielding 350 data points;the Y axis grid, established at 0.99 inch overthe full 20 feet, yielded 241 data points. Thedeviations between measured and calcu-

[Probe Linear [Orthogonality] [Small Orthogonal DisplacementsPosition [Displacements] -7 Error from Straightness Interferometers

+[Tower VectoI Tower + [Carriage Vectol[Carriage

Lengths Rotations Lengths Rotations]

Fig. 7. Matrix equation defining probe tip displacement in three-dimensional space


Table I. Results of laser algorithm verificationProbe Tip Displacement Verification Errors

(Inches RMS)

Error Source X Axis Y Axis Z Axis

Tower MotionCarriage Stowed (A) 0.0003 0.0010 0.0006Carriage Displaced 0.0005 N/A 0.0016

Carriage MotionTower Stowed (B) 0.0029 0.0001 0.0005

Orthogonality (C) 0.0011 N/A N/A(Max.)

Total(A2 + B2 + C2) 1/2 0.0031 0.0010 0.0007

Specified 0.0040 0.0040 0.0040

Total Probe Position, Radial Error

System Requirement/Allocation: 0.0040N/3 = 0.0070"

Current Performance: [0.00312 + 0.00102 + 0.00072f = 0.0034"

lated displacement were computed at eachof these locations and analyzed for RMSerror content. A Perkin-Elmer 3250 com-puter was used as the system controller forthe verification.

ConclusionsThe measured accuracies of the probe tiptracking algorithm show five of six verifica-tion paths to have errors in calculating theprobe tip displacement in the range of0.0001 inch to 0.001 inch RMS. Two ofthree axes, Y and Z, show a total positionerror also in that range ( Y axis error =0.0010 inch RMS; Z axis error = 0.0007inch RMS). The X axis positional mea-surement accuracy, which includes an esti-mate of orthogonality measurement error,shows a 0.0031 -inch RMS error.

The measured 0.0034 -inch RMS radialerror is considered to be a conservativeindication of the scanner performance forseveral reasons. This data includes residualerrors from the external laser system, andthe contribution of each scanner rotation isincluded twice in the verification. Also, anestimate of the maximum error due touncertainty in the orthogonality measure-ment is included in the error summaryrather than an RMS value.

The major contributor to the total scan-ner error resides in the AX path. While theother five verification paths show RMS

errors ranging from 0.0001 inch to 0.001inch, the residual error of the AX, pathalone was measured to be 0.0029 inchRMS, approximately three times greaterthan the next largest single error. The prin-cipal cause of this error is in the probedisplacement induced by the carriage rollangle.

The inaccuracies in the measurement ofthis parameter are responsible for the rela-tively large AX, error. With no vertical rollangle sensing, the AX, path showed a0.0038 inch RMS probe -position error.Therefore, while inclusion of the carriageroll angle correction into the probe positionequation has provided an improvementover the uncorrected AX, error, the correc-tion effect is not as accurate as that pro-vided by the tower roll angle measurements.

The difference in the accuracies betweenthe calculation of the tower and carriageroll angles (the tower roll angle calculationis the main contributor to A Yx residual errorof 0.0010 inch RMS) lies in the length ofthe baseline between the two reflectors. Thebaseline of the tower reflector measuresapproximately 66 inches, about 3:1 greaterthan the carriage reflector baseline. Thisbaseline is the only significant difference inthe layout and measurement method ofthese two systems.

The measured 0.0034 inch RMS radialerror in probe position calculation pro-vided by the laser calibration system was

Tim Fuhr has worked on near -fieldantenna test facilities for RCA since hisgraduation from Drexel University with aBSME in 1981. He is a Member of theEngineering Staff in RCA Moorestown'sStructures and Mechanisms DesignGroup. For his development and verifica-tion of the twelve axis laser measurementsystem, he received a Chief Engineer'sTechnical Excellence Award for theFourth Quarter of 1983.Contact him at:Missile and Surface RadarMoorestown, N.J.Tacnet: 224-2622

2:1 under the specified error allocation of0.007 inch RMS, and represents an un-precedented level of accuracy for a near -field scanner. In addition to its speed andaccuracy, this automated laser measure-ment system has also shown a high degreeof reliability in its first year of usage.

References

1. W.A. Harmening, "A Laser -Based, Near -Field, ProbePosition Measurement System," Microwave Journal,Vol. 26, No. 10 (October 1983), pp. 91-102.

2. R. Balwin, et al., "An Interferometer That MeasuresStraightness of Travel," HP Journal, Vol. 25, No. 5(Jan. 1974), pp. 10-20.

Fuhr: A laser measurement system 27

The RCA Lancaster Library serves two divisionsThe Lancaster Library serves the technicalneeds of the New Products Division and theVideo Component and Display Division, bothheadquartered at the Lancaster plant. Thelibrary contains approximately 7000 booksand subscribes to 120 technical journals.Although the library is small in size, it has theability to retrieve current technical informa-tion through a network of libraries. To illus-trate, one can consider the Lancaster Libraryas a small circle surrounded by ever largercircles, making it possible to locate nearlyany book or journal article.

In addition to books and journal articles, theLancaster Library provides the following:

Computer search services able to accesshundreds of commercial and technicaldatabases via the DIALOG and BRS searchsystems.

On-line access to the private RCA data-base containing the RCA technicalabstracts data from 1968 to the present.

Weekly listings of titles of relevant journalarticles.

Monthly listings of new books, patents andRCA technical reports.

Distribution and storage of engineeringnotebooks

A collection of applicable patents selectedby the resident patent attorney.

Service data on RCA television receiversdating back to the 1940s.

Service data on RCA videocassetterecorders and VideoDisc players.

Videocassette players (1/2 -in. and 3/4 -in.) andmonitors for viewing tapes.

VCDD and SSD procedures manuals.

Selected ASTM standards.

All RCA technical reports and many engi-neering memos for the past ten years.

For more information, contact Mary Kathryn Noll,Administrator of Library Services, at: (717) 295-3100 or Tacnet: 227-3100


W. A. B6senberg N. Goldsmith

Parametric testing of integratedcircuits an overview

Parametric testing is an essential element in adjusting the entiremanufacturing process for maximum yield.

Parametric testing, as it applies to inte-grated circuits, requires sophisticated mea-surement equipment controlled by elabo-rate computer systems executing complextest programs. Most testing produces cop-ious quantities of data that are reduced byother computers to make it comprehensi-ble. In this introductory article we attemptto provide a general picture of how, andwhy, parametric testing is used in the designand manufacture of integrated circuits.

Test system descriptionBefore describing how and why parametrictesting is done, it is useful to understand theequipment used to make the tests. Anumber of different brands of equipmentare used within RCA to make parametrictests. Despite the inevitable differences indetails, all of the testers operate in funda-mentally the same way. Figure 1 shows theblock diagram of a typical test system oper-ated by a dedicated minicomputer. One ofthe functions of the minicomputer is to

Abstract: Parametric testing is widelyused in the development and manufactureof integrated circuits. This paper intro-duces the reader to the basic concepts andprovides an outline of how the elements ofparametric testing work together.

©1985 RCA Corporation.Final manuscript received January 15, 1985.Reprint RE -30-2-5

SWITCHINGMATRIX

INSTRUMENTS& POWERSUPPLIES/h

OUTPUTDEVICES

PROBER

COMPUTER SYSTEM

hoilr1:,SS

STORACA

Fig. 1. Typical test system operated by dedicated minicomputer.

control a set of test hardware in response tothe commands of a test program. The samecomputer can also be used to generate thetest program. The test hardware consists ofprogrammable power supplies, meters, andan elaborate switching network. The com-puter can connect the test instruments usingthe switching network to, typically, any of64 different output pins. These pins makecontact, via probe cards, to pads on thecircuits to be tested.

In addition to controlling the powersupplies and the measurement equipment,the minicomputer stores the measured valuesonto disk files, and for archiving data, sup-

ports magnetic tape. In some systems thesame computer that gathers the data is alsoused to analyze it. All of the test systemsalso incorporate an elaborate self -test rou-tine to verify the accuracy and precision ofthe power supplies as well as testing to seethat the switching matrix operates as ex-pected.

Data analysis can be as complex a pro-blem as testing. Every parametric test sys-tem we are familiar with comes with someprovision for analyzing the data. Analysisreports are usually generated for each lot.However, when experiments are run, thereports have to be generated in accordance


Writing Test Programs-avoiding the gathering of garbage

Writing a WAT program that willmeasure the parameters soughtis far from being an easy task.The article by Brehm illustratesan approach to building complextest programs from prewrittenmodules. The creation of theoriginal modules and the specifi-cation of the order of applicationof the tests from these modulesconstitutes the true art of para-metric test program generation.

Consider what happens in try-ing to establish the properties ofthe transistor shown in cross-section in Fig. A. The structure ofthe transistor is really quite sim-ple. It has three electrodes calledsource (1), gate (2), and drain (3).The source and drain are ofopposite conductivity type to thebody (4). The gate is isolated fromthe body by a thin layer of insula-tion. In some technologies-not-ably CMOS-the body may be aregion of opposite conductivitytype diffused into the substrate.The transistor shown is an n -channel device, typical of p -wellCMOS technology. In highlysimplified terms, almost no cur-rent should flow from source todrain unless some minimum vol-tage (the threshold voltage) isapplied to the gate. The curve -tracer display shown in Fig. Billustrates the expected currentflow (Y-axis) as the source todrain voltage is increased (X-axis). Each curve in the figure isfor a different value of gatevoltage.

Integrated circuit designersand builders almost always de-scribe a transistor in terms of itssize (length and width) along withan extensive set of parametersthat describe how well it oper-ates. In fact, the design of circuitsis based upon mathematicalmodels of how a transistor oper-ates, and the value of theparameters that are used in themodel are derived from paramet-ric testing. Three of the mostcommon parameters are:

1. Threshold voltage-the min-

GATE

SOURCE DRAIN

BODY

(ALso CALLED THE vvELL1

SUBSTRATE

Fig. A. Cross-section of a typical n -channel CMOS transistor.

imum voltage that has to beapplied to the gate to cause aspecified current to flowbetween source and drainwhen a bias voltage is appliedbetween the latter twoelectrodes.

2. Leakage current-the currentthat flows between source anddrain when the gate voltage iszero (or at some voltage lessthan the threshold voltage) fora given bias between sourceand drain.

3. Drive current-the current thatflows between source anddrain when the gate voltage isat some predetermined valueabove threshold and a biasvoltage is applied betweensource and drain.The main text describes how

manufacturing decisions will bemade based on the values ofthese parameters. It is veryimportant that the data that isreturned represent the value ofthe parameters, and not arbitrarycurrents and voltages. The temp-tation of the first-time user of aparametric test system is tosimply apply the voltage or cur-rent called for in the test specifi-cation and obtain the relevantparameter. A much safer proce-dure is to first verify that the tran-sistor being measured meets cer-tain criteria. These criteria attemptto answer the question "is thisstructure a valid transistor?" Thetest sequence given below isused to answer that question.Failure to pass any of the testswill cause the test program to

skip over that transistor. None ofthe data derived from it willappear in the database.1. Diode tests-a set of tests are

made on all of the diodes ofthe MOS transistor structure.These tests also confirm conti-nuity between the tester pinand some part of the MOStransistor.

a. Apply a foward current andmeasure the voltage. Voltagesbelow a lower limit are shorteddiodes. Voltages above ahigh limit are open diodes orconnections. Failure of eithertest aborts further tests.

b. Apply the voltage found in stepa and measure the current. Ifthe ratio of the foward currentto this current is less than alimit, then the diode is a failure(does not rectify).

2. Gate isolation test-check tosee if the gate is shorted to anyof the other electrodes of thedevice. There is no way to testfor open gates unless twoprobe pads are dedicated toone gate. Passing the transis-tor action test (below) guaran-tees that the gate is not open.

a. Ground all of the device termi-nals except the gate. Apply atest voltage to the gate andmeasure the current. If the cur-rent is greater than some limit,the device fails.

3. Transistor action test-checkto see that the gate controlsthe current flowing from sourceto drain.

a. A small bias voltage is placedon the drain, typically 0.1V. A


4 Vg(V),5

45

4

35

5Vd (V1

32

t 2

10

Fig. B. Current flow as a function ofdrain current.

small voltage (safely below theanticipated threshold voltage ofthe transistor) is applied to thegate. The source -drain currentis measured. Devices arerejected as shorts if too high acurrent flows.

b. The same test as in a, but thevoltage on the gate is chosenwell above the anticipatedthreshold voltage. If thesource -drain current is toohigh, the device is rejected asa short. If the source -drain cur-rent is too low, the device isrejected as being open. If theratio of the second test to thefirst test is less than somechosen limit, the device isrejected for failing to showtransistor action.

Transistors that pass all of theseinitial suitability tests are accep-table for parametric testing. Fail-ure to test for suitability will "con-taminate" the data base withvalues for improperly functioningdevices.

The combination of these testsensure that the source -to -draincurrent is controlled by the appli-cation of voltage to the gate andbetween the source -drain elec-trodes, not by unanticipatedshorts in one or more of the elec-trodes. The tests also ensure thatcontact is continuous from thetester's computer -controlledpower supplies and meters downto the electrodes of the transistor.

with the way the lot was subdivided. Mostanalysis systems provide for the generationof histograms, calculation of common sta-tistical measures, historical or trend analy-sis, and the calculation of parameters derivedfrom a set or sets of measurements. Graphi-cal output is sometimes supported in theform of scatter plots of one or more varia-bles against each other or the mapping ofparameters using two- or three-dimensionalplots. In general, the analysis of data is aseparable function from that of testing.Sometimes the analyses are complex enoughto require the use of a separate computer. F.Brehm's article in this issue discusses oneapproach to data analysis that has beenfollowed by RCA Laboratories.

Parametric testing andcircuit manufacturingAlthough parametric testing is heavily usedduring the manufacture of integrated cir-cuits, it is only indirectly connected with thefunctioning of specific products (see thearticle by F. McCarty in this issue). Theprime function of parametric testing in anintegrated circuit manufacturing environ-ment is to ensure that the complicated fab-rication process used to produce the inte-grated circuit has been completed satis-factorily. Unlike functional testing, whichverifies that the circuits operate as required,parametric testing returns numeric values.Most integrated circuit fabrication linesrequire that the results of parametric testingmust be within defined limits before thewafers will be released for functional test-ing. When used for this purpose parametrictesting is often called WAT-wafer accep-tance testing. For brevity, we will adopt theacronym to describe all uses of parametrictesting. WAT serves a number of purposesfor a manufacturing operation. The prim-ary function is to avoid costly functionaltesting of parts that are unlikely to operate.The values of the parameters that are mea-sured can be used to provide feedback tocorrect processing errors or drifts in themanufacturing process. Parametric testing,in fact, is an essential element in adjustingthe entire manufacturing process so as tomaximize the yield.

WAT is performed on special test struc-tures that appear on each wafer processedthrough a manufacturing line. These struc-tures are most often elements that are usedin the circuits being manufactured; diodes,transistors, resistors and capacitors, forexample. The same set of test structuresappears on every wafer, independent of thechanging nature of the product on the

Fig. 2. Typical wafer, showing knock-out positions.

wafer. The test structures are usually groupedtogether to form a "chip." This pseudo -chipreplaces one or more product chips on themask, and is called a "knock -out" (forobvious reasons) or a "WAT key." Thephotograph in Fig. 2 shows a typical waferas it appears at the end of the manufactur-ing cycle. The arrow points to one of theknock -out locations. The other knock -outpositions are readily apparent in the photo-graph. Figure 3 is an enlarged view of atypical WAT key used in RCA factories.

Early in the development of a new tech-nology it is not at all unusual to manufac-ture only test chips. The test structures usedfor technology development almost alwaysaddress one type or another of a geometricquestion. A typical question would be"How close can one structure be placed toanother without electrical interaction?" Thetest structures frequently address new waysof making circuit elements. To that end themask set will probably include many morelevels than will be found in the productionset.

Once the basic fabrication technologyhas been defined, the manufacturing of theinitial product (circuit) is begun. At thisearly stage of manufacturing as many as athird of the product sites on a wafer may bereplaced by test chips. The test chip willreplicate many of the important test struc-tures used to develop the technology. Anecessary condition of technology transferfrom a laboratory or development activityto a manufacturing environment is the abil-ity of the learning location to replicate theelectrical properties of specific test struc-tures. Once the process is stable, and largescale manufacturing of a product family hasbegun, the number of test chips is reducedto only four or five on a wafer. Sometimesthe test structures are placed in the "streets",i.e. in the spaces between the chips that are

BOsenberg/Goldsmith: Parametric testing of integrated circuits 31

-:#1111121111111 II It..-.-4111111111111

III41 ,;,,,-i%,,, 1

,... *-,1

1 -sielliOn .i AL r .-4,...

no -r. t! .) tin it es it 0 : lo. ,.4..' ..1., .-- ..' I t4p.;i ;

1b4.. -'1.°- . '

I I a. VI ik0 014 t r..,.., , , ,

Vgil .1,., -1.

14

.

4. - ,, -, .

Fig. 3. Typical WAT key.

left to allow them to be cut apart from oneanother at the end of the manufacturingcycle. This latter approach is required whenusing wafer steppers that lack rapid, auto-matic reticle changers.

As you might imagine, there are manycommunities involved in the design, manu-facturing, and testing of integrated circuitsthat require information about the status ofthe manufacturing line. Designers wantinformation on the possibility of fabricatingstructures that are smaller than those on thepresent circuits so that they can shrink oldparts in a cost-effective manner. Processengineers want information that they canuse to bring the manufacturing proceduresunder tighter control by identifying thoseoperations that detract from yield. Productengineering uses information derived from

WAT to shift the fabrication process so asto yield greater proportions of premiumpriced products. The net result of thesediffering needs is that competition for spaceon a WAT key is intense. Furthermore, theWAT key itself must be kept small to min-imize the loss of productive space on thewafer. This loss can be significant if theproduct dice are large. All of these compsti-tive pressures combine to make the designof an effective WAT key as difficult a job asthe design of a new product.

The use of automatic testing equipmentresults in the need for large pads (typically80 x 80 micrometers) within' he WAT keyto ensure proper contact of the probes.Most WAT key designs turn out to belimited by the number of pads that can beplaced in the area allocated to the die. A

single transistor, for example, may behardly 1/100th of the area of a pad, yet aminimum of three pads are needed in orderto test a transistor. One can arrange testtransistors so that common types (n- or p -channel) have common gates and drains.This allows k transistors to be tested usingonly k+2 pads. However, if one of theelectrodes in any one of the k transistors isshorted or open, none of the transistors canbe fully tested. The awareness of such diffi-culties is one of the factors that makesWAT key designs so difficult. The objec-tive is to produce structures that, whentested, provide unambiguous results thatcan be associated with a single process stepor, at the very most, a single mask level.

A typical WAT program will contain asmany as 100 tests and even more teststatements. The most important parametersderived from WAT testing, for the controlof a manufacturing line, are those that des-cribe how well controlled the transistors areand those that describe how well the resist-ances of the various layers have been con-trolled. The parameters that describe tran-sistor operation are threshold voltage, drivecurrent, leakage current and breakdownvoltage. The resistances are used to verifythe proper operation of processes such asimplantation, diffusion, oxidation, contact,formation, and occasionally, dimensionalcontrol.

Applications of parametric testingParametric testing is not limited to the gath-ering of electrical characteristics of circuitelements. It is possible to design structureswhose electrical properties vary with sizeand placement. The sizes associated withthe transistor also can be derived from a setof electrical measurements followed byproper data reduction.

RCA researchers were early pioneers inthe use of parametric testing for yield pre-diction and yield analysis. Ipri and Sarac&showed that special patterns, which coveredthe entire wafer, could be designed to testthe ability of the process to isolate andconnect circuit elements. For example,metal continuity yield can be predictedfrom a measurement of meandering lines ofvarying length. The probability of a metalline being continuous decreases if the line ismade narrower at the same length or ismade longer at the same width. Knowledgeof how the yield decreases with length andwidth allows the designer to optimize thenumber of good die per wafer.

In the case of yield analysis, W. Ham andA. Crossley' showed that it was particularly


useful to "map" the various parameters thatwere measured. Two -and three-dimensionaldisplays of the transistor parameters dis-cussed in the sidebar are often used to trackdown problems that arise in the manufac-turing process. Patterns that repeat from lotto lot, for example, will point to processsteps where the geometric orientation of thewafer and the manufacturing tool are fixed.

Another example of the advanced use ofparametric testing is in the derivation of thecomplex factors that go into a modern tran-sistor model. The input data is derived fromparametric tests.

ConclusionParametric tests continue to grow both innumber and in degree of complexity. Weexpect that this trend will continue or evenaccelerate to keep pace the growing com-plexity and shrinking feature size of inte-grated circuits. The advantages of increasedcomplexity and speed of modern integratedcircuits are obtained at the expense oflonger and more intricate manufacturingmethods. Parametric testing has becomethe indispensable tool in developing andmaintaining new and efficient manufactur-ing methods.

References1. A. C. Ipri, "Impact of Design Rule Reduction on Size,

Yield, and Cost of Integrated Circuits", Solid -StaleTechnol Vol. 22, pp. 85-91, (Feb. 1979).

2. Crossley, P. A. and Ham, W. E., "Use of Test Struc-tures and Results of Electrical Tests for silicon onSapphire Integrated Circuit Processes," J. Electron.Mater. Z No.4, 465-483 (1983).

Norman Goldsmith is Staff Scientist, RCALaboratories, Princeton, N.J. He startedwith RCA in 1959 in the Materials andComponents Division (since renamed theSolid State Division). He joined RCALaboratories in 1971, after fours years withLaser Diode Laboratories. Mr. Goldsmithreceived the MS degree in chemistry fromStevens Institute of Technology in 1964.His interests encompass all aspects ofsemiconductor fabrication technology,with special emphasis on chemical vapordeposition and the application of compu-ters to processing and process control.Contact him at:RCA LaboratoriesPrinceton, N.J.Tacnet: 226-2627

Wolfram A. Bosenberg is a SeniorMember of the Technical Staff at RCASolid State Technology Center, Somerville,New Jersey. Since joining RCA in 1957,Dr. Bosenberg has held various technicaland managerial positions in both the SolidState Division and the RCA Laboratories inPrinceton, New Jersey. His prior expe-rience includes five years with ITT Stand-ard Electric in Nuremberg, Germany.Dr. Bosenberg, who received a diploma inPhysics in 1951 and a PH.D. in 1955, bothfrom the University of Stutgart (Germany),has been involved in the design anddevelopment of semiconductor devicesand techology, modeling, parametric test-ing and instrumentation since 1949. Dr.Bi5senberg recently retired from RCA.

Bbsenberg/Goldsmith: Parametric testing of integrated circuits 33

F.W. Brehm

A software system for the collectionand analysis of electrical data

Programming a complex test system can be tedious and timeconsuming, but the right kind of software can free theprogrammer from much of the drudgery.

The electrical testing problem is usuallyconsidered to be one where a circuit istested for proper function: making sure thata memory remembers, or that a gate islogical, for example. The "functional" charac-teristics produced by this kind of test are -useful for checking the design of a circuit.However, these tests yield little informationabout the design of the process or devicesused to build the circuit. This kind ofinformation is provided by another type ofelectrical testing: parametric testing.

Parametric testing is used to characterizethe devices that make up a circuit and toprovide information to the manufacturerabout the quality of the process. For circuitsmade of discrete components-resistors,capacitors, individual transistors, etc.- para-metric testing is performed by the manufac-turer of the parts. The information neededby a circuit designer is collected into "specsheets," while other control information iskept by the manufacturer.

Abstract: Enough electrical data mustbe collected to make statistically signifi-cant statements about the performance ofan experimental design for manufacturinglarge scale integrated circuits. The systemdescribed in this article aids in the collec-tion and analysis of this data

@1985 RCA Corporation.Final manuscript received December 18, 1984.Reprint RE -30-2-6

The Integrated Circuit Laboratory at theDavid Sarnoff Research Center, like acomponent manufacturer, is engaged in thedesign of the processes and devices used tomanufacture integrated circuits. The dataused in this design process are collected byseveral means. Optical methods may beused to measure parameters such as filmthickness. The electron microscope may beused to study physical structures. The even-tual goal, however, is to produce electri-cally active components on a silicon wafer.Enough electrical data must be collected tomake statistically significant statementsabout the performance of an experimentaldesign for manufacturing large scale inte-grated circuits. The system described in thisarticle aids in the collection and analysis ofthis data.

System overviewThe requirements of the system design aredictated largely by the interests of theresearchers at RCA Laboratories. Peoplewho become expert in the use of a large andexpensive tester are more interested indoing their own research than in writingtest programs to gather data for anotherperson's experiment. Conversely, there aremany people who wish to use the tester butdo not have the interest or time to learnhow to program it. Therefore, the systemmust be able to collect the knowledge of theexpert in an unobtrusive manner and allow

another person to use the knowledge easily.A study of the typical experimental

method produces additional requirements.The experimental vehicle is usually a sili-con wafer with many copies of a test pat-tern on its surface. This test pattern maycontain one or more devices to be tested.The test procedure requires that measure-ments on each device of interest be savedwith the location of the device and otheridentifying information. The informationcollected during testing should be presentedby graphical and statistical methods.

The nature of process and device researchresults in a short lifetime for most test pro-grams. This means that writing and runningthe test program and analyzing the datashould be easy and reliable. The testing andanalysis programs do not have to be asefficient as those used in a factory, becausethe goal is to optimize the efficiency ofpeople, not of equipment.

A data flow diagram 1,2 of the overallsystem is shown in Fig. 1. An expert intesting or a device physicist designs an algo-rithm to be used for testit g some structure.A computer code called the test function isdeveloped to perform the algorithm whiletaking into account all of the peculiarities ofthe hardware on which it runs. This func-tion is inserted into a library that is availableto all who use the tester.

An experimenter who has the matchingstructure on a test wafer may use this func-tion in a test program by supplying device


names, the test to be performed, and theother values required by the function. Theprogram generator produces a test programand an analysis program. The test programis used to gather data from the wafer, andthe analysis program produces wafer maps,histograms, and statistics.

The library

A library is divided into three parts: STRUC-TURE definitions, FUNCTION definitions,and SUBROUTINE definitions. A STRUC-TURE definition contains the menu offunctions that may be used and the list ofcommon values that every function uses.These values are usually the pad connec-tions. A FUNCTION definition has thename of the subroutine that contains thecode to perform the function and a list ofvalues to be supplied. These values are usu-ally the stimulus and limit values for powersupplies. A SUBROUTINE definition con-tains a list of declarations of inputs andoutputs that must be supplied, and theactual code to perform the measurement.

Figure 2 is a listing of a small library.This library is incomplete for several rea-sons. First, the FUNCTION and SUB-ROUTINE definitions are missing for theRes2V and Res4 functions named on lines6 and 7 of the listing. Second, the functionsin the menu are not enough to test the widevariety of resistor structures that exist.Finally, resistors are not the only structuresthat can be tested. These omissions willhave no effect on the test program shownlater, but a useful library will be morecomplete.

Notice the amount of internal documen-tation in the STRUCTURE and FUNC-TION blocks. These are the two parts of thelibrary that will be read by the person whowrites a test program. This documentation,when written properly, allows a test pro-grammer to use the library independentlyof the person who developed the testfunction.

This decoupling satisfies a major goal ofthe design. An expert can devote more timeto developing new tests for old structures,or new structures that are sensitive to differ-ent conditions. Time is not wasted on writ-ten before. In most cases, a researcher maywrite a test program that will work the firsttime without having to consult with theperson who is the expert on the testingsystem.

The SUBROUTINE block begins withdeclarations of all inputs (lines 37 through44) and outputs (lines 45 through 49). Theset of inputs should equal the set of values

ANALYSISPROGRAM

TESTINGEXPERT

ALGORITHM

TEST FUNCTION

REQUIREMENTS(TEST

JUDE

DATA

STIMULUS

RESPONSE

* EXPERIMENTERTEST

TEST PROGRAM

DATA

REPORT

Fig. 1. Parametric test system structure.

named in the ASK lines of the STRUC-TURE and FUNCTION blocks. The SUB-ROUTINE will return values for one ormore RESPONSE, and for one of theERROR values.

There are several things to notice in thecode of the SUBROUTINE in the illustra-tion. All these were put in by the author ofthe routine, but probably would have beenmissed by an inexperienced or sloppy pro-grammer. Line 61 contains a check for apower supply compliance limit. Failure tocomply will cause erroneous values to bereturned for the resistance of an open cir-

cuit. The resistance is assigned a valuedefined to be "OverRange", and the errorcode "Open" is returned. Line 68 checksthat the absolute value of the measuredvoltage is not less than a value called"VM1Accuracy." This check was insertedafter noticing that the routine sometimesgave negative values of resistance for ashort circuit. The resistance is assigned avalue of zero, and the error code "Short" isreturned. Line 74 contains an explicit checkfor divide -by -zero. This protects against anasty run-time error that is the result of acoding error in the test program. In this case

Brehm: A software system for the collection and analysis of data 35

4

07

8 ASK9

10

11

12

1314

151617

1819202122232425262728293031323334 END353637383940414243444546474849505152535455565758596061626364656667686970717273747576

The numbers on the left are not part of the library. They are for

reference only. The sharp character ("*") introduces a comment.

1 LIBRARY Sample "A consistent (14 incomplete) library."

3 STRUCTURE Resistor "Resistor Structures"MENU

Res2 "Two terminal resistance measurement"Res2V "Two terminal resistance measurement (force voltage)"Res4 "Four terminal resistance measurement"

LOHIC est

"Ground connection""Connection for current or voltage application""Approximate capacitance of structure in farads"DEFAULT = 0.0

HELPResistances may be measured on two terminal or four terminaldevices. The C est value should be supplied if the structurehas an area large enough that the charging time isappreciable.

END

FUNCTION Res2 "Two terminal resistance measurement"ASK

I "Current to force". V max "Compliance voltage for current source"

DEFAULT = 100.0CALL res2HELP

The current I is forced from the HI to LO connections with avoltage limit of V max. The resulting voltage is measuredand the resistance R is calculated. If the voltage is lessthen the voltmeter accuracy then the resistance will be zero.and the error "Short" will be returned. 14 the compliancelimit V max is reached then the resistance will be OverRangeand the error "Open" will be returned.

SUBROUTINE res2 "Two terminal resistance measurement."PIN

LO "Ground connection"HI "Connection for current or voltage application"

STIMULUS1 "Current to force from current source"

LIMIT max "Compliance voltage for current source"C est "Approximate capacitance of structure"

RESPONSE"Measured resistance"

ERROROpen = 1 "Resistance too high to measure"Short = 2 "Resistance too low to measure"

CODErealexternal filc. mvlInteger filcreal mvl

* CONNECTcall pin3 (LO. GND. VM1L)call pin3 (HI. 1St. VM1H1

* FORCEif (+11c(I. V max. C est) '= InRancle)

= OverRanciereturn (Open)

* MEASUREv = mvl (IIf (abs(v) VMIAccuracv)

= 0.0return (Short)

* compliance limit

S accuracy limit

S CALCULATEIf (I '= 0.0) * don't divide by 0

R = v/IEND

Fig. 2. A sample library.

the resistance is left undefined and wouldbe considered "Empty" by the analysisroutines.

The numbers on the left are not part ofthe library. They are for reference only. Thesharp character (#) introduces a comment.

The program

To illustrate the programming process, letus suppose that we must investigate theuniformity of a polysilicon patterning pro-cess over the whole area of a wafer. We

have a test pattern that contains a resistorwhose value is proportional to the linewidth produced by the process. (A real testpattern would contain more devices becauseother factors may cause the resistance tochange.) We know to expect resistances ofabout 10k ohms. This test pattern will berepeated many times on the wafer. The pro-gram to test the resistor is shown in Fig. 3.

The items named in the ASK list of theresistor library are defined on lines 8 and 9.The "C est" item will have a value of 0.0 asspecified by the DEFAULT value in thelibrary. The stimulus current and limit vol-tage are specified in lines 13 and 14. Thisprogram is quite small compared to onewritten from scratch. It does not have anyexplicit output statements, nor does it tellanything about the repetition of the testpattern. Instead it concentrates on the mea-surement of a single resistor.

The output statements are generated bythe program generator from information inthe library. The measurement program willbe invoked each time the probes are restingon the test pattern. The measurementsmade by the test program will be storedalong with the location of the pattern, theexperiment identification, and the waferidentification.

This is another instance of decoupling inthe system. The test programmer does nothave to learn the exact format of the datafiles that the analysis program reads, andmore importantly, cannot make mistakes inwriting the code. The instructions to makethe wafer prober work may also remain(blissfully) unknown.

This simple program cannot illustrate allof the facilities of the program generator. Astimulus value may be a function of a pre-viously measured result. For example, thedrive current of an MOS transistor may bemeasured at a gate bias several volts higherthan the measured threshold voltage. TheIF -THEN -ELSE control structure may beused to modify the flow of testing to avoidcontaminating the data with measurementson devices that are not functioning prop-erly. For example, it makes little sense toperform measurements that characterizethe behavior of a MOS transistor if thethreshold voltage changes after a stress isapplied.

Running the program

A set of wafers (usually called a lot) is testedby giving the wafers and pertinent informa-tion to the system operator. The requiredinformation includes the probe card, theexperiment or lot identification, and the


size of the pattern to probe. When the oper-ator mounts each wafer on the prober theidentity of the wafer and the name of theprogram must be supplied. The operatorinitiates the analysis by answering a fewmore questions, and the analysis printoutsare delivered to the researcher.

The interaction between the operatorand the test program is always the same, sooperators do not have to go through a train-ing period for each new program. This is abig advantage because a test program maybe used to test only a few wafers.

The program generator provides morefacilities that may not be appreciated bysomeone who has never tried to write anddebug a test program. Debugging state-ments that may be enabled at run time areinserted by the program generator. This isinvaluable when trying a new test program,or when the system hardware or a libraryfunction is suspected of misbehaving.

The numbers on the left are not part ofthe program. They are for reference only.The sharp character (#) introduces a com-ment.

The data analysis

The sample printout shown in Fig. 4 is,except for one detail, the default printout ofthe analysis system. The one detail is theformat of the histogram. The portion of thesample program that produced this printoutis shown in Fig. 5. Line 19 has been re-placed by line 20, which sets the endpointsof the histogram display to 0 and 30,000.The number of categories, or bars, in thehistogram was changed from 50 in line 21to 60 in line 22. This produces a rationalscale on the horizontal axis.

We can now see the result of our exper-iment. The patterning process has producedalmost a two -to -one variation in line widthover the wafer (see lines 21 and 22). Thewafer map (lines 26 to 37) shows that thevariation is strongly related to the positionon the wafer. It looks like this test programwill be used again!

Line 1 contains the lot, wafer, and pro-gram identification as entered by the opera-tor. Notice that this is the second page of theanalysis printout. The first page containsitems such as the date and time the waferwas tested, the version number of the testprogram, and some information used bythe system. Lines 3 through 5 contain thedevice, test, and response names from thetest program. This is followed by a histo-gram (HIST), some statistics (STAT), awafer map (MAP), and a population table(TABLE) for the wafer map. The first line

The numbers on the left are not part of the program. They are forreference only. The sharp character ("*") introduces a comment.

1 PROGRAM Poly "A program to measure one resistor."2 FROM LIBRARY Sample3

4 VERSION 1.0 "F. Brehm for RCA Engineer"56 DEVICE Poly "Poly resistor."7 IS STRUCTURE Resistor8 LO = 10 * Resistor common pad9 HI = 15 it Poly pad

1011 TEST Res "Resistance of Poly resistor."12 USE FUNCTION Rest13 I = 1E-4 it amps14 V max = 10.0 * volts15 END TEST16

17 END DEVICE18 END

Fig. 3. A sample program.

The line numbers do not appear in the actual printout. They are forreference only.

1 Lot EXP1 Wafer 2 Program POLY

.3 Device POLY4 Test RES5 Response R67 HIST test8 51+9 4:

10 3:

11

12131415161718 STAT test 1 POLY:RES:R19 Of 32 Observations Of20 0 <= UnderRange 021 Min = 1.0113E+04 Min22 Max = 1.8750E+04 Max23 0 '= OverRange 024 0 Illegal Values Pass2526 MAP test27 X = 49928 50029 1-+----:30 500+ 1111 +31 501:111222:32 502:322333:33 5031444445134 504:666678:35 505+ 989A +36 :-+----:37 5003839 TABLE test 1 POLY:RES:R40 Category Pop. Low Limit41 1 (1) 7 1.0113E+0442 2 (2) 5 1.0976E+0443 3 (3) 4 1.1840E+0444 4 (4) 5 1.2704E+0445 5 (5) 1 1.3567E+0446 6 (6) 4 1.4431E+0447 7 (7) 1 1.5295E+0448 8 (8) 2 1.6159E+0449 9 (9) 2 1.7022E+0450 10 (A) 1 1.7886E+0451 10 LIN categories

Poly resistor.Resistance of Poly resistor.Measured resistance

1 POLY:RES:R+5 +

**** *2: ** *

1: ******** ****** *

0:+- -+0.00 5.00E+03 1.00E+04 1.50E+04 2.00E+04 2.50E+04

2.50E+03 7.50E+03 1.25E+04 1.75E+04 2.25E+04 2.75E+0460 LIN categories from 0.00000 to 30000.

Page 2

32 Passing 32 Analyzed LIN6638. Mean = 1.3186E+04

= 1.0113E+04 Median = 1.2738E+04= 1.8750E+04 Std Dev = 2355.

2.0888E+04 C of V = 17.86%100.00% Analyze = 100.00%

1 POLY:RES:Rto 504: Y = 500 to 505

Minimum Maximum High Limit1.0113E+04 1.0962E+04 1.0976E+041.1175E+04 1.1825E+04 1.1840E+041.1988E+04 1.2488E+04 1.2704E+041.2988E+04 1.3463E+04 1.3567E+041.3863E+04 1.3863E+04 1.4431E+041.4525E+04 1.5213E+04 1.5295E+041.5863E+04 1.5863E+04 1.6159E+041.6250E+04 1.6738E+04 1.7022E+041.7175E+04 1.7350E+04 1.7886E+041.8750E+04 1.8750E+04 1.8750E+04

from 10113. to 18750.

Fig. 4. A sample analysis printout.

of each of these contains the type of display,the internal test number, and the test title.

The graphics are low resolution because

a line printer is used as the output device.This is sufficient for a quick look at the data.If high resolution graphics or multivariate


The numbers on the left are not part of the analysis program.are for reference only. The sharp character ("*") introducescomment.

1 * 0001 POLY:RES:R Measured resistance2 TOP3 C Device POLY4 C Test RES5 C Response R

6

7 * Get the data8 TEST 00019 TITLE POLY:RES:R10 DISTRIBUTION normal11 POLARITY default12 PASS underranae overranae1314 * Scale data as necessary15 *NEG ABS MULT RECIPROCAL etc.16 *TITLE POLY:RES:R17

18 * Histogram19 *DISPLAY default20 DISPLAY 0 3000021 *BARS 5022 BARS 6023 HIST2425 * Statistical summary26 LIMIT default27 STAT2829 * Wafer map and population table30 BARS 10

31 *LIMIT default32 *DISPLAY default33 AVERAGE34 MAP35 TABLE

Poly resistor.Resistance o4 Poly resistor.Measured resistance

Theya

Fig. 5. The analysis program.

analysis is required, then the data of interestmay be written to a file in tabular form forprocessing by another program.

The histogram is constructed by dividingthe display range into a number of catego-ries and counting the number of data valuesthat fall into each category. A vertical barwith height proportional to the count isdrawn for each category. The wafer map isconstructed the same way except for thefinal display. Each location on the wafermap represents a test site. The code lettershows the category for the measurement onthat site. The table shown below the wafermap represents the population of each cate-gory in the map. Note that a plot of popula-tion ("Pop.") versus "Low Limit" would bea histogram.

The data axis is linear in this example.The data axis should be logarithmic formeasurements such as transistor leakagecurrent. When the data axis is logarithmicthe size of each category is some multiple ofthe previous category. For example, divid-ing the range 1 to 1000 into three logarith-mic categories would give the followingtable:

Category Low Limit High Limit1 1.0 10.02 10.0 100.03 00.0 1000.0

The statistics table is divided into threecolumns. The first column represents all ofthe data. A PASS range (line 12 in Fig. 5) isdefined to exclude any data that are mea-surement failures. In this example thePASS range could have been defined as 0.0to OverRange, but it would not have madeany difference. Additional data may beexcluded for logarithmic statistics if theyare not positive.

The second column represents all of thegood measurements, but not necessarily allof the good data. If a priori knowledgeexists about a "good" data range, then theLIMIT statement may be used to define itin the analysis program (line 26 in Fig. 5).The default limits are computed by a statis-tical procedure that attempts to remove anyoutliers or data points that are probablyerroneous. The procedure is a modificationof the method used to calculate fences in aboxplot.3 It was developed by AchillesKokkas with help from Russ Barton andDon Barton. No assumptions are madeabout the distribution of the data. The first,second, and third quartiles of the passingdata are calculated. Call these q1, q2, andq3. The limits are calculated by the follow-ing formulas:

Low Limit = q - 3.0 * (q1-q1)

High Limit = q3 + 3.0 * (43-92)

The third column gives some statisticsfor data that fall within both sets of limits."Mean" and "Std Dev" are the samplemean and sample standard deviation, re-spectively. They are computed in the usualway when the data distribution is defined tobe "NORMAL." For "LOGNORMAL"data the sample mean (a) and samplestandard deviation (a) of the logarithm ofthe data values are computed. The printedstatistics are calculated as follows:

Let w = e 0.2

and m = ei2

Then Mean = m e a31

Std Dev = m W2-W

The coefficient of variation ("C of V") is the"Std Dev" divided by the "Mean" inpercent.

The mean and standard deviation arequantitatively meaningless when the distri-bution is unknown. These statistics appearfor historical reasons. Many people arefamiliar with these numbers and are un-comfortable with anything different. Itwould make more sense to print statisticsthat do not make any assumptions aboutthe distribution of the data. These are called"non -parametric statistics."

The only non -parametric statistic in theprintout is the "Median," or second quartileof the data. We (Achilles Kokkas and I) areexperimenting with some non -parametricstatistics. The midrange is, like the standarddeviation, a measure of the spread of thedata. It is equal to the third quartile minusthe first quartile. A statistic similar to "C ofV" above may be calculated by dividing themidrange by the median and expressing theresult in percent. A statistic we call the"Symmetry Ratio" is a measure of thedirection of greatest spread. When q 92,and q3 are the first, second, and third quar-tiles of the data to be analyzed, the symme-try ratio is:

SR = (42-q1) / (43-92)

The line numbers do not appear in theactual printout. They are for reference only.

The numbers on the left are not part of theanalysis program. They are for referenceonly. The sharp character (#) introduces acomment.

Conclusion

The goals of the system design are met byhiding the tricky, tedious, difficult, and


error prone aspects from the experimenter.The test functions that require an intimateknowledge of the test hardware are thedomain of the testing expert. These testfunctions are reusable, thereby eliminatingredundant effort and allowing others toshare the results of good programmingpractice. The price for this is paid by theexpert, not the user. It is a small pricebecause good documentation, which shouldbe produced anyway, will reduce the numberof telephone calls and visits from confusedusers.

The system software aids the user inmany ways. Explicit read and write state-ments are not required in either the libraryor the program language, and are kept to aminimum in the analysis language. Theoperator follows the same procedure whenrunning each program. The wafer prober, afussy device, does not need to be pro-grammed. Information used to identify thedata is always collected and stored the same

way. Identifying information is automati-cally carried from one step to the next.

The system does not guide the experi-menter in the design of test chips, nor does itsuggest an overall strategy. These functionswould require the application of artificialintelligence research (that is, an expert sys-tem). In any case, the experimenter shouldhave some idea of the measurements requiredfor the experiment. This system does makeit possible to use a complex tester withoutlearning the details of its operation.

References

1. R. Poulo, "Software design methodologies applied toremote process control," RCA Engineer, Vol. 25, No.3, pp. 55-59 (Oct./Nov. 1979).

2. T. DeMarco, Structured Analysis and System Specifi-cation, Yourdon, Inc. (1978).

3. P.F. Velleman and D.C. Hoaglin, Applications, Bas-ics, and Computing of Exploratory Data Analysis,Daxbury Press (1981).

Fred Brehm joined the Integrated CircuitTesting and Process Control group atRCA Laboratories in 1975. He worked inthe areas of process control, semiconduc-tor device simulation, international datacommunications, and VideoDisc andsemiconductor device testing. He receivedthe RCA Laboratories Outstanding Tech-nical Achievement Award in 1977. Mr.Brehm is no longer with RCA.


F. McCarty

Integrated circuit engineering analysis system

We must establish a thoroughly complete method of evaluatingour manufacturing processes and products, one that will enableus to make cost effective real-time corrections.

Over the last 20 years, integrated circuittechnology has made enormous leaps inknow-how, equipment, techniques, andresults. Through advances in nearly everyphase of semiconductor design and manu-facture, we have come from one junction tohundreds of thousands of junctions per die;from one gate component per chip to thou-sands of gates contained in the same activearea; from handling one device at a time tohandling batches of wafers, each of whichcontains hundreds of large scale integratedcircuits. Yet in one area, although difficultto believe, our industry is still using thetechnology of the fifties. That neglectedarea is engineering analysis. The industrystarted using lot card travelers to recordin -process readings, operator, equipmentIDs, and values .of curve tracer readings for

Abstract: Today's semiconductor indus-try is experiencing a major evolution inthe area of automation. Sophisticatedcomputer aided manufacturing (CAM)systems are being introduced that arecapable of handling the complex envi-ronment associated with semiconductormanufacturing. However, many systemsrely on manual data entry, and depend onhumans to establish a physical link be-tween computers and very high technologyprocessing equipment. As a result, the in-dustry is still plagued with improper pro-cessing and invalid data related to humanerror, with substantial penalties in costsand time.

©1985 RCA Corporation.Final manuscript received February 4, 1985.Reprint RE -30-2-7

wafer accept and final test. The curve tra-cers have been replaced, but all else remainsthe same. To evaluate a low -yield wafer lotor a process change against normal produc-tion, it is first necessary to define normalproduction. Typically, this involves gather-ing all available information on lots fabri-cated during a time interval deemed to benormal, and then manually tabulating thisgenerally incomplete information. Fromsuch a skimpy database, process, assembly,and test decisions are made that will finan-cially affect that product line for years.

The competitive nature of the IC busi-ness demands devices that do more, arefaster, and operate over wider environmen-tal conditions-all at an increasingly lowercost. In order to satisfy this need the indus-try focus is now on CMOS technology. Themomentum toward CMOS by the Japa-nese and some classical CMOS domesticvendors has increased dramatically duringthe past year. Over the next five yearsCMOS is expected to make enormouspenetration in both memories and micro-processors.

In order to meet the market demands,accomplish the present long term plans, andachieve the yields required to remain costcompetitive, we must establish a thoroughlycomplete method of evaluating our pro-cesses and products, one that will enable usto make cost effective real time corrections.

Today's semiconductor industry is expe-riencing a major evolution in the area ofautomation. Sophisticated computer aidedmanufacturing (CAM) systems are beingintroduced that are capable of handling thecomplex environment associated with semi-conductor manufacturing. However, many

systems rely on manual data entry, anddepend on humans to establish a physicallink between computers and very hightechnology processing equipment. As aresult, the industry is still plagued withimproper processing and invalid data relatedto human error, with substantial penaltiesin costs and time.

The RCA Solid State Division's Memory/Microprocessing facility in Palm BeachGardens, Florida undertook the major taskof defining and implementing an integratedcircuit engineering analysis system. Oncethe system was defined, a specification waswritten and presented to management forreview. Using the specification as a guide, astudy was made to determine if the presentRCA analysis software could be upgradedto support such a project, or if RCA shouldpurchase the system from an outside vendor.

Comparison of results between RCA'sTest Data Analysis System (TDAS) andoutside vendor capabilities showed thatPalm Beach Gardens definitely should pur-chase a vendor product. Many factors wereconsidered in making the decision to pur-chase an engineering analysis softwarepackage from a vendor:

1. Is the software available today?2. Is the software "user friendly?"3. Does the software provide a common

database?4. Is the product supported by vendor

representatives?5. Will the software make use of existing

software files?6. Do training courses exist?

Various vendor software products were


RAWSILICONWAFERS FABRICATION

PARAMETERS

PHASE 16

WAT

PARAMETERS

PHASE 1A

CIRCUITPROBE

PHASE 1A

ASSEMBLYTAIWAN/

MALAYSIA

PHASE DI

FINALTEST

TAIWAN/MALAYSIA

PHASE DI

LOWEST LEVEL OFDATA RECORD LOT WAFER WAFER LOT LOT

WAFERMOVEMENTS

DEFECTDENSITY

YIELDSWAFER/DICETRACEABILITY

PERFORMANCEBINS

INS GATE SHORTS % YIELDS LOT NUMBER ACCESS TIMINGOUTS OPEN CONTACT NDPW DATE CODE HIGH/LOW VOLT

REJECTS METAL OPENS (NET DICE PER WAFER)

OPERATORID

PARAMETRICTEST

DATALOGBINS

TC-1 0

REJECTCATEGORIES

FAILCATEGORIES

EMP. NUMBER BREAKDOWNS FUNCTIONAL PELLET INSPECT FUNCTIONALSHIFT SHEET RHO'S PARAMETRIC MOUNT/BOND PARAMETRIC

THRESHOLD MEAS.

EQUIPMENT DC QCID PARAMETRICS ACCEPTANCE

FURNACE TUBE GROSS LEAKAGE PDA (PERCENT DEFECTS ALLOWABLE)ALIGNER # OUTPUT DRIVES AQL (ALLOWABLE QUALITY LEVEL)

CONTACT

VISUALELECTRICAL

PARAMETERS

TOX OXIDE THICKNESS)V/I (VOLTAGE/CURRENT)C -V (CAPACITANCE -VOLTAGE)

Fig. 1. Data generation and flow through an engineering analysis system.

evaluated before deciding on one vendor.No one vendor could meet all of the expec-tations defined in the specification. Thedecision was made to purchase HewlettPackard's EA -10 software package due tothe compatibility between EA -10 and theexisting HP IC -10, which is a softwarepackage structured to store work -in -process(WIP) data for the manufacture of inte-grated circuits.

Figure 1 shows the flow for total wafermanufacturing data generation for an engi-neering analysis system. Although the flowshows five separate data generation areas,the initial implementation of the analysissystem is only going to generate data fromthe wafer fabrication, wafer acceptancetest, and wafer circuit probe areas. Theassembly and final test areas will be addedin the future.

Each area will generate unique datathat relates to the particular function ofthe area.

Area Data

Fabrication Wafer movementOperator identifi-cationEquipment identifi-cationVisual/electricalParametrics

Wafer acceptance Defect densitytest Parametric testCircuit probe Yields

Data log binsDC parametrics

Assembly Wafer/die traceabilityReject categories

Final test Performance binsFail categoriesQuality controlacceptance

The lowest level of data recorded also willvary from one area to another. Fabrication,

assembly and final test gather data at the lotlevel, and wafer acceptance test and circuitprobe gather data from each individualwafer within a lot. The type of data col-lected at each area is also shown in Fig. 1,and represents only a small sample of theenormous amount of data that will be col-lected throughout the wafer fabrication andtest procedures/steps.

In order to collect each individual type ofdata, different software packages were deve-loped and tailored to pass data to a com-mon database. Figure 2 shows the engin-eering analysis data collection flow in ourpresent environment. Future plans for col-lecting data in the assembly and final testare not shown in the flow.

The EA -10 software packageThe EA -10 (engineering analysis) system isan interactive, online system that allows allengineering groups to extract production

McCarty: Integrated circuit engineering analysis system 41

The engineering analysis system specification

Integrated Circuit EngineeringAnalysis System Palm Beach GardenSpecification -1984

I. PurposeTo provide a user-friendly interactive computer sys-tem that is capable of monitoring, storing historicaldata, and evaluating and controlling key parametersthat impact integrated circuit manufacturing.

II. Benefits Improved process control Reduced defect densities Increased product yield and quality Cost reductiono Provision for long term historical data trends, gra-

phics and plots for engineering analysis Accelerates the manufacturing learning curve by

reducing the effective cycle time for productanalysis.

III. FunctionsA. Real-time data collection and historical data archive.1. Real-time is defined as within a 24- hour period.2. Data collection points (DCP) can be categorized into

five general areas:

Fabrication parameters WAT parameters (electrical parametric test) Circuit probe (circuit functionality testing) Offshore assemblyo Final test

The quantity of data is specified in Fig. 3 at eachdata collection point. Phase I of the system willinclude circuit probe yield, bins, parameters bywafer, and fabrication parameters by WAT lot. Thesystem must have the capability to collect assemblyand test data in the future.3. Data entries must be validated at each entry point.4. Fabrication lot information within the past four

months must be in the "ON LINE" database. Themaximum number of lots in a four -month period is1600 lots in 1984 up to 3500 lots in 1986. Themaximum number of wafers in a lot is 45 at WATand circuit probe.

5. Historical data archive must include fabrication lotinformation for one year.

B. Notification of equipment and process monitoralarm set points.1. The system will notify the user on an exception

basis of any process or equipment out -of -controlcondition through automatic report generation.

2. This feature is termed an alarm function forexcepreporting.

C. Statistical correlation, graphical display, andreport generation among process, equipment, andfacility variables.1. The system must make all of the data captured

throughout the manufacturing process readilyavailable to a wide user community in real-time.

2. Users must be able to proceed from question, toanswer, to further questions without losing theiranalysis objective.

3. The system must be designed to maintain quickresponse time, even with many simultaneoususers.

4. The system must be an interactive, on-line systemthat allows the process/product engineeringgroups in an integrated circuit environment toextract and analyze production data.

5. The system must have one integrated databasethat allows users to perform logical retrievals ofdata of any system parameter through a simpleEnglish -like query.

6. The analysis programs must include trends, scat-ter plots, histograms, statistical analysis andreports.

7. Reports, plots, etc. must have user -defined, alpha-numeric label without the need for cross referencetables.

D. Real-time closed -loop equipment and processcontrol.

1. The system will permit interfacing each measure-ment process monitor and "intelligent fabricationequipment directly to a central computer, forautomatic data collection and recipe "download"at specific process steps.

2. Each link to computer will require individual cus-tomized software per semi standards (1982 secs2) for each piece of equipment.

IV. Product MilestoneA. Phase I

1. Circuit probe, yield, bins andWAT parameters by wafer.

2. Fab parametersB. Phase II

1. Process controlC. Phase III

1. Assembly and test


data for statistical analysis, graphic analysis,and reporting purposes. There are threebasic steps to its operation :

Step 1: Transfer. Weekly/daily transfer ofIC -10 WIP data and EN -10 engineeringdata into the EA -10 database.

Step 2: Data selection. User selection ofdata to be analyzed into user report file.

Step 3: Data analysis. Analysis of selecteddata in the user report file using EA -10statistical analysis, graphics output, or re-port software. EA -10's data selection soft-ware converts a user request for data into anextract program.

Access command This specifies the path tobe used when data is collected. There arefive path names in EA -10:

Equipment Part All

Date Process

Select command This narrows the selec-tion requests by eliminating lots that qualifyaccording to the access statement.

Extract command This tells the EA -10software to file certain items and theirrelated values if they have met the Accfssand Select command criteria.

Go -Now command. This compiles yourselection request and extracts the requesteddata. Once your selection request is com-piled and extracted, you can do any of threetypes of analysis on the extracted data:

1. Graphical2. Statistical3. Report writing

GraphicsWhen it comes to solving problems, onechart or graph can be worth a dozenreports. The following types of graphicrepresentations are especially important tosemiconductor engineers because they illust-rate complex correlations and relationshipsin easy -to -read formats:

Pie chartsLine charts

Scattergrams Horizontal or vertical bar charts

Control charts

Statistical analysisThe statistical software consists of proce-dures for the statistical analysis of a filecomposed of parameters and variable namesthat have been selected by prior EA -10extractions. The statistics software allowsprocedures in different category levels.

Elementary statisticso Chisquareo Frequency Scatter Correlation Groupsort Tabulate Elemstat Percentile

Advanced statistics Analysis of variance Canonical correlation Discriminant analysis Factor analysis

Linear regression Polynomial Data smoothing

Data transformationsSum

o Gaussian Difference Random numberD Product Sine Divideo Cosine Exponential Square rooto Inverse Power Log

Report writingThe report writer is called QUIZ, which is aproduct of COGNOS Corporation and isnot sold by Hewlett Packard, but can bepurchased separately. These are some of itsadvantages:

It uses an easy -to -learn set of statementsto produce reports in a formatted orunformatted style.Data can be accessed in a predeterminedorder.

Data can be extracted by key value. Data can be sorted in ascending or des-

cending order. A final summary of the report can be

printed or displayed.

The EN -10 software

The EN -10 (engineering data collection)system is stored in the IC -10 database, andmanually collects wafer fabrication engi-neering data for each wafer lot at selectedoperations. An example of EN -10 data col-lected on each lot in one of the fabricationareas is shown in Table I.

The TC-10 softwareThe TC-10 (tester data collection) system isstructured to collect keithley wafer accep-tance test (WAT) and circuit probe testresults and enter the data into the EA -10database. Future plans are to take FairchildSentry/Series 10 circuit probe test data andinsert the data into the EA -10 database.Initially, data will be collected on magnetictape and transferred to the database, buteventually communication links betweentester host computers and the HP3000 willautomatically transfer the data.

The IC -10 software

The IC -10 system monitors each lot in thefabrication area, providing managementwith up-to-the-minute status reports, andpasses move/yield and equipment identifi-cation information to EA -10. All engineer-ing -related data from IC -10 is automati-cally transferred to the EA -10 database.Operation lot tracking (OLT) is an exten-sion of IC -10 and allows a lower levelbreakdown of a lot's status, providing amore detailed report for management. Italso provides:

Detailed "two -level" lot tracking.Increased process flexibility.

Tracks between stations.Automatic on-line instructions.Improved operator productivity.

As can be seen in Fig. 2, the EA -10 soft-ware package is the hub of the analysissystem. It contains software to generate var-ious engineering reports, and also containsthe common database to which all othersoftware packages pass data. Each engineeruses a video display terminal to access thedatabase. Real-time and historical dataextractions can be performed with a min-imum of computer knowledge. The "userfriendliness" of the software system enablesthe engineer to concentrate on analyzingproblems without spending time learningthe intricate details of the software architec-ture. Once the requested data has beenextracted from the database, the engineerhas the option of using any of the three


Table I. EN -10 data collection points.

CMOS 2

1. P drive thickness (tox)2. P drive resistance (Rs)3. Active area inspect (CD)4. P. Implant resistance (RS)5. Depletion implant (Rs)6. Gate oxide 2/anneal (tox)7. Poly deposition (TSI)8. N+ resistance on poly (Rs)9. N+ resistance on single crystal (RS)

10. Gate critical dimension (CD)11. Re -oxide thickness (tox)12. P+ S/D resistance (Rs)13. N+ S/D resistance (Rs)14. Boron phosphorus silicon glass

deposition/ density (SOITH)

CMOS 2 DLM (double -level metal)

1. P drive oxide thickness (tox)2. P drive junction depth (tox)3. Active area after etch insp. (CD)4. P implant resistance (Rs)5. Gate oxide 1 thickness (tox)6. Gate oxide 2 thickness (tox)7. Field oxide thickness (tox)8. Poly silicon dep thickness (TSI)9. Gate photo critical dimension (CD)

10. Re -oxide 1 oxide thickness (tox)11. P+ diffusion resistance (Rs)12. N+ diffusion resistance (Rs)13. BPSG silicon thickness (SOITH)14. Contact post etch insp. (CD)15. Metal 1 deposition thickness (TM)16. Metal 1 post etch insp. (CD)17. CVD oxide thickness (tox)18. VIA contact post etch insp. (CD)19. Metal 2 deposition thickness (TM)20. Metal 2 post etch insp. (CD)

CMOS I

1. P drive thickness (tox)2. P drive resistance (Rs)3. Active area insp. (CD)4. Poly I deposition (TSI)5. N+ poly resistance (Rs)6. Gate critical dimension (CD)7. P+ resistance (Rs)8. N+ resistance (Rs)9. Boron phosphorus silicon glass

deposition/density (SOITH)

Note: CD = Critical dimensionRs = Sheet RHOSOITH = BPSG thicknessTox = Oxide thicknessTSI = Silicon thicknessTM = Double -level metal

types of analysis (graphical, statistical, orreport writing) or any combination of thethree.

The EA -10 database receives data froma multitude of specialized software pack-ages that collect data from different areas

TEST DATACOLLECTION

MAGTAPE

PARAMETRICDATA (WAT)

(CRTDISPLAY

CIRCUIT PROBETEST

SYSTEMS

/CRTDISPLAY

ENGINEERINGANALYSIS

DATA BASE

ENGINEERINGDATA COLLECTION

ENGINEERINGREPORTS

lc 10-..rWIP

TRACKINGDATA BASE

(3ISPLAY)CRT

OLTLOT TRACKING'

Fig. 2. The EA -10 software is the center of the engineering analysis system.

within the fabrication/test cycle. The IC -10software package contains the WIP data-base, and all data is entered in a manualmode via video terminals throughout fabri-cation and test. This system also has thecapability of capturing data that is not con-sidered work -in -process, but is of an engi-neering nature, as shown in Table I.

At certain steps in the fabrication of awafer, electrical tests are performed and thetest results are passed on to the EA -10database. This collection of test results isdefined and supervised by EN -10. Once thedata has been determined to be legitimateengineering data, it is entered into the IC -10database. The OLT package adds morecapability to IC -10. Information at lowerlevels can be collected to obtain a moredetailed report on work -in -process, andinstructions for each step within the fabrica-tion process can be viewed on the videoterminal by the operator, eliminating anyconfusion or questions on each task to beperformed. The OLT box in Fig. 2 is shownin dotted lines because this software pack-age has not yet been purchased and installed.

The TC-10 software package operatesseparately from the IC -10 database andtransfers data directly to the EA -10 data-base. When each wafer/lot has completedthe fabrication process, electrical tests mustbe performed on each test die, and on the

circuitry of each die for which the wafer hasbeen fabricated (circuit probe). The testdice are used to obtain parametric data thatrelate directly to the fabrication process.This test procedure is called WAT (waferacceptance testing) and depending on thetest results, the decision is made whether tocontinue testing on every die on each waferin the circuit probe area.

The WAT parametric data is stored onthe test system disc and transferred to mag-netic tape on a daily basis. The magnetictape contents are then loaded into the EA -10 database via TC-10 software, whichconverts the test data to the proper EA -10format. Future plans are to connect theWAT test system directly to the EA -10system with a communication link. Thesame philosophy of transferring circuitprobe tests results will be used.

The method used to properly analyzedata and derive concrete conclusions is tocorrelate the present data with valid datathat has been collected over a period of time(historical data), and that resides in thesame database. The engineering analysisspecification for Palm Beach Gardens re-quires a minimum of four months of data tobe present in the EA -10 database. Figure 3shows the amount of data that will be col-lected in each area; you can readily see thelarge amount of data that may possibly be


FABRICATION WAT PARAMETERS PBG TEST

WAFER MOVE INFO

OPERATOR ID

EQUIPMENT ID

1600 LOTS / MO. PERIOD 45 WAFERS

150 DATE ENTRIES 80 DATA ENTRIES

60 DATA ENTRIES

609 DATA ENTRIES

YIELD

BINS

PARAMETRICS

45 WAFERS

1 DATA ENTRY

8 DATA ENTRIES

16 DATA ENTRIES/DICE

X 25 DICE/WAFER

400 DATA ENTRIES/WAFER

FABRICATION ELEC/VISUAL 90 DATA ENTRIES 80 ENTRIES/WAF. 409 ENTRIES/WAFER

TOTAL 4 MONTH 360 ENTRIES/LOT X 45 WAFERS/LOT X 45 WAFERS/LOT

PERIOD X 1600 LOTS 3600 DATA ENTRIES/LOT 18405 DATA ENTRIES

X 1600 LOTS X 1600 LOTS

576,000 DATA ENTRIES 5,760,000 DATA ENTRIES 29,448,000 DATA ENTRIES

GRAND TOTAL OF DATA ENTRIES WITHIN A 4 MONTH PERIOD

ASSUME 10 CHARACTER/ENTRY = 357,840,000

Fig. 3. An example of the analysis data collected in each area.

collected within a four month period. Asthe lot/wafers progress from fabrication toWAT to test, more and more data is col-lected and stored in the database. Over aperiod of four months, close to 36 millionentries to the database may be made.

The Palm Beach Gardens EA -10 engi-neering analysis system is still in the earlystages of collecting all the data that willdirectly correlate to product yield. Thedynamic environment of an integrated cir-cuit manufacturing facility requires thatmany independent parameters be constantlymonitored and the results entered into thedatabase. Procedures for collecting datamanually by fabrication operators are verycritical and must be clearly defined anderror -proof before implementation, andthey must be enforced by setting softwareflags that make entries mandatory. Nor-mally a new procedure is implemented forapproximately one month before making itmandatory; this way, everyone involvedbecomes accustomed to entering the newdata.

Although the ultimate goal is to collectengineering data from each collection pointdescribed in Fig. 3, Palm Beach Gardenshas already benefited from reports derivedfrom data extracted from the present EA -10 database, which does not receive datafrom all of the desired collection points.(Plans are to have all data collection pointsactivated in 1985.) For example, a particu-lar device type was experiencing zero-

35 784,000

1Ig

George Gillespie (left) & Frank McCarty discussing engineering parameters that willbe collected in wafer fabrication.

percent yield, caused by a defective ion -implant set up. The EA -10 analysis reportlocated and isolated defective lots by dateand the shift during which the implant wasmade, allowing for fast corrective action. Inother instances EA -10 has been used toanalyze "what if' situations for determin-

ing specification changes that could improveproduct yield. For example, data wasextracted from the EA -10 database andsorted according to known process varia-tion dates. Thirty-two combinations werereported from the extracted data, eachshowing a correlation of yield versus the


Chuck Palmer (sitting) and Frank McCarty using HP -150 PC to analyze data fromthe EA -10 database.

particular process variation. A simple taskof selecting the best correlation reporthelped determine the process to follow inorder to optimize yield.

This engineering analysis system is not,in the literal sense, a piece of manufacturingequipment. However, because of its poten-tial to provide RCA with a competitiveedge, it should be regarded as one. Thissystem is as much a breakthrough in the

state-of-the-art as are the new diffusionfurnaces or mask aligners.

AcknowledgmentsThe author gratefully acknowledges theefforts of all who assisted in the preparationof this article. Special thanks must go toGeorge Gillespie and Chuck Palmer fortheir advice and guidance.

Frank McCarty is a Member of the Tech-nical staff in the Product EngineeringGroup. He received a BS degree in Com-puter Science in 1977 from Florida AtlanticUniversity. Mr. McCarty joined the PalmBeach Gardens Computer Division in1961 as a technician in the computer testgroup, advancing to Systems Analystdeveloping diagnostic software for theRCA Spectra computers, and as sectionleader of the Customer Systems Accep-tance department before transferring intoa special projects software group in 1971.In 1976, he joined the Solid State Divisionas a test engineer implementing anddesigning ROM and custom automotivedevice test programs, advancing to Sec-tion Manager of the Test EngineeringGroup. His present assignment is organ-izing a new diagnostic software group thatis responsible for collecting all data withinthe IC manufacturing cycle that is perti-nent to engineering yield analysis andstoring the data in a common data base.

Contact him at:Solid State DivisionPalm Beach Gardens, Fla.Tacnet: 722-1219


W. Price

Wafer electrical testingin the factory environment

A factory environment requires high productivity at its auto-mated test facilities. Locally customized software as well ascarefully selected commercial software can provide flexibilityand speed.

Wafer electrical testing (WET), often called wafer acceptancetesting (WAT), is the measurement of certain wafer electricalcharacteristics to determine whether the completed wafer wasprocessed correctly. These characteristics can include sheet re-sistances, betas, junction breakdowns, and other (usually dc)electrical parameters. Typically, these parameters are measured onfive special diagnostic keys on each wafer.

In a factory environment, WET performs three importantfunctions:

1. Quality inspection. Wafers that fail to meet acceptance limitsneed not be sent on to circuit probe.

2. Fast feedback to process engineers. WET quickly measuresmany basic process steps such as sheet resistances.

3. History of process performance. Process engineers can analyzeparametric trends and relate them to process changes.

4. Checks factors that could indicate potential reliability problems.

There are many wafer parameters measured during processing,but WET measurements represent the result of all processing stepsand their complex interactions.

Test system hardware

The Findlay Bipolar fab area uses a Keithley System 300 Para-metric Tester to perform WET. This test system includes:

Abstract: First, the author briefly states the purpose of waferelectrical testing, and lists the test hardware. Then, in moredetail, he describes the software that increases productivity forboth programmers and test equipment operators. Finally, futuresoftware enhancements are discussed that would improve engi-neering use of test data.

(01985 RCA Corporation.Final manuscript received February 4, 1985.Reprint RE -30-2-8

o Voltage supplies: Two Kepko BOP 100-100V, 1A TwoKeithley QDAC - 10V, 12mA Current supplies: Two Keithley 7916-100mA, 100VO Voltage measurement: One Keithley 37615 voltmeter-50uV

to 100Vo Current measurement: One Keithley 35810-2pA to 200mA Capacitance measurement: One Boonton Model 72B-0.1pF

to 3000pFa Frequency measurement: One HP 5345A counter (IEEE

bus)-500MHz National Instruments GP 1 B11V-1 IEEE businterface

Test stations: Three Signitone Model S1007 manual probersO Computer hardware: DEC PDP 11/23 cpu Main memory: 265

kb RAM Disk drives: Four RLO2 drives-10Mb each Tapedrive: One Kennedy Model 9800-800 & 1600 bpi Terminals:Two DEC VT100, Three Lear-Seigler ADM3A Line printer:One Data Products Model 600-600 1pm

Test system software

Much of the software for the System 300 has been written inFindlay to satisfy local needs. In a high volume production en-vironment, high productivity for the WET operator is important,so the operator/computer interface has been optimized. The oper-ator must enter data such as lot name, wafer number, key number,and start test. The computer must indicate wafer quality to theoperator. To increase operator speed, the Findlay interface soft-ware minimizes the number of operator keystrokes without reduc-ing flexibility. This is accomplished by listing the typical answer toeach question asked of the operator. To accept the typical answer,the operater presses the return key. To enter something different,the operator types a different answer before pressing return. Toincrease system programmer productivity, a public domain soft-ware package called FLECS was acquired. FLECS has the effectof adding several structured statements to normal FORTRAN,creating a new, easy to learn structured language. FLECS pro-grams are easier to read and debug, and take less time to write thanstandard FORTRAN programs.

RCA Engineer 30-2 Mar./Apr.1985 47

With well over two hundred test programs written it is alsoimportant to be able to create and change test programs quicklyand easily. To increase test programmer productivity, a test pro-gram generator was written in FLECS. Called "PREPRO," thisgenerator allows programmers to reduce the number of repetitivetasks necessary to create or modify test programs. PREPRO wasdesigned to do the following:

Provide a flexible binning and grading system. Reduce programmer typographical errors by automatically

generating many parameters that would otherwise have to beentered manually.

Make test programs self -documenting so almost anyone canread them.

Provide for fast test program generation and changes.

Here is an excerpt from a typical test program using PREPRO:

C TA9999 PROGRAM& USE PROBE CARD BIMOS PROCESS 21

C

C REV 001 INITIATES PROGRAM

C

C

12/06/82

TO EXECUTE-CELLI

& TEST 1

&NPN 1 5X1 5&BETA& CRIT LOLIMIT HILIMIT IC(mA) VCE(V) IC-CLAMP( V) VCE-CLAMP(mA) DELAY( mS)

T 50 1000 I 2 10 2 10

C

& TEST 2& NPN 1 5X1 5& BETA LOW& CRIT LOLIMIT HILIMIT IC( mA) VCE(V) IC-CLAMP( V) VCE-CLAMP( mA) DELAY( mS)

F 20 1000 I 2 10 2 10

FIN

TO EXECUTE -CONTACTS -CELL I

C

& TEST 900& NPN 1 5X1 5& CONTACT B E

& CRIT LOLIMIT HILIM1T CURRENT( mA) VOLT-CLAMP(V) DELAY( mS)

T -I 14 I 20 4

C

& TEST 901&NPN 1 5X1 5& CONTACT B C

& CRIT LOLIMIT HILIMIT CURRENT( mA) VOLT -CLAMP( v) DELAY( mS)

T -1 14 1 20 4

C

FIN

Notice that the sample test program does not include probenumbers. On a previous test system (C -CAT), many of the typo-graphical errors involved probe numbers. To reduce probenumber typos, a "probe card definition file" is used. A probe carddefinition file consists of a list of device names for each fixed pointprobe card. The advantage is that probe numbers are typed onlyonce for each probe card. Many test programs can use one probecard definition. The sample test program invokes the "BIMOS"probe card definition file with the statement "& USE PROBECARD BIMOS." Here is a sample probe card definition file:

BIMOS PROBE CARD

NPN 1.5X1.5:VRT :

E=12 B.11 C=4E=228.3 C=17

RES B&R I .0 MIL: R+=32 R-=7RES B&R 0.4 MIL: R+=31 R-=7CAP EPI: C+=14 C-=5

PMOS: D-1 G-10 S-8

Another common typographical error in test programs was incor-rect polarities. PREPRO8 automatically supplies the proper

polarity by recognizing that the first part of the device name (NPN,LAT, VRT, PMOS, NMOS, etc.) indicates the polarity to be used.

Binning and grading"Bins" and "grades" appear on the operator's screen to indicatethe general result of the parametric tests being performed. A"bin" is a number that characterizes the quality of a specificdiagnostic key on a wafer. For example, a "BIN 1" may meanthat the key passed certain tests. Normally, default binning isused, where a "BIN 1" means the key passed all critical tests.The critical tests are indicated in the body of the program bythe letter "T" under the word "CRIT," (meaning "True," thistest is CRITical). The non -critical tests are indicated by an "F'(for False). A "grade" is a number, word, or phrase that charac-terizes the quality of the wafer as a whole. For example, awafer that has a certain minimum number of BIN is can bedefined as a grade of "GOOD," an "F 1 ," or even a specialinstruction to the operator like "GIVE TO BILL PRICE."Default grading requires two BIN is for a wafer to have thegrade F1 (meaning "Findlay #1," or good). This default can beoverridden and special binning and grading can be explicitlystated by appending binning and grading statements to a testprogram. For example:

& BIN I ( I D I 1 )

& BIN 2 (2D 1 1 )

&GRADEF1 ( I IDDD )& GRADE FZ ( IT T T T )

& GRADE HOLD FOR B. PRICE (2 T T T T )

&GRADEFS(TTTTT)

Based on C -CAT bin tables, binning is accomplished as follows:

1. The test results of one diagnostic key are compared to theirrespective limits. Each character inside the parenthesis of abin statement corresponds to a parametric test.

2. For one key to match a particular bin, individual test results(such as BETA) must be equal to or less than the limitnumber indicated in the bin table.

3. "D" indicates "don't care"; it matches anything and indicatesthat the test is not "critical"-it is for information only, andnot to be used as pass/fail criteria.

4. "F' indicates "fail."5. "R" is an "OR fail" indicator. For example, BIN 2 (R R R)

would indicate that to match a bin 2, test number 1, 2, or 3must fail.

Example

C

& TEST 1

&NPN I 511 5& BETA& CRIT LOLIMIT HILIMIT IC(mA) VCE(V) IC-CLAMP(V) VCE-CLAMP(mA) DELAY( mS)

T 50 1000 1 2 10 2 10

& LIMIT 2 LOLIMIT HILIMIT120 1080

C

&BIN1 ( 1DFF )& BIN 2 ( 2 D F F )

To match "BIN 1" above, test I (NPN BETA) must pass thefirst set of limits (50, 1000), any result of test 2 (not shown)

48 RCA Engineer 30-2 Mar. /Apr. 1985

will match the "D" (don't care) bin condition, and the thirdand fourth tests (not shown) must fall outside their respectivelimits to match the "Fs". To match "BIN 2," test 2 must matchthe first or second set of limits (50, 1000 or 120, 1080).

Grading enables the test program to tell the operator whetherthe wafer is scrap, good, or any other message desired. Thereare as many characters in the parenthesis as there are diagnostickeys on a wafer (usually five). The characters are checked tosee if they match the bin results for the wafer being tested.

Grading example:& GRADE GOOD (1 1 D D D)& GRADE HOLD FOR B PRICE (1 T T T T)& GRADE SCRAP (T T T T T)

As soon as any two keys on a wafer are "BIN 1," the message"WAFER #n = GOOD" is displayed, and that wafer need notbe tested further ("D" is "don't care"). This tells the operator togo to the next wafer.

If a key has been tested, it matches one "T". If all keys havebeen tested and one key was a "BIN 1," the message"WAFER #n=HOLD FOR B PRICE" is displayed. If all fivekeys have been tested and the first two grades have not beenmatched, the message "WAFER #n = SCRAP" is displayed.

Data archive

The computer also must generate printed reports for test, pro-cess, and type engineers. Since many different engineers usethem, the reports are largely self -documenting. All reports includedevice names, conditions, and limits, so one does not need tosee the test program to interpret a report.

A tape archive system is used to keep wafer data for up tonine months (or longer with the purchase of more tapes). Thistape archive system is useful for type engineers because theymay be asked to investigate a wafer's parametric data after thewafers are shipped to Taiwan, packaged, and have been throughfinal testing. Also, all test program revisions are archived.

Future enhancementsCurrently, there are two types of real-time parametric testreports used: datalogs and histograms (histograms and 100 -daytrend plots are also available in a batch mode from the Some-rville IBM 370). There have been requests for many other typesof report printouts.

We are currently investigating ways that commercially avail-able software can improve the presentation of WET data. Ideal-ly, all reports should be displayed on a CRT screen and option-ally printed. Also, reports should be in a form that can beedited to add additional notes or to do text searches. Thereshould be a capability for ad hoc reports whose format iscreated by non -programmer engineers using a simple menu -d-riven system. An ad hoc report format could be saved for futureuse if desired. Typical reports would include tables, graphs, sta-

Bill Price is a Member of the Technical Staff in Bipolar WaferFab, and is responsible for the operation of the bipolar WET sys-tem. He has a BS in Physics and a BS in Computer Science fromBowling Green State University. He joined RCA in 1979.

Contact him at:RCA Solid State DivisionFindlay, OhioTacnet: 425-1489

tistical functions, X -BAR -R charts, histograms, and trend plots.Besides different formats, a query language or menu is needed.A process engineer should be able to sit at a terminal and getanswers for questions like, "What is the trend of B&R resist-ance for all BIMOS types over the past month?", "What typeshad any scrap today and what were the major failing parame-ters?", "What is the correlation between lateral VCEO and cir-cuit probe yield for type X?", or -What is the variation of npnbeta across the wafer for lot number 98099?". The computermight not be expected to interpret the questions as stated above,but an English -like query language or menu system would beuseful. And perhaps the system could even anticipate problemsand automatically generate an "alarm report" if an X -BAR -Ranalysis indicated that a parameter was drifting for a specifictype.

For wafer electrical testing in a factory environment, increasedproductivity through additional "computer aided yield enhance-ment analysis" is an important next step.

Price: Wafer electrical testing in the factory environment 49

RCA Astro-ElectronicsCelebrates25 Years of Weather Satellites

he first generation of weather satellites,TIROS -1, launched in April 1960, providedcloud pictures that helped to improve theaccuracy of weather forecasts. For the firsttime, forecasters were able to monitorremote areas of the earth. Today, TIROSprovides global coverage four times a dayand is the only source of environmental datafor 80% of the earth not covered by conven-tional means.

The current NOAA series collectsmeteorological data from several hundredlocations around the world on land, in theair, and at sea. These satellites provideimportant meteorological data for theNational Weather Service's daily forecasts.This series of spacecraft provides scientistswith the most comprehensive meteorologicaland environmental information since thestart of the US space program A

TIROS IV

4110TIROS II

4ESSA-3

ESSA-2

141ESSA-1TIROS VII

TIROS VI

TIROS V

4[11TIROS X

TIROS IX


ESSA-9

ESSA-8

ESSA-7

IIESSA-6

-1/1-ESSA-5

ESSA-4

NOAH -3WilPF-

14

-1111pill-0A -A-2 - -

ITOS 1

NOAA-1

Although its primary mission, TIROSis not limited to meteorological datagathering. A search and rescue (SAR)system was added to the AdvancedTIROS -N, launched in April 1983, toprovide a relay point to help locate downedaircraft and ships in distress. The success ofthe SAR system is but one illustration of thegrowth potential and broad spectrum ofmissions of the TIROS spacecraft A

TIROS -NNOAA-7

114111411111NOAH -8

111111111411NOAA-9

IIII

IIIIIIIIII

1,111111111,11111

Astro - Electronics


Patents

Astro-ElectronicsCallen, P. J.Satellite dual bus power system -4494063

Broadcast SystemsDivision

Hamalainen, K. J./Reitmeier, G. A.Television signal standards conversionusing a helical scan VTR -4500930

Lovick, R. B./Firestone, W. L.Television descramble with security plughaving folded flexible printed circuit boardproviding tier tag memory -4494143

Schmitz, A. N./Clark, R. N.Audio-visual diplexed television transmitterin which the aural signal can be multiplexedwithout switching -4491871

Consumer ElectronicsDivision

Deiss, M. S.Remote controlled receiver with provisionsfor automatically programming a channelskip list -4495654

Duvall, W. E./Hwang, M. P.Television receiver standby powersupply -4500923

Filiman, P. D.Signal sampling network with reduced offseterror -4502079

Hermeling, Jr., G. C./Muterspaugh, M. W.Double conversion tuner for broadcast andcable television channels -4499602

Lea, J. G./Carlson, D. J.Variable frequency U.H.F. local oscillator fortelevision receiver -4494081

Luz, D. W./Willis, D. H.Single controllable switch, push-pull inverterfor a television receiver ferroresonant powersupply -4492900

Maimpally, S. V./Tallant, 2nd, J. C.Wideband kinescope driveramplifier -4494146

Government CommunicationsSystems

Coyle, P. J.Protective cartridge for discrecord -4499996

Government Systems Division

Siryj, B. W./ Lazzery, A.G.Automatic handling mechanism for an opti-cal disc enclosed in a protective cartridge-4502133

Missile and Surface Radar

Forquer, T. J./Li, H.Multiprocessor -memory data transfernetwork -4491915

Schwarzmann, A.Method and apparatus for neutron radiationmonitoring -4498007

Schwarzmann, A.Folded dipole radiating element -4498085

RCA Laboratories

Altman, T. N.Binary drive circuitry for matrix -addressedliquid crystal display

Aschwanden, F.Digital sync separator -4491870

Aschwanden, F.Slow genlock circuit -4498103

Bernard, F. S./Eliscu, S. M./Batterman, E. P.Apparatus for generating scaled weightingcoefficients for sampled datafilters -4494214

Bolger, T. V.FIR chrominance bandpass sampled data fil-ter with internal decimation -4500912

Bunting, R. M./Acampora, A.Apparatus for frame -to -frame comb filteringcomposite TV signal -4498100

Cartwright, Jr., J. M.Programmable logic gates andnetworks -4495427

Dholakia, A. RPickup cartridge having improved stylusflylead-4502135

Dischert, R. A./Topper, R. J.Television gamma corrector with symmetri-cal response about black -level -4499494

Dischert, W. A.Video disc player having carriage drivemechanism -4493070

Faraone, L.Method of making semiconductor devicewith multi -levels of polycrystalline siliconconductors -4494301

Ham, W. E.Process for forming an improved silicon -on -sapphire device -4496418

Hammer, J. M./Neil, C. C.Microtranslator and microtranslatorassembly -4495704

Harada, S./Tosima, S.Method for characterizing soldercompositions -4491412

Hawrylo, F. Z.Method of soldering a light emitting deviceto a substrate -4491264

Hinn, W./Fecht, H. R.Noise suppressing Interface circuit in akinescope bias control system -4502073

Jastrzebski, L. L./Lagowski, J.Method to determine the crystalline proper-ties of an interface of two materials by anoptical technique -4498772

Johnston, L. B.System for segmentally refreshing the storedelectron gun drive voltages of a flat paneldisplay device -4500815

Levine, P. A.Compensation against field shading in videofrom field -transfer CCD imagers -4495982

Levine, P. A.CCD imager with improved low light levelresponse -4499497

Miller, E. A.Distributor tube for CVD reactor -4499853

Pike, W. S.Diode simulator circuit -4500798

Pritchard, D. H.Apparatus for frame -to -frame comb filteringcomposite TV signal -4498099

Reitmeier, G. A.Digital television signal processingsystem -4502074

Roach, W. RStylus Manufacturing apparatus andmethod -4490945

Southgate, P. D./Fairbanks, D. W./Davis, R.B./Beltz, J. P.Automatic stripe width reader -4498779

Theriault, G. E.Terminated switch -4492937

White, A. E./Coleman, D. E./Miller, S. R.Statistical teaching apparatus -4493651

White, L. K.Method for detecting distance deviations to


a photoresist surface in an opticalprinter -4498775

SelectaVisionKelleher, K. C/Kiser, N. J./Christopher, T. J.DC motor servo system -4494052

McNeely, R. K.Stylus arm insertion apparatus -4501063

Turner, R. L.Video disc package -4499995

Wierschke, D. J.Method for the manufacture of recordstampers-4500393

Solid State Division

Bismarck, 0. H.Coincident pulse cancellingcircuit -4502014

Crawshaw, D. D.Field -transfer CCD imagers with reference -black -level generation capability -4498105

Gentile, C. J./Hagge, M. L./Croes, R. C.Level shift interface circuit -4501978

Harwood, L. A.Hue control system -4500910

Hoover, M. V.FET negative resistance circuits -4491807

Keller, R F.Magnetron filament having a quadrilateralcross -section -4494034

Steckler, S. A./Balaban, A. R.Digital television receivers -4502078

Yamazaki, T./Faltas, M./Webb, P. P.Silicon photodiode with N -type controllayer -4499483

Video Component andDisplay Division

Baran, A. S.Stencilling a unique machine-readablemarking on each of a plurality ofworkpieces-4497848

Pen and Podium

D'Amato, R. J.Arc suppression structure for an electrongun -4491764

Deyer, C. E.System for converting the frequency of apulse train to a binary number -4499588

McCandless, H. E.Multibeam electron gun with compositeelectrode having plurality of separate metalplates -4500808

Piascinski, J. J./Axelrod, R. H./Mount, J.Method for combined baking -out and panel -sealing of a partially -assembledCRT -4493668

Wilbur, Jr., L. P./Vanrenssen, M.Shadow mask washer/spring weldingapparatus -4500767

Recent RCA technical papers and presentations

To obtain copies of papers. check your library or contact the author or divisionalTechnical Publications Administrator (listed on back cover) for a reprint.

Advanced TechnologyLaboratoriesG. Ammon/J. CalabriaOperational performance of optical disk sys-tems-Presented at the Technical Symposiumon Optical and Electro-Optic Engineering, LosAngeles, Ca. (1/85)

V. J. BenokraitisA one-on-one hit avoidance model-Model-ing and Simulation, Vol. 15, Part 2, pp. 727-733 (1/85)

G. ClaffieHigh performance optical disk jukebox -Presented at the SPIE Third InternationalConference on Optical Mass Data Storage,Los Angeles, Ca. (11/85)

G. ClaffieOptical mass storage systems-Presented atthe Rendevous and Proximity Workshop atthe Johnson Space Center. Houston, Tex.(2/85)

A. FellerHow to buy or build custom LSI devicesusing automated design techniques -Presented at GOMAC 84, Las Vegas, Nev-ada, and published in the Proceedings(11/84)

W. F. GehweilerMultiprocessor systems and a system levelsimulator-Presented at the IEEE Conference,Ft. Huachuka, Ariz. (1/85)

R. G. HackenbertParsing natural language on a microcompu-ter-Presented at the Calico Symposium,Baltimore, Md. (2/85)

H. W. KaiserRCA CMOS/SOS rad hard technology stat-us-Presented at SDI Space Radar Discrimi-nation Conference, Boston, Mass. (12/84)

R. PutatundaAutodelay: A second generation automaticdelay calculation program for LSI/VLSI chips -Presented at the International Conference onCAD, Santa Clara, Ca., and published in theProceedings (11/84)

R. H. SchellackThe GaAs quick chip: A high-speed cell arrayfor both analog and digital applications-EDN, Issue 23 (11/11/84)

D. C. Smith/ R. Noto /J. C. Werbickas/G.Powell/S. SharmaGVAUA and ATLAUA: A total gate arraydesign capability-Presented at GOMAC 84,Las Vegas. Nevada, and also at the ICCAD

Conference, Santa Clara, Ca., and publishedin the Proceedings (11/84)

L. E. Toombs/W. B. SchamingMultifeature methods for target detection-RCA Engineer, Vol. 29, No. 6, pp. 56-60 (Nov/Dec 1984)

J. R. Tower/B. M. McCarthy/R. T. Strong/L.F. PellonDevelopment of multispectral detector tech-nology-RCA Engineer, Vol. 29, No. 6, pp.

48-55 (Nov/Dec 1984)

J. S. Zapriala /J. A. Gaev/N. StraguzziAl applications in future military systems-Presented at GOMAC 84, Las Vegas, Nev.,and published in the Proceedings (11/84)

Astro-ElectronicsD. Chu/G. ClarkStructural dynamic modification using modalanalysis data-Presented at the 3rd Interna-tional Modal Analysis Conference, Orlando,Fl. (1/85)

D Chu/C. TrundleReanalysis techniques used to improve localuncertainties in modal analysis-Presented


at the 3rd International Modal Analysis Con-ference, Orlando, Fl. (1/85)

C. HubertComputer -aided stability analysis of spinningspacecraft with moving parts-Presented atthe Rutgers Mechanical & Aerospace Engi-neering Colloquium, New Brunswick, N.J.(2/85)

J. C. LograndoEvaluation of high voltage multilayer ceramiccapacitors for spacecraft power supplies-Presented at the 1985 High Voltage Work-shop, Monterey, Ca.(2/85)

L. O'Hara/A. Rosenberg/J. SrogaGround based 0.53 pm wind sensor-Pres-ented at the Topical Meeting on OpticalRemote Sensing of the Atmosphere, InclineVillage, Nev. (1/85)

K. W. SchmidtBridging the generation gap: The sigma -3computer upgrade program-Presented at theTeleXchange 6th International Meeting,Newport Beach, Ca. (1/85)

D. SolomonCovariance matrix for a -b -y filtering-lEETransactions on Aerospace and ElectronicSystems (1/85)

Automated Systems

L. Arlan/E. H. MillerInteractive color graphics support to intelli-gence analysis-Presented at the VerdugoChapter, Association of Old Crows, CanogaPark, Ca. (2/85)

L. R. Armstrong/P. Berrett/E. G. ZablockiDiesel engine power prognostics-Pre-sented at the SAE International Congressand Exposition, Detroit, Mich. (2/85)

R. E. HartwellArtificial intelligence applied to diagnos-

tics-Presented at the SAE InternationalCongress and Exposition, Detroit, Mich.(2/85)

Government CommunicationsSystems

H. R. Barton, Jr.Predicting guaranty support using learningcurves-Presented at the Reliability andMaintainability Symposium, Philadelphia, Pa.and published in the Proceedings (1/85)

RCA Laboratories

W. A. Bbsenberg/C. W. Magee/E. M. BotnickChlorine content in dry and wet MOS gateoxides-J. of the Electrochem. Soc. 131,2397 (1984)

J. B. Clegg/A. E. Morgan/H. A. M. DeGrafteF. Simondet/A. Huber/G. Blackmore/M. G.Dowsett/D. E. Sykes/C. W. Magee/V. R.DelineA comparative study of SIMS depth profilingof boron in silicon-Surface Interface Analy-sis, 6, 162 (1984)

F. J. Feigl/R. Gale/H. Chew/C. W. Magee/D.R. YoungCurrent -induced hydrogen migration andinterface trap generation in aluminum -silicondioxide -silicon capacitors-Nucl. lnstum.Meth. Phys. Res. B1, 348 (1984)

C. W. MageeOn the use of secondary ion mass spec-trometry in semiconductor device materialsand process development-Ultramicroscopy14, 55 (1984)

C. W. Magee/E. M. BotnickThe use of secondary ion mass spectrometryin semiconductor device materials and pro-cess development-RCA Engineer, Vol. 29,No. 5 (Sept/Oct 1984)

C. W. MageeSecondary ion mass spectrometer designconsiderations for inorganic and organicanalyses-3M/NSF Sponsored Symposiumin SIMS and FAB, St. Paul, Minn. (10/84)

C. W. MageeAnalysis of amorphous silicon photovoltaicmaterial by secondary ion mass spectrome-try-Invited presentation in a Symposium onAnalysis of Ultrapure Materials, Eastern Ana-lytical Symposium, New York City, N.Y. (11 /84)

C. W. MageeMaterials characterization using ion beams -Invited seminar at Kodak Research Labo-ratory Rochester, N.Y. (11/84)

L. K. WhiteApproximating spun -on, thin film planariza-tion properties on complex topography -Journal of Electrochemical Society, 132 (1),168 (1985)

Missile and Surface Radar

W. A. MulleA distributed microcomputer architecture oftactical systems-Presented at the Electron-ics for National Security Asia Conference,Singapore (1/85)

Service CompanyR. C. BryantClosed circuit television in security-Pre-sented at the Philadelphia Chapter of theAmerican Society for Industrial SecuritySeminar (3/85)

R. L. LaytonOffice communications; requirements andsolutions-Presented at the UNIX Users Con-ference, Dallas, Tex. (2/85)


Engineering News and Highlights

Hearn named CEEAdministrator

Tony Hearn joined the RCA Corporate Engi-neering Education group (CEE) in January1985 as Administrator, Engineering Educa-tion programs. For the past three years he hastaught full time in the areas of digital electron-ics, microprocessors, industrial process tech-nology, and finance at Lyons Technical Insti-tute, Philadelphia Community College, and LaSalle University. He has 15 years of circuit andsystem design experience in color television,government satellite systems, and commer-cial computer systems. Mr. Hearn receivedBSEE and MSEE degrees from Drexel Univer-sity, and holds an MBA with a major inFinance from La Salle University.

Engineering CorporateComputer Center opens

The Engineering Corporate Computer Center(ECCC) became operational on January 31,1985. The facility is owned and operated byCorporate Information Systems and Services(CISS), but is managed in conjunction with theparticipating business units.

The primary purpose of this new center is toprovide support in shortening the overalldesign cycle for engineering. With user -sup-ported software, designers will be able to takeadvantage of the 10 -to -1 reduction in through-

put time over their local minicomputers. TheECCC will be the repository for code used inelectrical, thermal, and mechanical designs.Other applications will be added as necessary.

The ECCC is designed to be an additionalcomputing resource for the participating RCAbusiness units. Specifically, it comprises anIBM 3083J unit, which runs the IBM VM oper-ating system in a batch mode. To gain accessto the system, users will submit jobs eitherthrough their local VAX terminals or throughthe VM system at Cherry Hill. Using an Inter -link 3711, the VAX -submitted jobs will be firsttranslated to an acceptable IBM format andthen processed on the IBM mainframe.

Initially, the business units participating inthe ECCC are Astro-Electronics, Missile andSurface Radar, Advanced Technology Labor-atories, Automated Systems Division, Govern-ment Communications Systems, Solid StateTechnology Center, Government Systems Divi-sion staff, and RCA Laboratories. Engineersand programmers at any of these units areurged to contact their business unit ECCCrepresentative if they require additional infor-mation, or call Tacnet 253-6638 for the nameof their local representative.

The ECCC is currently supported by twogroups: the Management Committee, and theMajor Operating Unit User Committee. Thefirst group comprises one member selectedfrom each participating ECCC unit. Commit-tee members have a direct vote in resolvingmajor issues and deciding the future direc-tions of the ECCC facility. Overall, however,the Management Committee is responsiblefor establishing policies regarding softwareacquisitions, hardware changes, and operat-ing strategies.

The second group-the Major OperatingUnit User Committee-has during the pastyear evolved into a gathering of individualsrepresenting ECCC participants at the userlevel. Most of these committee members areMOU ECCC contacts, and they meet at leastonce every three weeks to discuss additionsor changes to the communications configura-tion, new software installations, standards,and usage problems.

As the need for additional computing re-sources is discovered, the ECCC system willbe re-evaluated.

Ed. Note: There will be an article in theJuly/August issue of RCA Engineer describ-ing the evolution of the ECCC and how thefacility functions.

Professional activities

Schmidt named AssociateFellow of AIAACharles A. Schmidt, Division Vice Presidentand General Manager of Astro-Electronics,has been elected an Associate Fellow of theAmerican Institute of Aeronautics and Astro-nautics (AIAA). Mr. Schmidt has been withRCA for 34 years.

Two at VCDD receive degreesRaymond E. Keller, a senior technician in theProduct Development group at VCDD, Scran-ton, recently received a Bachelor of Profes-sional Studies degree with a major in Mechan-ical Engineering from Elizabethtown College,Elizabethtown, Pa.

Nicholas J. Spryn, a drafter/designer inEquipment Engineering at the Scranton plant,received a Bachelor of Professional Studiesdegree with a major in Electrical Engineeringfrom Elizabethtown College. (More -)

Obituary

Meade BrunetMeade Brunet, former Vice President andManaging Director of the RCA InternationalDivision, died on February 10 at the age of 90.Mr. Brunet retired from RCA in 1966 after 44years of service. He joined RCA in 1922, andwas assigned to the sales department. From1923 to 1925 he was RCA District Manager inChicago, Ill. Subsequent promotions led to hisappointment as Manager of the EngineeringProducts Department, and he later becameVice President of the RCA ManufacturingCompany.

From 1939 to 1946, in addition to his otherduties, Mr. Brunet was in charge of the Wash-ington Sales Office, and was subsequentlyelected a Vice President of RCA. In 1946 hebecame Vice President and Managing Direc-tor, RCA International Division, and in 1957 hewas made Staff Vice President in the Salesand Services organization of RCA. During1960, he was assigned abroad for the elec-tronic development program in southern Italy.


Yost is IEEE Centennial Young Engineer

Thomas D. Yost, Manager, Audio Circuit De-sign, Consumer Electronics (Indianapolis) hasbeen named a Centennial Young Engineer bythe Institute of Electrical and Electronics Engi-neers (IEEE). Cited by the IEEE ConsumerElectronics Society, Mr. Yost received a "Cen-tennial Key to the Future" from IEEE PresidentRichard J. Gowen.

The "Keys to the Future" were presented to34 individuals representing the Institute's 33technical societies. Each recipient was identi-fied as an individual in the early stages of hisor her career "who best demonstrates soundunderstanding of the evolving technologies"in the individual's chosen field, and whose"progress shows the greatest promise forapplying these technologies toward the deve-lopment of new industrial products and sys-tems for the improvement of society."

The keys were laser -cut from a three-inchsilicon disk composed of metal oxide semi-conductor material.

Left to right: Dr, Richard J. Gowen, 1984 IEEE President; Thomas D. Yost; Dr.Stephen Kahne, IEEE 1985 Vice President, Technical Activities.

Technical excellence

Two new TECs formedThe Video Component and Display Division atCircleville, Ohio and RCA Service Company atSpringfield, Virginia recently formed their ownTechnical Excellence Committees.

Springfield is a Government Services loca-tion of RCA Service Company. Organizationalplanning for its new TEC was conducted forabout six months prior to installation. Thecharter was developed and approved, and thefirst set of committee members was selected.The first meeting was held on October 10,1984.

The VCDD TEC at Circleville was formed onNovember 7, 1984.1t has seven voting membersand two advisory members representing man-agement and Employee Relations.

Kearney wins Astro EEC Award

Chris Kearney has been presented with theEngineering Excellence Award for his innova-tive and expeditious design of the AttitudeLogic Processor (ALP) firmware for the RCASatcom H satellite. Analysis of on -orbit teleme-try from Satcom G in late May 1983 indicatedthe possibility of realizing a significant im-provement in the performance of the attitudecontrol system. As a result, new attitude require-

ments were imposed on the Satcom H AttitudeLogic Processor firmware.

Mr. Kearney assisted in the analysis of theSatcom G telemetry and provided importanthelp in the selection of the improved design forSatcom H, and was the lead engineer in theproduction of the revised ALP package. Withinrigid and demanding scheduling constraints,he designed and delivered the code. Hisinsight and diligent effort were instrumental inthe testing, modification, and final certificationof the ALP firmware. As a result of this extraor-dinary effort, Satcom H was launched onschedule and has been meeting or exceedingall mission attitude requirements since launch.

Astro Engineering ExcellenceTeam Award

Lawrence Slivinski, James Sturges, and Jial-ing Yang have won the Astro-ElectronicsEngineering Excellence Team Award for theiranalytical contributions in support of the DMSPS-9 spacecraft modal test and loads verifica-tion program. They were responsible for deve-loping and adjusting the finite element modelof the spacecraft, for pre-test analytical sup-port for the structure test group, and for real-time analysis of the modal test data during the

course of the test. To accomplish these tasks,new software programs were developed thatwere essential to the successful completion ofthe test and the final verification launch loadsanalysis. New software, implementing ad-vanced structural dynamics mode synthesistechniques, was developed in order to analyti-cally remove the effects of a solar array masssimulator, while adding the effects of the ana-lytical solar array finite element model to theexperimental spacecraft modal model.

Division -wide SSD award toParkerKen Parker, a member of Findlay's EquipmentTechnology Group, has been named as therecipient of this year's Solid State DivisionTechnical Excellence Award. He was selectedfrom a field of all Technical Excellence Awardwinners in SSD. The Division Award consistsof an engraved bowl and a cash award.

Marion Technical ExcellenceAwardJerry Hotmire, Quality Control Engineer atVCDD Marion, has been awarded the fourthquarter Technical Excellence Award. He was


selected for developing, establishing, makingoperational, and updating the HP -1000 Pro-cess Quality Computer System. This systemhas enabled engineering to maintain tight con-trol of matrix opening sizes.

Mehling wins MSR annualaward

Thomas H. Mehling has won the MSR AnnualTechnical Excellence Award for 1984. He washonored for outstanding contributions to AEGISCombat System readiness and operationalexcellence. His services were specifically re-quested during March and April 1984 to assistin preparations for a special post -deploymentoperational test designed to challenge USSTiconderoga's air defense capabilities. Hisability to diagnose subtle and unusual pro-blems and provide instantaneous solutionswas a major factor in the extraordinary perfor-mance levels achieved.

During this period he operated virtuallyalone, relying on his ability and backgroundto correct deficiencies. On a number of oc-casions he made computer program changesin a matter of hours that others estimated interms of man -months. His habit of verifyinghis work by exhaustive testing contributessignificantly to the immediate customer ac-ceptance of his solutions to problems.

As the winner of the annual award, Tomwill receive a special plaque honoring his ac-complishments, a text or reference of hischoice, and an extended weekend vacation.

MSR third quarter awardsThere were five winners of the 1984 third quar-ter Technical Excellence Awards in MSR,Moorestown, N.J.:Pradeep K. Agrawal, for conceiving a specialtechnique to overcome the need for extremeposition precision in near -field antenna test-ing. The approach uses a laser system todetermine probe displacement from a perfectmeasurement grid to provide the basis forphase adjustments. Dr. Agrawal's "k -vector"method simplifies computation of scannerpositioning error compensation, thereby relax-ing mechanical requirements for the extremelyaccurate ANFAST II measurement system.Daniel L. Friedman, for his innovative solutionto a potentially serious problem in a class ofvertically launched SM-2 / Block II missiles.The obvious solution, requiring missile designchanges and significant computer programchanges, would have involved extensive, costlydelays. Mr. Friedman's alternative solutioninvolved a simple parameter change in thecomputer program to avoid the conditionsunder which the problem could occur, provid-ing efficient and timely resolution of the problem.Seth R. Putney, for his systems engineeringrole in the design and development of theFAA's Request for Proposal for the Air Traffic

Left to right: Fred I. Palmer, Chief Engineer; Thomas H. Mehling; James B. Feller,Division Vice President, Engineering, Government Systems Division.

Seated (left to right): Obrey B. Smith; James B. Feller, Division Vice President, Engineering,Government Systems Division; Thomas H. Mehling; Fred I. Palmer, Chief Engineer; RichardRabbitz. Standing (left to right): Seth R. Putney, Ralph L. Stegall, Frank J. Reiffer, Daniel L.Friedman, Michael S. Perry, Leonard H. Yorinks, Joseph P. Pryzbylkowski, William J.Graham, Stanley M. Yuen. Absent: Pradeep K. Agrawal, Daniel J. Wawrzyniak.

Control Host Computer System. Mr. Putney'stechnical guidance provided a systematic andconsistent approach to technical input anddocumentation. His efforts have contributedsignificantly to the FAA's Advanced Automa-tion Project and to RCA's technical reputation.Ralph L. Stegall, for exceptional technicalaccomplishment in successfully interpretingcustomer requirements and defining a systemfor the Multiple Object Tracking Radar. As leadsystems engineer for the program, he definedthe radar architecture, including the array andsoftware subsystems. As the principal techni-cal interlace with the customer, he was re-

sponsible for selling the MSR concepts. Theresult is a new MSR product line with signifi-cant long-term business potential.Leonard H. Yorinks, for special contributionsto the achievement of ANFAST II operationalcapability. Dr. Yorinks developed calibrationand alignment techniques for the rf receiver aswell as test procedures to validate the calibra-tion. He devised a series of experiments thatresolved discrepancies between reported andanticipated data, and specified correctiveaction. His contributions to the identificationand resolution of beam -pointing computerprogram deficiencies were especially valuable.


Fourth quarter MSR awards

Graham Perry

There were four winners of the fourth quarterMSR Technical Excellence Awards:William J. Graham, for outstanding contribu-tions to the Multiple Object Tracking Radar(MOTR) antenna design. When it becameapparent that his original reflectarray designwould not support all the MOTR marketingtargets, Dr. Graham quickly shifted to a trans-mission lens array design. The computer -aided design tools he developed allowed himto rapidly perform the required tradeoffs andachieve an optimized design that meets allMOTR requirements.Michael S. Perry, for successfully developinga new design for a 7 -bit precision ferrite phaseshifter for the Modular Advanced TacticalRadar. In addition to his development effort, hecoordinated a pilot production run, set up aproduction test program, and conducted high -power tests at a vendor plant. The result is aproduction -ready design for a precision C -band phase shifter suitable for low-sidelobephased arrays.

Obrey B. Smith, for his leadership and per-sonal performance in the design, develop-ment, and test and evaluation of the New Zea-land R76C5 fire control system. In addition toleading the hardware development team, healso contributed significantly to the successfulfactory acceptance tests of the first system.His technical direction and personal designcontributions were a key element in the suc-cessful completion of the R76C5 developmentprogram.Stanley M. Yuen, for developing a new tech-nique of highly accurate, unambiguous, dopplerdiscrimination of low cross-section targetsusing minimal radar dwell time. His spectralestimation algorithm-compatible with AEGISsystem requirements-affords the rapid threatdetection necessary for protection againstclose -in missile threats. Mr. Yuen's solution tothis previously unresolved problem was suc-cessfully demonstrated by computer simula-tion using realistic air defense system para-meters.

Astro-Electronics hosts computer symposium

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On March 14, 1985 an RCA corporate sym-posium on "Special Uses of Computers inEngineering" was held at Astro-Electronics,Hightstown, N.J. The co-chairmen were JamesP. Layton and Lawrence C. Scholz. Therewere 90 attendees representing 14 RCA busi-

ness units: Astro-Electronics, Corporate Staff,Automated Systems, Government Systems Divi-sion, RCA Service Company, RCA Records,Government Communications Division, Amen -corn, RCA Laboratories, the Frequency Bu-reau, Missile and Surface Radar, Solid StateDivision, Consumer Electronics Division, andCorporate Engineering Education.Robert Miller, Chief Engineer, Astro-Electron-ics was the first of ten speakers, and at theend of the day he felt that the symposium"provided a very worthwhile interchange be-tween our groups at RCA who are usingcomputers to improve engineering productiv-ity. I think we should encourage frequent inter-changes among our working level people onthis subject. I heard one of the participantssay that 'fifteen minutes of this meeting hassaved me three weeks of work in developinga software package.' "

The day's activities included a tour of Astro-Electronics and a microcomputer demonstra-tion.

Papers presented:

Use of computers in space engineering

R. Miller

In order to maintain its competitive position,Astro has been a leader in using computersin space and on the ground to achieve engi-neering productivity improvement. This spansthe areas of design, test, in -orbit control, andoperations.

Benefits of computer aided spacecraft design

Nelson F. Samhammer

Computer aided design and drafting (CADD),which has been available at a lower level ofcapability for years, has become available ata level of sophistication and cost effective-ness useful in the area of mechanical design.Early in 1984, we began our search for sucha system to satisfy our needs. Ultimately, ourselection process led us to the system thathas been in operation at Astro since January1983: PRIME MEDUSA.

Times, Terminal Interactive Menu ExecutiveSystem

Jerry Golub

Menu input, which is popular for many tran-saction systems, is an attractive alternative tothe current methods of input preparation forscientific and engineering programs. TIMES,a program to develop a menu input capabil-ity, has been written and successfully app-lied to two graphics programs and a NavalBattle Group simulation.

On -board spacecraft computers

Steven Teitelbaum

The space environment places constraintson computer design such as low power con-sumption, low weight, high reliability, andsmall production quantities. These constraintshave a dramatic effect on the physical and


performance characteristics of present dayspacecraft machines.

Computer aided microwave engineering

Dr. Barry S. Perlman

Computer -aided engineering (CAE) has per-mitted the microwave engineer to gain morefunctionality and benefit with increased pro-ductivity. For the microwave engineer, CAEincludes computer -aided design (CAD) of cir-cuits and devices, performance simulation,analysis and optimization, CAD for physicallayout, prototype evaluation, and automatedtesting.

Intelligent man -machine interface for satel-lite control

R. H. Harten

The volume and complexity of telemetry infor-mation make it increasingly difficult for oper-ators to notice and respond to abnormal space-craft conditions. Current systems typically usea series of telemetry limit checks and alarmsto monitor and signal abnormal conditions.

Astro's Intelligent Man -Machine Interface pro-ject was initiated to explore ways of solvingthis growing problem.

VLSI semi -custom chip design by computer

Gary Gendel

A system for the automated design of anintegrated circuit in use by RCA Solid StateDivision is based on a collection of varioussoftware tools that perform various tasks ofIC design, driven by a single program calledFASTRACK. This synergy produces rapid turn-around in design cycles and dramatically re-duces development costs while insuring avery high probability of first-time success.

Computer -aided experimental structuralanalysis

C. Voorhees

Experimental structural analysis is anotherhighly specialized area in the field of engi-neering that is a product of the computerrevolution. With the discovery of the Fast Fou-

rier Transform in 1965, FFT analyzers andcomputer -based structural analysis systemssoon followed.

Computer -aided manufacturing at RCA Labs

Keith S. Reid -Green

In a corporate model shop, accuracy may beas important as repeatability. Computerizednumerical control (CNC) may represent a wayto make those parts that are unusually diffi-cult to make manually. Fast turnaround is asmuch an issue here as anywhere else-anengineer waiting for a part is a source ofwasted money.

The Engineering Corporate Computer Center

Dr. Ronald A. Andrews

The Engineering Corporate Computer Center(ECCC) is currently in operation. First pro-duction was in January. The managementand operation staff are in place. Experienceto date suggests the ECCC will meet theexpectations of the user organizations.

RCA Engineer 30-2 Mar. / Apr. 1985

Want to write for the gi

RCA Engineer?Need some tips?

ftOur author's guide gets right to the point . ..AIf you are writing an articlefor the RCA Engineer'smultidisciplinary engineer-ing audience, the 48 -page "Guide for RCAEngineer Authors" canshow you practical waysto attract and maintainreader interest. The mate-rial specifically applies to

RCA users. Experiencedand novice authors canuse many of the univer-sally applicable principles,methods, and examplesgiven here. Each chapterpresents a series of Pre-mises, Goals, andMethods that lead youthrough the writing effort.

The first chapter, "ArticleMechanics & Specifica-tions," defines the parts ofa complete article pack-age. The second chapter,"Article Content," con-tains idea starters that willhelp you to gather the

right information and art-work, organize the mate-rial, establish and keepaudience interest, andwrite for the reader. Thethird chapter, "WritingStyle," illustrates by exam-ple the five major ways toimprove written expres-sions by making themactive, lean, clearly quali-fied, symmetric, andspecific.

Send your request for afree copy of the "Guidefor RCA Engineer Authors"to the RCA EngineerMagazine, TechnicalExcellence Center, 13 Ros-zel Road, P.O. Box 432,Princeton, NJ 08540-0432.Call Tacnet: 226-3090.

RCA Engineer 30-2 Mar. / Apr. 1985

Editorial RepresentativesContact your Editorial Representative at the Tacnetnumbers listed below to schedule technical papersand announce your professional activities.

Broadcast Systems Division (BSD) Tacnet*Harry Green Gibbsboro, New Jersey 266-3791

Consumer Electronics (CE)

*Eugene JansonJohn HopkinsLarry Olson

Indianapolis, IndianaIndianapolis, IndianaIndianapolis, Indiana

422-5208422-5217422-5117

Corporate Information Systems & Services

Sue Handman Cherry Hill, New Jersey 222-6242

Corporate Technology

*Tony Bianculli Princeton, New Jersey 226-2111

Government Systems Division (GSD)

Advanced Technology Laboratories*Merle PietzEd Master

Astro-Electronics*Frank YannottiCarol Coleman

Automated Systems*Dave Wellinger

Dale Sherman

Camden, New Jersey 222-2161Camden, New Jersey 222-2731

Princeton, New Jersey 229-2544Princeton, New Jersey 229-2919

Burlington, Massachusetts 326-3435Burlington, Massachusetts 326-3403

Government Communications Systems*Dan Tannenbaum Camden, New Jersey 222-3081GSD Staff

*Susan Suchy Solid State Tectlnology CenterSomerville, New Jersey 325-7492

Missile and Surface Radar*Don HiggsGraham BooseJack Friedman

Moorestown, New JerseyMoorestown, New JerseyMoorestown, New Jersey

National Broadcasting Company (NBC)

224-2836253-6062224-2112

"Bob Mausler New York, New York 324-4869

New Products Division

*Art Sweet Lancaster, Pennsylvania 227-6878Bob McIntyre Ste Anne de Bellevue 514-457-9000

Patent Operations

George Haas Princeton, New Jersey 226-2888

RCA Communications Tacnet

American Communications*Carlton ThomasCarolyn Powell

Global Communications*Dorothy UngerNetwork ServicesBill Brown

RCA Laboratories

Eva Dukes

RCA Records

*Greg Bogantz

Princeton, New Jersey 272-4192Princeton, New Jersey 258-4194

Piscataway, New Jersey 335-4358

Princeton, New Jersey 272-7601

Princeton, New Jersey 226-2882

Indianapolis, Indiana 424-6141

RCA Service Company

*Murray KaminskyDick DombroskyRay MacWilliams

Cherry Hill, New JerseyCherry Hill, New JerseyCherry Hill, New Jersey

"SelectaVision" VideoDisc Operations*Harry Anderson

222-6247222-4414222-5986

Indianapolis, Indiana 426-3178

Solid State Division (SSD)

*John SchoenPower DevicesHarold Ronan

Integrated CircuitsDick MoreySy SilversteinJohn Young

Somerville, New Jersey 325-6467

Mountaintop, Pennsylvania 327-1473or 327-1264

Palm Beach Gardens, Florida 722-1262Somerville, New Jersey 325-6168

Findlay, Ohio 425-1307

Video Component and Display Division

*Ed MadenfordLou DiMattioNick MeenaJ.R. Reece

Lancaster, PennsylvaniaScranton, Pennsylvania

Circleville, OhioMarion, Indiana

227-6444329-1435432-1228427-5566

*Technical Publications Administrators, responsible for review and approvalof papers and presentations, are indicated here with asterisks before their names.

21 MAR 1985

RCA EngineerA technical journal published bythe RCA Technical Excellence Center"by and for the RCA engineer"

13 Roszel Road, P.O. Box 432, Princeton, N.J. 08540-0432

Address correction requested

Printed in the U.S.A.Form No. RE -30-2

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