rcw@dei - adl
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Architectural Description Languages:Past, Present, and Future
Luca [email protected]
System Architectures Group
October 29, 2008
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 1 / 44
Outline
1 Overview of Architectural Description Languages
2 ADL based Design Methodologies
3 ADL: Most Important Examples
4 TRAP: TRansactional level Automatic Processor generator
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 2 / 44
ADL: Overview
Outline
1 Overview of Architectural Description LanguagesWhat are They?Why?Classification
2 ADL based Design Methodologies
3 ADL: Most Important Examples
4 TRAP: TRansactional level Automatic Processor generator
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 3 / 44
ADL: Overview What are They?
Architectural Description Languages: What are they?
Architectural Description Languages
High level specification of (processor) architectures used during theirdesign, verification, implementation, simulation . . .
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 4 / 44
ADL: Overview What are They?
Architectural Description Languages: What are they?
ADLs
High level specification of(processor) architecturesused for their design,verification,implementation,simulation . . .
Example
Architecture Specification(User Manual)
ADL Specification
ModelGeneration
Hardware PrototypeValidation Models
...
TestGeneration
Test ProgramsTestbenches
...
ToolkitGeneration
Compiler, SimulatorAssembler, Debugger
...
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 5 / 44
ADL: Overview What are They?
Architectural Description Languages: What are they?
ADLs capture the structure (hardware components and their connectivity)and the behavior (instruction-set) of processor architectures
Enable:
high level processor modeling
automatic analysis of processor architectures
automatic prototype generation
General Features
Based on a simple specification:
Formal and unambiguous semanticsEasy correlation with the architecture manual
Automatically produce tools for the design flow
Compiler, Simulator, RTL code . . .
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 6 / 44
ADL: Overview What are They?
Architectural Description Languages: What are they?
ADLs capture the structure (hardware components and their connectivity)and the behavior (instruction-set) of processor architectures
Enable:
high level processor modeling
automatic analysis of processor architectures
automatic prototype generation
General Features
Based on a simple specification:
Formal and unambiguous semanticsEasy correlation with the architecture manual
Automatically produce tools for the design flow
Compiler, Simulator, RTL code . . .
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 6 / 44
ADL: Overview What are They?
Architectural Description Languages: What are they?
ADLs capture the structure (hardware components and their connectivity)and the behavior (instruction-set) of processor architectures
Enable:
high level processor modeling
automatic analysis of processor architectures
automatic prototype generation
General Features
Based on a simple specification:
Formal and unambiguous semanticsEasy correlation with the architecture manual
Automatically produce tools for the design flow
Compiler, Simulator, RTL code . . .
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 6 / 44
ADL: Overview Why?
Architectural Description Languages: Why?
Embedded Systems’ market stresses performance, customization,tight time-to-market, . . .
Rapid Exploration and evaluation of system configuration is needed.
Automation of the development process may help by:
Keeping the model and its implementation consistentProviding a wide range of tools to aid the designer
A formal specification improves communication among team members
It represents the first mapping from requirements to architecturalcomponents
It enables evaluation of system’s target metrics
Validation of early design decisions
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 7 / 44
ADL: Overview Why?
Architectural Description Languages: Why?
Embedded Systems’ market stresses performance, customization,tight time-to-market, . . .
Rapid Exploration and evaluation of system configuration is needed.
Automation of the development process may help by:
Keeping the model and its implementation consistentProviding a wide range of tools to aid the designer
A formal specification improves communication among team members
It represents the first mapping from requirements to architecturalcomponents
It enables evaluation of system’s target metrics
Validation of early design decisions
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 7 / 44
ADL: Overview Why?
Architectural Description Languages: Why?
Embedded Systems’ market stresses performance, customization,tight time-to-market, . . .
Rapid Exploration and evaluation of system configuration is needed.
Automation of the development process may help by:
Keeping the model and its implementation consistentProviding a wide range of tools to aid the designer
A formal specification improves communication among team members
It represents the first mapping from requirements to architecturalcomponents
It enables evaluation of system’s target metrics
Validation of early design decisions
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 7 / 44
ADL: Overview Why?
Architectural Description Languages: Why?
Embedded Systems’ market stresses performance, customization,tight time-to-market, . . .
Rapid Exploration and evaluation of system configuration is needed.
Automation of the development process may help by:
Keeping the model and its implementation consistentProviding a wide range of tools to aid the designer
A formal specification improves communication among team members
It represents the first mapping from requirements to architecturalcomponents
It enables evaluation of system’s target metrics
Validation of early design decisions
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 7 / 44
ADL: Overview Classification
Architectural Description Languages: Classification
Architecture Description Languages (ADLs)
Structural ADLs(e.g.
MIMOLA)
Mixed ADLs(e.g. EXPRESSION,
LISA, nML)
Behavioral ADLs
(e.g. ISDL)
Synthesis-oriented
Validation-oriented
Compilation-oriented
Simulation-oriented
Structural ADL
Describes the low-level structure of the processor
Helps achieving generality
Suitable for hardware synthesis and RTL cycle-accurate simulation
Unfit to efficiently model the ISA
No compiler or functional simulator generation
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 8 / 44
ADL: Overview Classification
Structural ADL
RT-level description
Describe in detail the structure of the basic processor elements(ALUs, registers, . . . )
Consistent work for the designerNo close relation with the processor manual
Overall ISA behavior not explicit
it must be extracted from the structural descriptionDifficult creation of tools which require behavioral information
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 9 / 44
ADL: Overview Classification
Architectural Description Languages: Classification
Architecture Description Languages (ADLs)
Structural ADLs
(e.g. MIMOLA)
Mixed ADLs(e.g. EXPRESSION,
LISA, nML)
Behavioral ADLs
(e.g. ISDL)
Synthesis-oriented
Validation-oriented
Compilation-oriented
Simulation-oriented
Behavioral ADL
Models the Instruction Set Architecture of the processor
One-to-one correspondence with the architecture and instruction-setmanual
Suitable for compiler retargeting and functional simulation
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 10 / 44
ADL: Overview Classification
Behavioral ADL
High Level Description
Focuses on the behavior rather than on its implementation
Explicit specification of the instruction semantics
Suitable for modeling the architecture functional behavior
Detailed hardware structure is ignored
Complex modeling of timing detailsTedious and explicit specification of hazards, exceptions . . .Complex generation of synthesizable HDL code
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 11 / 44
ADL: Overview Classification
Architectural Description Languages: Classification
Architecture Description Languages (ADLs)
Structural ADLs
(e.g. MIMOLA)
Mixed ADLs(e.g. EXPRESSION,
LISA, nML)
Behavioral ADLs
(e.g. ISDL)
Synthesis-oriented
Validation-oriented
Compilation-oriented
Simulation-oriented
Mixed ADL
Capture both structural and behavioral details of the architecture
Combine the benefits of Structural and Behavioral languages
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 12 / 44
ADL: Overview Classification
Mixed ADL
Suitable for a wide range of design automation tasks
compiler retargetingfunctional, RTL, and cycle-accurate simulationarchitecture synthesisexploration of design choices
Ammount of structural details kept to a minimum
pipelinedata and resource hazardsregister bypassing. . .
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 13 / 44
ADL: Overview Classification
Architectural Description Languages: Classification
Objective-base classification
Classification based on the primary purpose of the ADL, theobjective for which it is optimized
Compilation-oriented ADL
Simulation-oriented ADL
Synthesis-oriented ADL
Validation-oriented ADL
Architecture Description Languages (ADLs)
Structural ADLs
(e.g. MIMOLA)
Mixed ADLs(e.g. EXPRESSION,
LISA, nML)
Behavioral ADLs
(e.g. ISDL)
Synthesis-oriented
Validation-oriented
Compilation-oriented
Simulation-oriented
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 14 / 44
Design Methodologies
Outline
1 Overview of Architectural Description Languages
2 ADL based Design MethodologiesOverviewDesign Space ExplorationRetargetable Compiler GenerationRetargetable Simulator GenerationArchitecture SynthesisValidation
3 ADL: Most Important Examples
4 TRAP: TRansactional level Automatic Processor generator
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 15 / 44
Design Methodologies Overview
ADL based Design Methodologies
Embedded systems usually target narrow application classes
Customization and heavy optimization is possible and needed
Rapid exploration and evaluation of candidate architectures isnecessary
ADLs enable the automatic creation of development and support tools
ADLs driven design allow to easily test and analyse differentimplementations and designs
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 16 / 44
Design Methodologies Overview
ADL based Design Methodologies
Embedded systems usually target narrow application classes
Customization and heavy optimization is possible and needed
Rapid exploration and evaluation of candidate architectures isnecessary
ADLs enable the automatic creation of development and support tools
ADLs driven design allow to easily test and analyse differentimplementations and designs
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 16 / 44
Design Methodologies Design Space Exploration
Design Space Exploration
ADL Specification(Embedded Processor)
HardwareGenerator
HardwareModel
CompilerGenerator
Compiler
SimulatorGenerator
Simulator
ApplicationPrograms
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Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 17 / 44
Design Methodologies Retargetable Compiler Generation
Retargetable Compiler Generation
Definition
A compiler is classified as retargetable if it can be adapted to generate codefor different target processors with significant reuse of the compiler’s sourcecode
Necessary for exploiting the architecture’s custom features
Various levels of retargetability:
Instruction Set: code creation for different instruction sets
Architectural details usually needed only for code optimizationse.g. Knowledge on pipeline structure may reduce stalls by enabling betterscheduling
Processor pipeline: generation of optimized code in front of changes in theprocessor pipeline
Derived from the structural description of the processor’s pipelineExplicitly provided in Mixed ADLsImplicit in Structural ADLs
Memory hierarchy: taken into account to optimize the runtime and thepower consumption of processors
Cache-Based systems (e.g. data-placement to reduce misses)Scratchpad-Based systems (automatic generation of code to managescratchpads)
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 18 / 44
Design Methodologies Retargetable Compiler Generation
Retargetable Compiler Generation
Definition
A compiler is classified as retargetable if it can be adapted to generate codefor different target processors with significant reuse of the compiler’s sourcecode
Necessary for exploiting the architecture’s custom featuresVarious levels of retargetability:
Instruction Set: code creation for different instruction sets
Architectural details usually needed only for code optimizationse.g. Knowledge on pipeline structure may reduce stalls by enabling betterscheduling
Processor pipeline: generation of optimized code in front of changes in theprocessor pipeline
Derived from the structural description of the processor’s pipelineExplicitly provided in Mixed ADLsImplicit in Structural ADLs
Memory hierarchy: taken into account to optimize the runtime and thepower consumption of processors
Cache-Based systems (e.g. data-placement to reduce misses)Scratchpad-Based systems (automatic generation of code to managescratchpads)
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 18 / 44
Design Methodologies Retargetable Compiler Generation
Retargetable Compiler Generation
Information necessary for compiler retargeting can be expressed invarious ways:
parameter based: microarchitectural parameters (operation latencies,number of functional units, number of registers, . . . ) are explicitlyprovided in the ADL (behavioral and mixed ADLs)structure based: the processor’s structure is described;microarchitectural parameters and pipeline details are automaticallyextracted (structural ADLs)
the mapping between the target ISA and the compiler IntermediateRepresentation (IR) is usually explicitly provided
e.g. GCC translates programs into RTL expressions ((plus:SI(reg:SI 2) (const int 10)))We have to provide mapping between ISA and RTL expressions
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 19 / 44
Design Methodologies Retargetable Simulator Generation
Retargetable Simulator Generation
Tradeoff-between retargetability and simulation speed:Limited retargetability:
+ high simulation speed
- limited applicability in the design process
Simulation is used in many phases of the development process:
verification of system’s functionality
verification of system’s timing behavior
generation of quantitative metrics (power consumption, . . . )
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 20 / 44
Design Methodologies Retargetable Simulator Generation
Retargetable Simulator Generation
Tradeoff-between retargetability and simulation speed:Limited retargetability:
+ high simulation speed
- limited applicability in the design process
Simulation is used in many phases of the development process:
verification of system’s functionality
verification of system’s timing behavior
generation of quantitative metrics (power consumption, . . . )
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 20 / 44
Design Methodologies Retargetable Simulator Generation
Retargetable Simulator Generation
Classification can be made on how the simulator structure refers to theprocessor’s:
pin-accurate models the external processor interface
bit-accurate precise description of the processor’s internal structure
pipeline-accurate focuses on interaction among pipeline stages
. . .
Different abstraction levels:
Functional:
Simulates only the processor’s functionalityObtainable by modeling only the instructions set
Cycle-accurate:
Produces detailed timing informationRequires the specification of some structural details
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 21 / 44
Design Methodologies Retargetable Simulator Generation
Retargetable Simulator Generation
Classification can be made on how the simulator structure refers to theprocessor’s:
pin-accurate models the external processor interface
bit-accurate precise description of the processor’s internal structure
pipeline-accurate focuses on interaction among pipeline stages
. . .
Different abstraction levels:
Functional:
Simulates only the processor’s functionalityObtainable by modeling only the instructions set
Cycle-accurate:
Produces detailed timing informationRequires the specification of some structural details
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 21 / 44
Design Methodologies Retargetable Simulator Generation
Retargetable Simulator Generation
Phase-accurate
model
Cycle-accurate
model
Instruction-accuratemodel
High-levelmodel
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ProcessorInstructions
Cycles Phases
Temporal Accuracy
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Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 22 / 44
Design Methodologies Architecture Synthesis
Architecture Synthesis
Definition
Generation of synthesizable HDL code of the described processor core
Two approaches:
Parametrized processor-core based (e.g. Tensilica):
Partially customizable processor templateA generic processor is configured changing cache size, register bankwidth . . .support tools (e.g. compiler, simulator) are automatically created
Fully retargetable
Customization of all the processor aspects
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 23 / 44
Design Methodologies Architecture Synthesis
Architecture Synthesis
Definition
Generation of synthesizable HDL code of the described processor core
Two approaches:
Parametrized processor-core based (e.g. Tensilica):
Partially customizable processor templateA generic processor is configured changing cache size, register bankwidth . . .support tools (e.g. compiler, simulator) are automatically created
Fully retargetable
Customization of all the processor aspects
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 23 / 44
Design Methodologies Validation
Validation
Definition
Assessment of the model’s correctness with respect to the specification
Problems
Specification usually given innatural language
Lack of a golden referencemodel
ADL-driven validation: ADLspecification as golden model atdifferent abstraction levels
Architecture Specification(Processor User Manual)
ADL Specification(Golden Reference Model)
Manualverification
HDLGenerator
Test-vectorGenerator
RTL Implementation RTLDesign
Properties
SimGenerator
Simulator
Sameoutput
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Symb
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Simula
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Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 24 / 44
Design Methodologies Validation
Validation
Simulation Based:
Test vectors are automatically generated from the ADL specificationOutput of the RTL implementation and of the simulator can becompared
Model Checking
Properties are created from the ADL specificationChecked against the RTL implementation using model checkers andSymbolic simulators
Equivalence Checking
Formal techniques are used to prove that two versions of a design areequivalent or notDesign versions need to be similarCan be used to check manually optimized with respect to theautomatically generated golden model
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 25 / 44
Most Important Examples
Outline
1 Overview of Architectural Description Languages
2 ADL based Design Methodologies
3 ADL: Most Important ExamplesOverviewMIMOLAnMLLISAOther Examples
4 TRAP: TRansactional level Automatic Processor generator
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 26 / 44
Most Important Examples Overview
ADL: Most Important Examples
MIMOLA: structural ADL
Close to an HDL: its primary purpose is to create the hardwareimplementation of custom algorithmsbased on the PASCAL programming language
nML: behavioral ADL
minimizes the required amount of knowledge about the hardwarestructureused by the commercial tools Chess/Checkers
LISA: mixed ADL
contains information of both the structure and the instruction set ofthe target processorgenerates a variety of tools, from retargetable simulators to compilersand synthesisable HDL
Others: EXPRESSION, MADL, ADL++, ArchC, . . .
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 27 / 44
Most Important Examples MIMOLA
MIMOLAMachine Independent Micro-Programming Language
Structural language designed for synthesis of Application SpecificProcessors
Given a set of application specified using a high level language, MIMOLAcreates an architecture emulating the overall structure of the applications
If al algorithm for picture rotations is used, then a picture rotationprocessor will be created
Enables the creation of:
Cycle-accurate simulators
Retargetable compilers
Synthetizable HDL code
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 28 / 44
Most Important Examples MIMOLA
MIMOLA
Input:
Pascal-like description of the behavior to be implementedPredefined available structural componentsHints of the designer to create more efficient tools
Same input language can be used for hardware components andprogram behavior
Extension to Pascal for manual identification of parallelism
Works as tool for high level synthesis
It produces the hardware implementation of the specified behaviorNo instruction set will be used in the final design
. . . Or produces a micro-code interpreter (as ASIP)
The microcode is generated with the retargetable compiler
It is also possible to directly describe hardware modules and call themfrom the application program
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 29 / 44
Most Important Examples MIMOLA
MIMOLA: Example
Algorithm definition:
Program Mult;var a, b, c: integer;begina := 5; b := 7; c := 0;repeatc := c + a; b := b - 1;
until b = 0;end.
Definition of a module:
module ALU(in a,b:word;fct s:(0), out f:word)
beginf <- case s of0: a + b1: a - b
end;end;
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 30 / 44
Most Important Examples nML
nML
Behavioral language designed mainly for retargetable compilation
Works at the abstraction of the programmer’s manual
Requires the right ammount of knowledge of hardware structure
Not too many details which complicate the descriptionEnough details to assure high-quality results
Used by the commercial tools Chess/Checkers
compiler/cycle-accurate simulator
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 31 / 44
Most Important Examples nML
nML
Structural description:
Models storage elements (memories, registers, . . . )
Connections are modeled by transitory storage
pass a value from input to output without delay
Transitories are also used to model resources that may lead tohardware conflicts
at most one operation at a time can write to a transitoryby allowing access to the memory only through a transitory we canenforce one access at a time
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 32 / 44
Most Important Examples nML
nML
Instruction-Set description:
ISA structure specified using an attribute grammar
Actions attributes are associated to instruction parts
Implement the behavior of the instructionsModel cycle accurate details (pipeline stages, hazards, . . . )
Instruction Set hierarchies employed to reduce verbosity of thedescription
Different instruction parts can be combined with and or or rules
Execution pipeline is explicitly modeled in the action attributes
Behavior in front of Structural and Data hazards is explicitly specified
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 33 / 44
Most Important Examples nML
nML: Example
opn arith_mem_ind_instr (ar : arith_instr,mi : mem_ind_instr)
{action {ar.action;mi.action;
}syntax : ar.syntax ", " mi.syntax;image : ar.image::mi.image
}
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 34 / 44
Most Important Examples nML
nML: Example
opn cond_branch (t : c_10, c : cond){action {stage EX1:tT = t;switch (c){
case EQ:tC = eq(AS);......
}}....
}
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 35 / 44
Most Important Examples LISA
LISA
Mixed language designed for retargetable compilation, simulation and HDLgeneration
ASIP viewed first as an Instruction Set Architeture
ISA description captures the syntax, encoding and behavior of theinstructions
On top we have the structural information
Includes a timing model for each instruction
ISA description is mapped on the structural details during modelrefinement
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 36 / 44
Most Important Examples LISA
LISA
Operations are the basic LISA building block
Instruction descriptions are composed of several Operations
Operations are connected by activationsOperations can activate each other
Behaviors are associated to Operations
Described using the C programming language
Various tools can be generated:
Simulators (Interpreted, Compiler, . . . )
Retargetable Compiler
Synthetizable HDL implementation
Verification support tools (Equivalence Check, Test VectorGeneration, . . . )
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 37 / 44
Most Important Examples Other Examples
Other Examples
EXPRESSION
Mixed-level ADL: it captures both structure and behaviorSupports RISC, DSP, VLIW, and Superscalar architecturesEnables retargetable compiler/simulator generation, design spaceexploration, synthesizable HDL generation, and functional verification
MADL
Aims at the creation of both the cycle-accurate simulators andcompilers for a wide variety of architecturesUsed Operation State Machine (OSM) model to describe the processor
special version of Extended Finite State Machineseach state machine represents an ISA operation
resources are modeled as tokens
interaction between through tokens and OSMs control the progress ofthe operationsthis method encodes data dependencies, hazards, . . .
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 38 / 44
Most Important Examples Other Examples
Other Examples
ADL++Behavioral languageInitially thought for the generation of retargetable simulators,assemblers and disassemblersTargets complex architectures and Instruction Set, such as Intel IA-32Based on the concept of templates:
software module consisting of only the architecture-independent parts
Decoupling of ISA and microarchitectural detailsit facilitates the extension of the ISAit facilitates the development of different microarchitecturalimplementations
ArchCBehavioral Architectural Description Language based on SystemCEnables the generation of functional/cycle-accurate simulators and ofassemblersSeparates the instruction set from the microarchitectural descriptionInstruction behavior is explicitly specified in C++
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 39 / 44
TRAP
Outline
1 Overview of Architectural Description Languages
2 ADL based Design Methodologies
3 ADL: Most Important Examples
4 TRAP: TRansactional level Automatic Processor generator
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 40 / 44
TRAP
TRAP: TRansactional level Automatic Processor generatorhttp://code.google.com/p/trap-gen/
Mixed ADL designed for the generation of fast and accurateInstruction Set Simulators
Tight integration with SystemC and TLM 2.0
Language specified on top of Python
Development still in progress:
Only generation of functional simulators complete
Full/Partial Retargeting of GCC compiler will be implemented
enables true automatic design space exploration
Automatic retargetable dynamic binary translation will be used toaccelerate simulation
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 41 / 44
TRAP
TRAP
ISABehavior
ISAEncoding
ArchitectureDescription
TRAP APIC++ Writer
Python
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CycleAccurate
Retargetabledebugger
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Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 42 / 44
TRAP
TRAP Example: Architectural Description
p r o c e s s o r = t r a p . P r o c e s s o r ( 'ARM7TDMI ' , sys temc = False ,i n s t r u c t i o n C a c h e = True )
p r o c e s s o r . s e t L i t t l e E n d i a n ( )p r o c e s s o r . s e t W o r d s i z e ( 4 , 8 )p r o c e s s o r . s e t I S A ( ARMIsa . i s a )
regBank = t r a p . R e g i s t e r B a n k ( 'RB ' , 30 , 32 )cps rB i tMask = { 'N ' : ( 31 , 31 ) , 'Z ' : ( 30 , 30 ) , 'C ' : ( 29 , 29 ) , '
V ' : ( 28 , 28 ) , ' I ' : ( 7 , 7 ) , 'F ' : ( 6 , 6 ) , 'mode ' : ( 0 , 3 ) }c p s r = t r a p . R e g i s t e r ( 'CPSR ' , 32 , cps rB i tMask )
r e g s = t r a p . Al iasRegBank ( 'REGS ' , 16 , 'RB[ 0−15 ] ' )
p r o c e s s o r . setMemory ( 'dataMem ' , 10*1024*1024 )
i r q = t r a p . I n t e r r u p t ( ' IRQ ' , p r i o r i t y = 0 )p r o c e s s o r . a d d I r q ( i r q )p r o c e s s o r . s e t I R Q O p e r a t i o n ( ARMIsa . IRQOperat ion )
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 43 / 44
TRAP
TRAP Example: ISA
dataProc imm = t r a p . MachineCode ( [ ( ' cond ' , 4 ) , ( ' i d ' , 3 ) , ( '
opcode ' , 4 ) , ( ' s ' , 1 ) , ( ' rn ' , 4 ) , ( ' rd ' , 4 ) , ( ' r o t a t e ' , 4 ), ( ' immediate ' , 8 ) ] )
dataProc imm . s e t V a r F i e l d ( ' rd ' , ( 'REGS ' , 0 ) )dataProc imm . s e t B i t f i e l d ( ' i d ' , [ 0 , 0 , 1 ] )
opCode = c x x w r i t e r . Code ( ”””rd = rn + operand ;””” )a d c s h i f t i m m I n s t r = t r a p . I n s t r u c t i o n ( ' ADC si ' )a d c s h i f t i m m I n s t r . setMachineCode ( d a t a P r o c i m m s h i f t , { '
opcode ' : [ 0 , 1 , 0 , 1 ] } , 'TODO ' )a d c s h i f t i m m I n s t r . setCode ( opCode , ' e x e c u t e ' )a d c s h i f t i m m I n s t r . a d d B e h a v i o r ( condCheckOp , ' e x e c u t e ' )a d c s h i f t i m m I n s t r . a d d B e h a v i o r ( UpdatePSRSum , ' e x e c u t e ' ,
Fa l se )a d c s h i f t i m m I n s t r . addTest ( { ' cond ' : 0xe , ' s ' : 0 , ' rn ' : 9 , '
rd ' : 10 , ' rm ' : 8 , ' sh i f t amm ' : 0 , ' s h i f t o p ' : 0} , { 'REGS [ 9] ' : 3 , 'REGS [ 8 ] ' : 3} , { 'REGS [ 10 ] ' : 6} )
Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 44 / 44