re-examining conventional wisdom for networks-on-chip in ...mpapamic/research/fpga2012... ·...

Re-Examining Conventional Wisdom for

Networks-on-Chip in the Context of FPGAs

Monterey, CA, February 2012

Michael K. Papamichael, James C. Hoe [email protected], [email protected]

Computer Architecture Lab at

This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations.

CALCM - Computer Architecture Lab at Carnegie Mellon

Rapid growth of FPGA capacity and features Extended SoC and full-system prototyping FPGA-based high-performance computing

FPGAs and Networks-on-Chip (NoCs)

2

FPGA (Xilinx LX110T)

FPGA area requirements

for state-of-the-art mesh NoC*

3x3 4x4

5x5

*NoC RTL from http://nocs.stanford.edu/router.html

Map existing ASIC-oriented NoC designs on FPGAs?

Need for flexible NoCs to support communication




3




3x3 4x4

5x5


Map existing ASIC-oriented NoC designs on FPGAs? Inefficient use of FPGA resources ASIC-driven NoC architecture not optimal for FPGA





4




3x3 4x4

5x5


FPGA-tuned NoC Architecture Embodies FPGA-motivated design principles Very lightweight, minimizes resource usage

~50% resource reduction vs. ASIC-oriented NoC

Flexible NoC generator – public release today!

Map existing ASIC-oriented NoC designs on FPGAs? Inefficient use of FPGA resources ASIC-driven NoC architecture not optimal for FPGA


Often goes against ASIC-driven NoC conventional wisdom


Outline

5

NoC Terminology (single-slide review)

Approach

Tailoring NoCs to FPGAs

Results & Demo

Related Work & Conclusion

Public Release


Outline

6


Approach


Results & Demo


Public Release


Packets Basic logical unit of transmission

Flits Packets broken into into multiple flits – unit of flow control

Virtual Channels Multiple logical channels over single physical link

Flow Control Management of buffer space in the network

NoC Terminology Overview

7

Packet F F F F F F

Flits A B

Router A

Router A

Data Channel/Link Virtual Channels

Flow Control Link

Packet F F F F F F H T

Tail Flit Flits Head Flit Router B

Virtual Channels

T

Tail Flit Head Flit

H


Outline

8


Approach


Results & Demo


Public Release


How FPGAs are Different from ASICs

9

FPGAs peculiar HW realization substrate in terms of

Relative cost of speed vs. logic vs. wires vs. memory

Unique mapping and operating characteristics

focuses on 4 FPGA characteristics:

FPGA characteristics uniquely influence key NoC design decisions

Abundance of Wires 1

Reconfigurable Nature 4

Frequency Challenged 3

Storage Shortage & Peculiarities 2

Abundance of Wires 1



10

Densely connected wiring substrate

(Over)provisioned to handle worst case

Wires are “free” compared to other resources

Abundance of Wires Abundance of Wires 1

Make datapaths and channels as wide as possible

Adjust packet format

E.g. carry control info on the side through dedicated links

Adapt traditional credit-based flow control

--CONNECT-- NoC Implications



11

Modern FPGAs offer storage in two forms

Block RAMs and LUT RAMs (use logic resources)

Only come in specific aspect ratios and sizes

Typically in high demand, especially Block RAMs

Abundance of Wires Storage Shortage & Peculiarities 2

Minimize usage and optimize for aspect ratios and sizes

Implement multiple logical flit buffers in each physical buffer

Use LUT RAM for flit buffers

Block RAM much larger than typically NoC flit buffer sizes Allow rest of design to use scarce Block RAM resources




12

Much lower frequencies compared to ASICs LUTs inherently slower that ASIC standard cells Large wire delays when chaining LUTs

Rapidly diminishing returns when pipelining Deep pipelining hard due to quantization effects

Abundance of Wires Frequency “Challenged”

Design router as single-stage pipeline Also dramatically reduces network latency

Make up for lower frequency by adjusting network E.g. increase width of datapath and links or change topology


3



13

Reconfigurable nature of FPGAs Sets them apart from ASICs

Support diverse range of applications

Abundance of Wires Reconfigurable Nature

Support extensive application-specific customization

Flexible parameterized NoC architecture

Automated NoC design generator (demo!)

Adhere to standard common interface

NoC appears as plug-and-play black box from user-perspective


4


Outline

14


Approach


Results & Demo


Public Release


16-node 4x4 Mesh Network-on-Chip (NoC) SOTA: state-of-the-art high-quality ASIC-oriented RTL* CONNECT: identically configured -generated RTL

CONNECT vs. ASIC-Oriented RTL

15

*NoC RTL from http://nocs.stanford.edu/cgi-bin/trac.cgi/wiki/Resources/Router

FPGA Resource Usage (same router/NoC configuration)

SOTA

9K

8K

7K

6K

5K

4K

3K

2K

1K

Single Router

LUTs

4x4 Mesh Noc

60K

50K

40K

30K

20K

10K

LUTs

w/

FPG

A R

TL o

pts

.

50%

50%

2 4 6 8 10 12


500

400

300

200

100

Load (in Gbps)

Avg

. Pac

ket

Late

ncy

(in

ns)

2 4 6 8

16-node 4x4 Mesh Network-on-Chip (NoC) SOTA: state-of-the-art high-quality ASIC-oriented RTL* CONNECT: identically configured -generated RTL

CONNECT vs. ASIC-Oriented RTL

16

*NoC RTL from http://nocs.stanford.edu/cgi-bin/trac.cgi/wiki/Resources/Router

FPGA Resource Usage (same router/NoC configuration)

SOTA

9K

8K

7K

6K

5K

4K

3K

2K

1K

Single Router

LUTs

4x4 Mesh Noc

60K

50K

40K

30K

20K

10K

LUTs

Network Performance

(uniform random traffic @ 100MHz)

w/

FPG

A R

TL o

pts

.

50%

50%

2 4 6 8 10 12

~50% lower LUT Usage

2x lower idle latency

same LUT bugdet → 4x BW

similar bandwidth


CONNECT Sample Networks

17

Four sample CONNECT Networks ( router, endpoint) 16 endpoints, 2/4 virtual channels, 128-bit datapath

Ring Mesh Fat Tree High Radix

All above networks are interchangeable from user perspective

40

20

Load (in flits/cycle)

Late

ncy

(i

n c

ycle

s)

0.25 0.50 0.75 1

40

20


Late

ncy

(i

n c

ycle

s)

0.25 0.50 0.75 1

Uniform Random Traffic 90% Neighbor Traffic

Ring Fat Tree Mesh High Radix


CONNECT Sample Networks

18

Four sample CONNECT Networks ( router, endpoint) 16 endpoints, 2/4 virtual channels, 128-bit datapath

Ring Mesh Fat Tree High Radix

All above networks are interchangeable from user perspective

40

20


Late

ncy

(i

n c

ycle

s)

0.25 0.50 0.75 1

40

20


Late

ncy

(i

n c

ycle

s)

0.25 0.50 0.75 1

Uniform Random Traffic 90% Neighbor Traffic

please see paper for more synthesis & performance results

Ring Fat Tree Mesh High Radix

There is no one-size-fits-all NoC! Tune NoC to application.


Generates FPGA-tuned NoCs Used as part of larger system Coexist with rest of FPGA-resident components

Lightweight Minimize FPGA resource usage

Flexible Support rapid design space exploration Fully parameterized, topology-agnostic architecture Standard interface across different configurations

Adjustable Trade off performance vs. area

Public Release – Demo!

CONNECT NoC Generator

19


Outline

20


Approach


Results & Demo


Public Release


FPGA-oriented NoC Architectures

PNoC: lightweight circuit-switched NoC [Hilton ’06]

NoCem: simple router block, no virtual channels [Schelle ’08]

FPGA-related NoC Studies

Analytical models for predicting NoC perf. on FPGAs [Lee ‘10]

Effect of FPGA NoC params on multiproccesor system [Lee ‘09]

Modify FPGA configuration circuitry to build NoC

Metawire: use configuration circuitry as NoC [Shelburne ’08]

Time-division multiplexed wiring to enable new NoC [Francis ‘08]

Commercial Interconnect Approaches

ARM AMBA, STNoC, CoreConnect PLB/OPB, Altera Qsys, etc.

Related Work

21


Significant gains from tuning for FPGA

FPGAs and ASICs have different design “sweet spot”

CONNECT → flexible, efficient, lightweight NoC

Compared to ASIC-driven NoC, CONNECT offers

Significantly lower network latency and

~50% lower LUT usage or 3-4x higher network performance

Take advantage of reconfigurable nature of FPGA

Tailor NoC to specific communication needs of application

Conclusions

Acknowledgements

22


Outline

23


Approach


Results & Demo


Public Release


Public Release

http://www.ece.cmu.edu/~mpapamic/connect/

NoC Generator with web-based interface Supports multiple pre-configured topologies Includes graphical editor for custom topologies FreeBSD-like license (limited to non-commercial research use)

Acknowledgments Derek Chiou, Daniel Becker & Stanford CVA group NSF, Xilinx, Bluespec

Please come see me for demo! 24


Questions?

Thanks!

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