real-time systems lab, computer science and engineering, asu quark spi interface (esp – fall 2014)...

Real-time Systems Lab, Computer Science and Engineering, ASU

Quark SPI Interface(ESP – Fall 2014)

Computer Science & Engineering DepartmentArizona State University

Tempe, AZ 85287

Dr. Yann-Hang [email protected](480) 727-7507


A duplex, synchronous, serial communication between CPU and peripheral devices Master mode and slave mode Bi-directional mode Synchronous serial clock

Signals: MOSI: master out slave in MISO: master in slave out SS: select signal from master to slave SCK: serial clock

Serial Peripheral Interface (SPI)

MOSI

MISO

SCK

SS1

SS2

MOSI

MISO

SCK

SS

MOSI

MISO

SCK

SS

processor peripheral 2

peripheral 1

2


SPI Operation

Data registers in the master and the slave form a distributed register.

When a data transfer operation is performed, this distributed register is serially shifted by the SCK clock from the master

Can shift in burst mode

shift reg. shift reg.

MOSI

MISO

transmit data reg

receive data reg

transmit data reg

receive data reg

3


CPOL and CPHA (Polarity and Phase)

CPHA=0 – the first edge on the SCK line is used to clock the first data bit (the first bit of the data must be ready when selected)

CPHA=1 – if required, the first SCK edge before the first data bit becomes available at the data out pin

4


SPI Interface on Quark

Three controllers: SPI0 and SPI1 + Lagecy SPI

On Galileo LSPI flash memory SPI0 ADC SPI1 IO pins 10-13

Does not use SPIx_SS signals

gpio 8 SPI0_CS gpio10 SPI1_CS Similar to the SPI of PXA2xx

chip (Xscale)

5


SPI Drivers on Quark

6

SPI core (spi.c)

spidev

SPI chip driver (pxa2xx.c, pxa2xx-pci.c)

SPI device driver1

SPI device driver2

user space

kernel

hardware

SPI controllers

/dev/spidev1.0 /dev/ledmatrix /dev/xxx


SPI Drivers

Driver for SPI devices protocol driver bound to a spi_device

Driver for SPI chips (controller) IO model

queued messages submitted by protocol drivers

spi_message : a list of spi_transfer struct spi_transfer object for a

full duplex SPI transfer write-only if NULL in rx_buf

spi_async or spi_sync to submit message spi_async -- must wait for the completion

callback before accessing the data buffers in the spi_transfer records

7

struct spi_transfer {

const void *tx_buf;

void *rx_buf;

unsigned len;

dma_addr_t tx_dma;

dma_addr_t rx_dma;

unsigned cs_change:1;

u8 bits_per_word;

u16 delay_usecs;

u32 speed_hz;

struct list_head transfer_list;

};


Key Data Structures for SPI Drivers

spi_message spi_device (spi_add_device) spi_driver (spi_register_driver) spi_master (spi_register_master)

8

struct spi_message {

struct list_head transfers;

struct spi_device *spi;

unsigned is_dma_mapped:1;

void (*complete)(void *context);

void *context;

unsigned actual_length;

int status;

struct list_head queue;

void *state;

};

struct spi_device {

struct device dev;

struct spi_master * master;

u32 max_speed_hz;

u8 chip_select;

u8 bits_per_word;

u16 mode;

int irq;

void * controller_state;

void * controller_data;

char modalias[SPI_NAME_SIZE];

int cs_gpio;

};


Linux spidev

a limited userspace API, supporting basic half-duplex read() and write() access to SPI slave

/dev/spidevB.C – for chipselect C on bus B use ioctl() to set up transfer mode (bits_per_word, lsb_first, …etc) read() and write() for half-duplex operations

9

spidev_sync_write(struct spidev_data *spidev, size_t len){

struct spi_transfer t = {.tx_buf = spidev->buffer,.len = len, };

struct spi_message m;

spi_message_init(&m);spi_message_add_tail(&t, &m);return spidev_sync(spidev, &m);}


Construct and Use SPI Interface

In spidev, when init, register spi_driver (spi_register_driver) add driver to SPI bus (driver_register) create device spidevB.C

In spi-pxa2xx.c call spi_register_master() to register a SPI master set up properties for SPI bus master (bus number, irq, bits_per_word, etc.)

When spidev_sync is called spi_async (spidev->spi, message) // spi_device

spi->master message->spi master->transfer tasklet_schedule(pump_transfer) when done spi_finalize_current_message and complete(context)

wait for completion

10

real-time systems lab, computer science and engineering, asu quark spi interface (esp – fall 2014)...

Documents