realization of low contact resistance close to theoretical ... · realization of low contact...

Nano Res

1

Realization of low contact resistance close to

theoretical limit in graphene transistors

Hua Zhong, Zhiyong Zhang(), Bingyan Chen, Haitao Xu, Dangming Yu, Le Huang and

Lian-Mao Peng()

Nano Res., Just Accepted Manuscript • DOI: 10.1007/s12274-014-0656-z

http://www.thenanoresearch.com on November 28 2014

© Tsinghua University Press 2014

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Nano Research

DOI 10.1007/s12274-014-0656-z

TABLE OF CONTENTS (TOC)



Hua Zhong, Zhiyong Zhang*, Bingyan Chen,

Haitao Xu, Dangming Yu, Le Huang and

Lian-Mao Peng*

Peking University, China

High quality graphene/metal junction with contact resistance below 100 Ω μm at

room temperature has been realized.



Hua Zhong, Zhiyong Zhang(), Bingyan Chen, Haitao Xu, Dangming Yu, Le Huang and Lian-Mao

Peng()

Received: day month year

Revised: day month year

Accepted: day month year

(automatically inserted by

the publisher)

© Tsinghua University Press

and Springer-Verlag Berlin

Heidelberg 2014

KEYWORDS

Graphene Field-Effect

Transistors,

Contact Resistance,

Metal-Graphene Interface,

Transfer Length Method

ABSTRACT

Realizing low contact resistance between graphene and metal electrode remains

a well-known challenge for building high-performance graphene devices. In

this work, we attempt to lower the contact resistance in graphene transistors

and further explore the resistance limit between graphene and metal contact.

Through adopting highly pure palladium and high-quality graphene and

controlling the fabrication process so as not to contaminate the interface, the

Pd/graphene contact resistance at room temperate is lowered to sub-100 Ω μm

level both on mechanically exfoliated and chemical-vapor-deposition graphene.

After excluding the parasitic series resistances from the measurement system

and electrodes, the retrieved contact resistance is shown to be systematically

and statistically less than 100 Ω μm, with the minimum value of 69 Ω μm which

is very close to the theoretical limit. Furthermore, the contact resistance shows

no clear dependence on temperature ranged from 77 K to 300 K, and this is

attributed to the saturation of carrier injection efficiency between graphene and

Pd owing to the high quality of the graphene samples used which have

sufficiently long carrier mean-free-path.

Nano Research

DOI (automatically inserted by the publisher)

Research Article

www.theNanoResearch.com∣www.Springer.com/journal/12274 | Nano Research

95 Nano Res.

1 Introduction

Contact resistance between metal and

semiconductor is crucial for electronic devices,

especially for field-effect transistors (FETs).

Realizing low contact resistance is therefore the

precondition for building high-performance FETs.

For a FET, the source/drain contact resistance

should be much smaller than the channel resistance

to ensure that semiconducting channel dominates

the whole output resistance, and devices with

higher mobility and shorter semiconducting

channel requires lower contact resistance.

Graphene is considered as a competing channel

material for constructing high-speed FETs for

radio-frequency (RF) applications owing to its

ultra-high carrier mobility [1]. Compared with

conventional semiconducting devices with similar

gate length, graphene FETs should have lower

channel resistance per transfer mode due to the

much higher carrier mobility or Fermi velocity, and

thus lower contact resistance than conventional

device between channel and source/drain junction

is required [2]. However realizing low contact

resistance between graphene/metal is a well-known

challenge due to the small density of states (DOS)

of graphene near the Dirac point. In the past five

years, tremendous endeavors have been done to

reduce the contact resistance of graphene FETs. For

example, various kinds of metals, such as titanium

[2], palladium [3], nickel [4], cobalt [5], chromium

[6] and gold [7], have been used to contact

graphene aiming to transfer more charges into

graphene and to increase its carrier density. On the

other hand, various methods for interface

modification, such as oxygen plasma treatment

[8-10], rapid thermal annealing [11], and graphene

contact area patterning [12], have been

demonstrated to lower graphene/metal contact

resistance via increasing the carrier density of

graphene or the carrier injection area/length.

Values of Rc obtained from all these studies ranges

from hundreds to thousands Ω μm, and the lowest

metal/graphene contact resistance reported at room

temperature is around 100 Ω μm with Cu contact

and Au-grain contact [12, 13]. Such a large contact

resistance severely degrades the performance of

graphene FETs (GFETs), limiting such key device

parameters as the on-current and the peak

transconductance [13]. Contact resistance is

therefore becoming the main obstacle for further

performance improvement of GFETs, especially as

channel length scales down to sub-100 nm. Further

reducing contact resistance is currently the most

urgent requirement and the most profitable task for

the development of high performance GFETs.

This work aims to lower the contact

resistance in graphene transistors and explore the

resistance limit. In particular, we reconsider the

Pd/graphene contact experiment and analysis that

were reported in Ref. [3], where a contact resistance

down to 185±20 Ω μm was reliably realized at RT.

By using highly pure palladium and high-quality

graphene, and controlling the device fabrication

process and thus maintaining the clean interface,

the palladium/graphene contact resistance at RT is

lowered to sub-100 Ω μm, which has never been

systematically obtained before. After excluding the

parasitic series resistances from measurement

system, the retrieved contact resistance is shown to

be systematically and statistically less than 100 Ω

μm with the lowest value of 69 Ω μm, which is

very close to the theoretical limit. Furthermore, on

contrast to the linear dependence on temperature

reported in Ref. [3], the graphene/metal contact

resistance in our experiments does not show

obvious temperature dependence. We attribute this

temperature independent contact resistance to the

saturation of injection efficiency between graphene

and Pd owing to the sufficiently long

mean-free-path of carriers in clean graphene. In

addition, the ultra-low contact resistance also

benefits from the usage of purer Pd layer, which

should induce heavier hole transfer between Pd

and graphene than in previous experiments. 2 Experimental and Results Graphene flakes were mechanically exfoliated onto

heavily-doped silicon substrate covered with 285

nm silicon oxide. Single layer graphene flakes were

identified by optical microscope, and further

confirmed by Raman spectroscopy before device

fabrication and by atomic force microscopy (AFM)

Address correspondence to Zhiyong Zhang, [email protected]; Lian-Mao Peng, [email protected]

| www.editorialmanager.com/nare/default.asp

96 Nano Res.

after electronic measurements. Typical Raman

spectrum and AFM image are presented in Figures

S1 and S2 (see supporting information). The

identified monolayer graphene flakes were firstly

etched into strips with 2 μm width, and then metal

electrodes (Pd/Au 30/50 nm) were patterned and

deposited to contact graphene through standard

electron-beam lithography (EBL) and

electron-beam evaporation (EBE) processes. It is

worth mentioning that the metal Pd with high

purity (99.95%) was evaporated in high vacuum

with base pressure of about 1×10-8 Torr. Pd is one

of the best contact metal for graphene due to the

high work function of Pd and its wetting property

on graphene. The high work function provides

high density of carrier transferred from Pd to the

graphene, and then leads to large number of

conducting modes. Meanwhile the good wetting

between graphene and Pd can provide large

transmission efficiency for carrier. Metal contact

length was designed as 1 μm, which is much larger

than the transfer length of carriers between the

metal contact and graphene and is sufficient for

injection of carriers [3, 14]. A group of devices were

fabricated on the same graphene strip, with

channel length arranging from 1 μm to 6 μm and

with a step of 1 μm. A scanning electron

microscope (SEM) image showing a group of

GFETs is presented as the inset of Figure 1a. Total

resistance (Rtotal) of each GFET was measured in

vacuum at RT as a function of back-gate voltage

(Vbg), with the source-drain bias (Vds) being set to

0.05 V. Transfer characteristics of a typical group of

GFETs are plotted in Figure 1a, in which the largest

resistance points (corresponding to the Dirac point

voltage Vdirac) are found to locate at -8.3±1.3 V,

corresponding to a residual carrier density

fluctuation of less than 1×1011 cm-2. The narrow

distribution of Vdirac reflects excellent uniformity of

the group of fabricated devices, while such a low

residual carrier density indicates that the graphene

quality remained very high even after device

fabrication. Under large gate bias Vbg=Vdirac±50 V,

the graphene channel is heavily electrical doped

with an average carrier density of up to 3.78×1012

cm-2, and effects due to residual carrier density

fluctuation are becoming negligible since the

residual carrier density is much smaller than the

total carrier density. Standard transfer length

method (TLM) is used here to extract contact

resistance, by calculating the total resistance of

graphene channel as

Rtotal=Rsheet/W×L+2Rc/Wc (1)

where Rsheet is the sheet resistance of graphene, L

and W are respectively the channel length and

width, and Rc is the contact width (Wc) normalized

contact resistance. In our experiments, the channel

width (W) is designed to equal the contact width

(Wc). By linearly fitting Rtotal of GFETs with

different channel lengths, 2Rc/Wc and Rsheet/W can

be obtained from the intercept (Rint) and slope

simultaneously. The retrieved Rsheet/W (black

squares) and Rc (red squares) at various back gate

voltages (Vbg) are plotted in Figure 1b, in which

both Rsheet and Rc decline with increasing net gate

voltage (|Vbg-VDriac|). The gate voltage dependence

of Rsheet and Rc are both due to field doping via gate,

which shifts the Fermi level of graphene in the

channel and beneath the metal contact and

modifies the density of states of graphene channel

[3]. It is worth mentioning that the minimum Rc at

the p branch Rcp approaches 104.7±12.9 Ω μm at

Vbg=Vdirac-50 V (the left end of measurement range),

which is smaller than the 185±20 Ω μm through Pd

contact in Ref. [3], and even smaller than the

published minimum metal/graphene contact

resistance [12, 13]. Similar to previous results, the

contact resistances at p-branch and n-branch are

asymmetric. For example the Rc at back-gate

voltage of Vdirac+50 V at n-branch is 396.3±35.7 Ω

μm, which is almost three times larger than that at

p-branch. Asymmetry found in Rc originates from

the metal-induced doping, i.e. electrons transfer

into or out of graphene under the metal contact.

The measured asymmetric Rc demonstrates that

graphene is heavily p-doped by Pd, as Rc in

p-branch is always smaller than that in n-branch.

The more asymmetric Rc between n and p branch

found here than that reported in Ref. [3] indicates

heavier doping in our Pd/graphene contact. In

addition, the net charge density induced by gate

voltage [given by Cbg(Vbg-VDirac)/e], is about 3.80×1012

cm-2 for Rc =104.7 Ω μm in our graphene channel,

while the corresponding value reported in Ref. [3]

for Rc =185 Ω μm is 7.18×1012 cm-2 (with -30 V net

gate voltage and 90 nm gate oxide). Realization of


97 Nano Res.

smaller contact resistance at lower gate-induced

carrier density here indicates that the contact

resistance improvement is originated from the

improved carrier injection at metal/graphene

interface, rather than the increased carrier

concentration and conduct modes in graphene

channel.

Obviously, the reliability of retrieved Rc and

Rsheet through TLM relies on the uniformity of

graphene channel and graphene/metal contacts

among all GFETs in one group. In an ideal situation,

the Rc and Rsheet obtained from GFETs in one group

should be identical, and Rtotal of these devices

should depend linearly on channel length at fixed

bias. However, absolute uniformity among GFETs

is impossible to achieve in reality since discrepancy

among devices, such as those caused by charged

impurity (manifested by the Dirac point voltages

fluctuation) and introduced during device

fabrication process, is inevitable. In general, the

more uniform the graphene channel is, the more

reliable the retrieved Rc and Rsheet are. In the group

of GFETs as shown in Figure 1a, excellent

uniformity is evident as manifested by the small

value of VDirac and its narrow distribution, and

retrieved results through TLM are thus quite

reasonable and reliable. Reliability of the retrieved

results is further verified through the following

data analysis. We randomly pick out i (=2, 3, 4, 5, 6)

GFETs with different L from the group of six GFETs,

and linearly fit Rtotal at Vbg=VDirac-50 V to discern the

divergence between each other. For all possible

combinations (∑𝐶6𝑖=57, for i =2, 3, 4, 5, 6), Rint are all

below 120 Ω. Distribution of Rint is given in Figure

S3, showing that 85 percent of them lie between

100±20 Ω. Figure 1c gives five fitting curves with

five different i, each of them corresponds to the

largest intercept under fixed i. Therefore the up

limit of Rint is no more than 120 Ω, which testifies

the rationality of the minimum Rc about 104.7±12.9

Ω μm retrieved through TLM in our experiments.

As another evidence to support our claim is

that it is indeed possible to obtain such a low

contact resistance. We also fabricated a short

channel GFET (with 500 nm gate length) on

mechanically exfoliated graphene using Pd as

metal contacts. As shown in Figure 1d, the device

exhibits an on-state current (Ion) as large as 324 μA

at source/drain bias voltage of 0.05 V and back-gate

voltage of -60 V, corresponding to an on-state

resistance (Ron) of 154 Ω. The resistance of

graphene channel (W=2 um and Leffect=0.3 μm),

taking charge transfer effect into account, is

estimated to be about 60 Ω by assuming Rsheet of

400 Ω/□, leading to a single Pd/graphene junction

Rc ~ 94 Ω μm [16]. In a former report, Guo et al.

also claimed that Rc in a palladium-contacted

100-nm top-gated GFET is less than 100 Ω μm [17].

Therefore it is reasonable to lower resistance of

Pd/graphene contact down to sub-100 Ω μm. By

the way, the 500 nm GFET presents obvious

n-branch suppression and positive Dirac point

voltage different from that in longer channel

devices. It is mainly because the graphene channel

could be influenced more easily by the charges

transferred from the contact metal compared to the

long-channel-length transistors.

Strictly speaking, contact resistance Rc should

contain four components, i.e. metal/graphene

interface junction resistance (Ri), resistance of metal

upon the interface (Rm), resistance of graphene

under the interface (Rg), and potential junction

resistance in graphene between the contact and

channel parts (Rj), i.e. Rc=Ri+Rm+Rg+Rj. However, in

an actual measurement (depicted in Figure 2a), the

measured Rtotal of a GFET also contains a parasitic

series resistance (Rp) from measurement system,

which includes interconnect metal line resistance

and probe/pad contact resistance, and the real Rtotal

should be expressed as

Rtotal=Rsheet/W×L+2Rc/Wc+Rp. (2)

Therefore the retrieved Rc (via, e.g. TLM) by just

removing the channel length dependent sheet

resistance of graphene channel also contains the

parasitic series resistance (Rp), which exists in all

measurement systems and is always neglected in

metal/graphene contact resistance measurements

and analysis. To obtain the intrinsic Rc of a GFET,

the parasitic series resistance (Rp) should be

measured and subtracted from the obtained Rint,

which means the intrinsic contact resistance

expression is

Rc=(Rint-Rp)×Wc/2. (3)

Note, Rp is a system parameter and independent of

contact width, which should be subtracted before

contact resistance normalization. In our


98 Nano Res.

experiments, we develop a method to estimate Rp

by measuring the resistances of metal ‘devices’,

whose geometry are exactly as the same as the

GFET, but with the graphene channel replaced by a

metal line with width of 4 μm. SEM image of the

calibration structure is shown in the inset of Figure

2b, and a full view of the device patterning is

shown in Figure S5. Two sets of metal ‘devices’ are

fabricated and measured, and all 12 devices show

resistances around 25 Ω as presented in Figure 2b.

The resistances of those 12 devices have no obvious

dependence on channel length, suggesting that the

“metal” channel resistance is negligible. We thus

conclude that the parasitic series resistance Rp of

our measurement system is around 25 Ω. After

subtracting the effect of parasitic series resistance

Rp (here we used Rp=20 Ω in Eq. (3) to avoid

possible overestimation of contact resistance) from

the retrieved Rc in Figure 1c, the gate voltage

dependent intrinsic contact resistance then is

obtained and shown in Figure 2c. Obviously the

minimum contact resistance at p-branch (Vbg= VDirac

-50 V) is about 82.7 Ω μm, which is much smaller

than all published values of contact resistance for

graphene/metal junction. Moreover the contact

resistance at p-branch is very close to the

theoretical limit, which is calculated based on

Landauer formula for an ideal metal/graphene

contact on 285 nm silicon oxide and plotted as the

red line in Figure 2c [3].

To further confirm the reliability of contact

resistance below 100 Ω um in graphene/metal

junction, we fabricated 6 sets of GFETs (denoted as

S1 to S6) based on mechanically exfoliated

graphene flakes. The original contact resistances

are extracted by TLM and plotted in Figure 2d, in

which the p-branch contact resistance Rcp (green

squares) at Vbg= VDirac-50 V and n-branch contact

resistance Rcn (red dots) at Vbg= VDirac+50 V are

respectively shown together with their standard

errors. The retrieved contact resistances of the 6

sets devices are quite uniform, i.e. Rcp locates

around 100 Ω μm and Rcn is distributed about 400

Ω μm. The minimum contact resistance Rc, i.e Rcp in

Figure 2d, are found to be between 89 to 140 Ω μm,

and 2 of them are below 100 Ω μm. After

calibration, i.e. removing 20 Ω parasitic series

resistance, the intrinsic minimum contact resistance

Rc (black stars) are seen to distribute between 69 Ω

μm to 120 Ω μm, and half of them show Rc below

100 Ω μm. In addition, we fabricated two more sets

of GFETs using chemical-vapor-deposition (CVD)

graphene, and the extracted minimum Rc is also

found to be about 100 Ω μm (Figure 2d, denoted as

C1 and C2). Details of the CVD graphene samples

are presented in the supporting information

(detailed in Figure S4 and S5). The experimental

results both on mechanically exfoliated and CVD

graphene showed that contact resistance between

graphene and metal can be lowered down to

sub-100 Ω μm at RT, and sometime even close to

the theoretical limit.

Temperature dependence of contact

resistance in graphene devices is controversial. For

example, Xia et al. reported that Rc is linearly

dependent on temperature and drops from 185 Ω

μm to 120 Ω μm as temperature decreases from 300

K to 6 K [3]. However, completely different results

were reported by other group, showing that Rc of

optimized graphene/metal contact is independent

of temperature [18]. Therefore it is necessary to

check the relation between temperature and contact

resistance of our graphene devices. We measured

the transfer characteristics of the fabricated GFETs

from RT (300 K) down to liquid nitrogen

temperature (77 K), and transfer characteristics of a

typical GFET with channel length of 1 um in

sample S1 are shown in Figure 3a. As expected, the

transfer characteristics become sharper near the

Dirac point voltage as the temperature is decreased,

which may be attributed to the enhanced carrier

mobility at lower temperature. Field-effect mobility

of holes is found to increase averagely from about 4,

000 cm2V-1s-1 to near 10, 000 cm2V-1s-1 as

temperature decreased from 300 K to 77 K owing to

the suppressed surface phonon scattering on SiO2

substrate [19]. As a comparison, fitted mobility (μFT,

after decoupling the effect of contact resistance) is

also found to increase from about 4, 500 cm2V-1s-1 to

near 12, 000 cm2V-1s-1 as shown in Figure 3b. It

should be noted that the fitted mobility is larger

than field-effect mobility owing to its decoupled

contact resistance, and the difference becomes

more obvious at lower temperature, showing that

the effect due to contact resistance is becoming

more important as temperature decreased. The bias


99 Nano Res.

dependent contact resistance Rc is retrieved

through TLM at each temperature (except for room

temperature, all the transfer characteristics were

measured continuously from 77 K to 250 K) and

shown in Figure 3c. It should be noted the Rc

values at different temperatures are tending to

converge to a constant at large gate bias, indicating

that the minimum contact resistance is in fact

independent of temperature. It is also found that Rc

at several temperatures becomes negative near the

Dirac point voltage, suggesting that the TLM

method is not valid in this region any more. The

reason behinds the failure of TLM could be the

contact-induced doping effect [20], i.e. the

gate-induced carrier density is not sufficient to

screen out charges transferred from metal contact

into graphene channel. The independence between

contact resistance and temperature is further

demonstrated by Figure 3d, which gives Rc-T

relation of all 6 groups of grapheme devices. It is

obvious that none of the 6 groups show clear

temperature dependence, which differs from the

Rc-T relation reported in Ref. [3] while similar to

that found in Ref. [18].

3 Discussion

Although using the same metal (Pd) to contact

graphene, this work is different from that reported

by Xia et al. [3] in two important aspects. (1) The

contact resistance is found here to be independent

of temperature, while it was reported to be linearly

dependent on temperature by Xia et al.; (2) The

reported values of graphene/metal contact

resistance by Xia et al. is much larger than that

realized in this work. To find out why our results

are so different from that reported by Xia et al., we

compare some key parameters between our results

and Ref. [3] and list them in Table 1. In our opinion,

quality of graphene, work function difference,

interaction between metal and graphene, and the

properties of interface are those decisive factors.

Firstly, high quality graphene samples are

used in this work which are found to remain high

quality even after device fabrication. Carrier

mobility and mean-free-path are used to

characterize the quality of graphene samples. Hole

mobility of our samples all above 4,000 cm2V-1s-1

(Figure 4a) at RT, which are much higher than the

mobility of about 2,000 cm2V-1s-1 at RT and 3,600

cm2V-1s-1 at 6 K in Ref. [3]. Furthermore our

samples have a lower density of residual charges

(n0) and much smaller Vdirac which is closer to zero

(besides tox is different), both of which reflect the

cleanness and high-quality of the graphene

samples used in this work. The averaged n0 (3.0~4.0

×1011 cm-2) and μFE (4,000~4,500 cm2V-1s-1) of our

samples are plotted in Figure 4a. And the surface of

our graphene samples is seen to be very clean (see

the AFM image displayed in Figure S2 of

supporting information). Higher carrier mobility

indicates longer mean-free-path, which in turn

suggests better carrier injection efficiency between

graphene and metal. The mean-free-path Lm of hole

in a typical device is about 80 nm at 300 K, and

increases to about 125 nm at 78 K as shown in

Figure 4b. The mean-free-path of hole in graphene

is one of the important facts that dominate the

transmission efficiency TMG between graphene and

metal [9]. The relation between transmission

efficiency Tmg and Lm as given in Figure 4c (details

on the calculation are given in Methods) shows that

a decrease of temperature leads to an increase in Lm

and thus an increase in Tmg. It should be noted that

the gradient of Tmg becomes smaller and smaller

with increasing Lm, indicating that the dependence

of Tmg (or Rc) on Lm will become very weak if Lm is

sufficient large. Owing to the long Lm realized in

our graphene samples, TMG varies only from 0.81 at

300 K to 0.87 at 78 K, suggesting only 7% change

for Tmg over the entire temperature range in our

measurements. With smaller Tmg as reported in Ref.

[3], i.e. 0.75 even at 6 K, Tmg shows more sensitive

dependence on Lm. Therefore the negligible

temperature independence found in our

experiments on metal/graphene contact resistance

is mainly resulted from the use of higher quality

graphene samples, which is consistence with those

reports on metal/graphene interfaces with long Lm.

Secondly, higher metal-induced doping

concentration in the graphene under contact is

observed in this work than that in Ref. [3] owing to

the clean interface and high-quality Pd film

deposited in high vacuum. While it is difficult to

give a quantitative description of this character, we

may deduce the picture from the following two


100 Nano Res.

observations. (1) Heavier doping leads to higher

degree of asymmetry in contact resistances, which

may be measured by the resistance ratio

Rratio=Rcn/Rcp, where Rcn and Rcp are respectively the

contact resistance of n- and p-branch at fixed gate

voltage. It is obviously that Rratio is as large as about

4 (Figure 2d) at |Vbg-VDirac|=50 V. As a comparison,

the ratio is much smaller in Ref. [3] (about 1.4, from

Figure 2c of Ref. [3]). Larger contact resistance at

n-branch than at p-branch is originated from the

Pd-induced hole doping concentration in graphene

under the metal, and the heavier of p-doping, the

larger of the asymmetric Rratio [15]. (2) There are

two contact resistance peaks in Figure 4d. The main

peak locates at |Vbg-VDirac|=0, corresponding to the

Dirac point of graphene in the channel, and the

second peak locates at Vbg-VDirac>0, corresponding

to the charge neutral point of graphene under Pd

contact. For the observation of the second

resistance peak, the Fermi level shift (ΔEF, using the

Dirac point as the reference) or charge doping

concentration must be sufficiently large for the

minor peak to be distinguished from the main peak.

Simultaneously, coupling strength cannot be too

strong to broaden the second peak from

observation. It was supposed the appearance of the

second peak means a Fermi level shift of more than

125 meV [21], while ΔEF is about 80 meV in Ref. [3].

The different coupling strength, also affected by the

metal contact, quality of graphene and interface

properties, could be the main reason, in our

judgment, that finally leads to above two

remarkable differences.

4 Conclusions

In conclusion, we attempted to lower the contact

resistance in graphene transistors and explored the

limit resistance between graphene and metal.

Through adopting highly pure Pd and high-quality

graphene, companied with clean interface, the

palladium/graphene contact resistance at RT has

been lowered to sub-100 Ω μm both on

mechanically exfoliated and CVD graphene. After

excluding the parasitic series resistances from

measurement systems and electrodes, the retrieved

contact resistances are shown to be systematically

and statistically below 100 Ω μm with the

minimum value of 69 Ω μm which is very close to

the theoretical limit. Furthermore the contact

resistances shows no clear dependence on

temperature ranged from 77 K to 300 K, and this is

attributed to the saturation of injection efficiency

between graphene and Pd owing to the sufficiently

long mean-free-path of carrier in the graphene

samples used in this work.

Methods: [Experiments]

Graphene flakes used in this work were

mechanically exfoliated onto the silicon substrate

with 285 nm thick of silicon oxide. In the devices

fabrication process, graphene flakes were firstly

etched into a 2-μm width strips using oxygen

plasma reactive-ion etching (RIE) with shield of

polymethyl methacrylate (PMMA), defined by

traditional electron-beam-lithography (EBL)

process. The windows for source/drain contacts

are patterned through another EBL process on

PMMA. Then, Pd/Au (30 nm/ 50 nm) metal layer

was deposited using electron-beam-evaporation

(EBE) under base vacuum of 1 × 10-8 Torr,

followed by a lift-off process. Electronic

measurements were carried out using Keithley

4200 SCS in vacuum (under pressure about 1×

10-3 Torr) at RT. Low temperature measurements

were performed in a cryogenic probe station

(Lakeshore TTP-4) using liquid nitrogen as

cooling gas.

[Theoretical limit of graphene/metal

contact resistance]

The theoretical limit of graphene/metal

contact resistance is calculated based on

Landauer formula, which is G=(4e2/h)TM. h is

Planck constant, e is elementary charge, and T

and M are separately the carrier transmission

efficiency and number of quantum modes. For an

ideal metal/graphene contact on 285 nm silicon

oxide, the transmission efficiency T=1. Number of


101 Nano Res.

quantum modes can be derived from the Fermi

level shift ΔEF, that is M=2(ΔEF/πhVF), VF is the

Fermi velocity. As the carrier density of graphene

channel is controlled by the 285 nm silicon oxide

back-gate, which is determined by ρ

=-Cox(Vbg-VDirac)=4πeΔEF|ΔEF |/(h2VF2). So, for a

certain back-gate voltage, there is certain net

carrier density which corresponding to a certain

number of quantum modes and limited

conductance or resistance.

[Parameter calculation]

Field-effect mobility is calculated using

μFE=gmL/(WVdsCox), where gm is the

transconductance, Cox is the back-gate capacitance,

Vds is the source-drain bias voltage, and L and W

are respectively the channel length and width.

Averaged mobility is the average of mobilities of

GFETs with different channel length in the same

set. Actual mobility of graphene could be slightly

higher than μFE, as contact resistance degrades

transconductance which leads to a degraded

mobility value. The usually used model [22],

fitting the experimental data using a single

mobility value μFT, takes the contact resistance

into account, but the results are compromised

between Rc and μFT, and the mobility is always

overestimated [23].

Mean free path Lm is calculated according to

Lm=σh/2e2kF, σ is the conductivity which is

obtained from the linear fit of transfer length

method, h is Planck constant, e is elementary

charge, and 𝑘𝐹 = √𝜋𝑛 is the Fermi wave vector,

where n is the net carrier density.

Transmission efficiency 𝑇𝑚𝑔 =

√𝐿𝑚/(𝐿𝑚 + 𝐿𝑚𝑔) is the carrier tunneling

probability between metal contact and graphene,

where Lmg=hvF/2π2η is the effective coupling

length and coupling strength η is assumed to be 5

meV.

Acknowledgements

This work was supported by the Ministry of

Science and Technology of China (Grant Nos.

2011CB933001 and 2011CB933002), and National

Science Foundation of China (Grant Nos. 61322105,

61271051, 61321001 and 61390504), and Beijing

Municipal Science and Technology Commission

(Grant Nos. Z131100003213021 and

D141100000614001).

Electronic Supplementary Material:

Supplementary material (Raman spectroscopy

measurements, AFM imaging, linearity

demonstration, details of CVD samples and SEM of

calibration structure) is available in the online

version of this article at

http://dx.doi.org/10.1007/s12274-***-****-*

(automatically inserted by the publisher).

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95 Nano Res.

Table 1 Comparison of key parameters retrieved with that reported in Ref. [3].

tox(nm) μ

(cm2V-1s-1)

n0

(×1011 cm-2)

Vdirac

(V)

ΔEF

(meV)

Rration Rc(Ω μm)

Ref. [3] 90 2000 5.0 23 < 100 1.2 185

This work 285 4000 3.5 -8.3 >125 3.5 104 (84)


Nano Res.

Figure 1. Measurements of contact resistance of palladium/graphene interface and parameter retrieval. (a) A set of

Rtotal from a group of GFETs versus back-gate voltage. Inset: typical SEM image showing the channel of a group

of GFETs. Channel width is 2 μm and channel length varies from 1 μm to 6 μm, with step of 1 μm, and the scale

bar denotes 2 μm. (b) Rsheet/W of graphene channel (black squares) and Rc extracted by TLM (red squares),

together with the standard errors, versus back-gate voltage after shifting the Dirac point voltage to zero. Rsheet is

divided by the channel width for convenient illustration. (c) Linearity of Rtotal of GFETs in set S1. Fitting curves of

i (i=2, 3, 4, 5 ,6) GFETs that define the up limit of Rint. (d) Transfer characteristics of a 500-nm GFET. The largest

on-current Imax is 323.9 μA, corresponding to a minimum total resistance Rmin of 154.4 Ω. L=0.5 μm, W =2 μm,

and Vds=0.05 V.

0 1 2 3 4 5 60

200

400

600

800

1000

1200

1400 6 GFETs

2 GFETs

3 GFETs

4 GFETs

5 GFETs

Rtotal

c

Rto

tal(

L(m)

At 300 K

Vbg

-Vdirac

=-50 V

-40 -20 0 20 40 600

200

400

600

800

1000

1200

1400

1600

Vbg

-Vdirac

(V)

Rs

he

et/W

(

m)

b

Rsheet

/W

Rc

0

200

400

600

800

1000

1200

1400

1600

Rc

At 300 K

-60 -40 -20 0 20 40 600

2000

4000

6000

8000

10000

1um

2um

3um

4um

5um

6um

Rto

tal (

)

Vbg

(V)

a

Set S1

At 300 K

Vds=0.05 V

-60 -40 -20 0 20 40 6050.0µ

100.0µ

150.0µ

200.0µ

250.0µ

300.0µ

350.0µ

Vbg

(V)

I ds(A

)

100

200

300

400

500

600

700

Rto

tal (

)

Imax=323.9 A

Rmin=154.4

d


Nano Res.

Figure 2. Model and retrieved parameter statistics. (a) A schematic of the measured Rtotal, Rtotal=2Rc/Wc+

Rsheet/W×L+Rp. Definition of Rc is shown in the red dash rectangle. (b) Measured Rp of metal ‘devices’ with

different channel length. Inset: SEM image of the metal ‘channels’. Scale bar denotes 2 μm. (c) Comparison

of experimental contact resistance to the ideal G/M graphene. Red line, contact resistance in an ideal

metal-graphene contact on 285 nm oxide. (d) Minimum Rc in the n branch (red dots) and p branch (black

squares) from all sets of our graphene samples, including exfoliated graphene (denoted as S) and CVD

graphene (denoted as C) samples. The black starts represent the final Rc in p branch after excluding Rp in

DC measurement system. The dash lines are 400 Ω μm (red) and 100 Ω μm (black) respectively.

1 2 3 4 5 60

5

10

15

20

25

30

35

40

45

50

Rp(

)

Lm(um)

Rp1

Rp2

b

-40 -20 0 20 400

400

800

1200

1600

Rc(

m

)

Vbg

-VDirac

(V)

experiment

simulation

c

S1 S2 S3 S4 S5 S6 C1 C20

100

200

300

400

500

600

Rcp

Rcn

Rc

Rc(

m

)

Graphene Samples

d

At 300 K

Vbg

-Vdirac

=50 V


Nano Res.

Figure 3. Temperature dependence of graphene/metal contact resistance. (a) Typical back-gate transfer

characteristics of a 1-μm GFET under different temperatures. (b) Averaged μFE (red dots) and μFT (black

squares) versus T. (c) Rc as a function of back-gate voltage under different temperatures. (d) Rc from all sets

of GFETs under finite back-gate voltage bias versus temperature T.

-60 -40 -20 0 20 40 600

500

1000

1500

2000

2500 300 K

250 K

200 K

150 K

110 K

77.5 K

Rto

tal(

)

Vbg

(V)

L=1 m

Vds

=0.05V

a

-60 -40 -20 0 20 40 60-400

-200

0

200

400

600

800

1000

1200

C

300K

250K

200K

150K

110K

77.5K

Rc(

m

)

Vbg

-Vdirac

(V)

S1

50 100 150 200 250 300

4000

6000

8000

10000

12000

14000

FT

FE

cm

2V

-1s

-1)

T (K)

b

50 100 150 200 250 30060

80

100

120

140

160

180

200

S1 S2 S3

S4 S5 S6R

c(

m

)

T (K)

d

Vbg

=VDirac

-50V


Nano Res.

Figure 4. Retrieved materials and device parameters. (a) Average residual carrier density n0 and

field-effect mobility μFE of our GFETs at room temperature. (b) The temperature dependent hole

mean-free-path in a typical graphene device at Vbg=VDirac -50 V. (c) Mean-free-path dependent Tmg. (d) Rc

of GFETs in set S2 as a function of (Vbg-Vdirac). The red arrow points to the second peak in the red box of

the Rc-(Vbg-Vdirac) curve, which corresponds to the Dirac point of graphene under metal contact.

-60 -40 -20 0 20 40 600

200

400

600

800

1000

1200

S2

Rc(

m

)

Vbg

-VDirac

d

S1 S2 S3 S4 S5 S63,500

4,000

4,500

5,000

5,500

uF

E(c

m2V

-1s

-1)

Graphene samples

S1 S2 S3 S4 S5 S6

3.0

3.5

4.0

4.5

5.0

n0(1

01

1cm

-2)

a

0 50 100 150 2000.0

0.2

0.4

0.6

0.8

1.0

TMG

=0.81

RT

Tm

g

Lm(nm)

TMG

=sqrt(m+)

Xia's at 6 K

TMG

=0.87

77K

c

50 100 150 200 250 30080

90

100

110

120

130

T (K)

Lm (

nm

)

|Vbg

-VDirac

|=50 V

n3.7811012

cm-2

d


Nano Res.

Electronic Supplementary Material



Hua Zhong, Zhiyong Zhang(), Bingyan Chen, Haitao Xu, Dangming Yu, Le Huang and Lian-Mao

Peng()

Supporting information to DOI 10.1007/s12274-****-****-* (automatically inserted by the publisher)

RAMAN SPECTRUM:

Figure S1. Raman spectrum obtained from a mechanically exfoliated graphene. The

intensity ratio of 2D peak to G peak is about 2 and no D peak is observed, implying that

the graphene sample is single layer and of high quality without defects. Laser with

wavelength of 633 nm is used.

1000 1500 2000 2500 30000

500

1000

1500

2000

Inte

nsit

y (

a.u

.)

Raman Shift (cm-1)


Nano Res.

ATOMIC FORCE MEASUREMENT:

LINEARITY DEMONSTRATION:

Figure S3. Due to variations from device to device, linear fit of different GFETs leads to

different intercepts. For graphene sample S1, 6 GFETs in total, there exist 57 possible

combinations, most of the intercepts (48/57) locate around 100±20 Ω. Only a few of them

are far away from the center, for just 2 or 3 GFETs are used for linear fit. The concentrated

distribution shows that GFETs in device group S1 are quite uniform.

0.1

1

10

40

70

95

99.520 40 60 80 100 120

20 40 60 80 100 1200

4

8

12

16

20

24

Co

un

ts

Rint

()

Cu

mu

lati

ve C

ou

nts

Figure S2. AFM image showing the graphene channel. Height of the graphene layer is

about 1 nm, confirmed the single layer property of our graphene samples. Though, AFM is

the last characterization step, the surface of the graphene channel is still quite smooth and

clean. Width of the graphene channel is about 2 μm.


Nano Res.

CHEMICAL-VAPOR-DEPOSITION GRAPHENE SAMPLES: graphene was grown on polycrystalline

platinum surface and then transferred into the SiO2/Si substrate using polymethyl methacrylate (PMMA)

600K as sacrificial layer.[1,2] GFETs were fabricated using the same process flow as described in the main text,

etched into 2-μm width strip first and then the deposition of metal contact (Pd/Au 30/20 nm). The transfer

characteristics of 5 GFETs were measured in vacuum at room temperature (see left of Figure S4). Quality of

CVD graphene is great, though not as well as mechanically exfoliated graphene, Dirac point voltages are

around 0.7±1.1 V, and field-effect mobility of holes is above 3,000 cm2V-1s-1. Contact resistance were

extracted by transfer length methods as well, as plotted in the right of Figure S4. The minimum Rc is 124.6±

37.9 Ω μm in the p branch and 238.2±27.1 Ω μm in the n branch.

WHOLE VIEW OF THE MEASURED GFETS AND CALIBRATION STRUCTURE:

Figure S5. SEM images of the measured GFETs and calibration structure. Left: A set of

GFETs with channel with of 2 μm. Right: Calibration structure as the same as measured

GFETs only with the 2-μm graphene channel replaced with 4-μm metal line. All those

metal layers were deposited at same time. Scale bar is 50 μm.

Figure S4. CVD graphene sample. Left: transfer characteristics of 5 GFETs based on CVD

graphene sample, source-drain bias voltage was 0.05 V. Right: The extracted Rc (black

squares) as a function of back-gate voltage. Red caps shown the standard errors.

-60 -40 -20 0 20 40 600

100

200

300

400

500

600

700

800

900

1000

1100

Rc(

m)

Vbg

-Vdirac

(V)-60 -40 -20 0 20 40 60

0.0

20.0µ

40.0µ

60.0µ

80.0µ

100.0µ

120.0µ

140.0µ

160.0µ

180.0µ

I ds(A

)

Vbg

(V)

1um

2um

3um

4um

5um

Vds

=0.05 V


Nano Res.

[1] Gao, L. B.; Ren, W. C.; Xu, H. L.; Jin, L.; Wang, Z. X.; Ma, T.; Ma, L. P.; Zhang, Z. Y.; Fu, Q.; Peng, L. M.; Bao, X. H.; Cheng, H.

M., Repeated growth and bubbling transfer of graphene with millimeter-size single-crystal grains using platinum. Nat. Commun. 2012, 3,

699.

[2] Xu, H. L.; Zhang, Z. Y.; Shi, R. B.; Liu, H. G.; Wang, Z. X.; Wang, S.; Peng, L. M., Batch-fabricated high-performance graphene

Hall elements. Sci. Rep. 2013, 3.

Address correspondence to Zhiyong Zhang, [email protected]; Lian-Mao Peng, [email protected]

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