recent developments in sige and cmos phased...

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Recent Developments in SiGe and CMOS Phased Arrays Recent Developments in SiGe and CMOS Phased Arrays for MillimeterWave Applications Prof . Gabriel M. Rebeiz ECE Department University of California San Diego University of California, San Diego Tel: 8583363186 [email protected] Supported by DARPA, USARL, Intel and Toyota 1 Phoenix Talk – April 2012 – © UCSD

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Recent Developments in SiGe and CMOS Phased ArraysRecent Developments in SiGe and CMOS Phased Arrays for Millimeter‐Wave Applications

Prof. Gabriel M. RebeizProf. Gabriel M. Rebei

ECE DepartmentUniversity of California San DiegoUniversity of California, San Diego

Tel: 858‐336‐[email protected]

Supported by DARPA, US‐ARL, Intel and Toyota

1Phoenix Talk – April 2012 – © UCSD

Telecom. Integrated Circuitsand Systems Lab (TICS)

6307 EBU‐1 – UCSD(state of the art labs till 600 GHz)

Gabriel M. RebeizProfessor

21‐22 graduate students21 22  graduate studentsand post‐doctoral fellows(one of the largest groups in the US)

Millimeter‐wave RFICsPhased ArraysAutomotive Radars94 GHz Imaging Arrays94 GHz Imaging ArraysRF MEMS Devices‐Tunable Filters‐Tunable AntennasA t hi

2Phoenix Talk – April 2012 – © UCSD

Antennas on‐chipTHz Systems

US-NAVY Radar/Communication Phased Arrays

$250/ l t i ll G A t•$250/element using all GaAs components. • Reduced to $25/element using SiGe!!

3Phoenix Talk – April 2012 – © UCSD

US-NAVY Radar/Communication Phased Arrays

4Phoenix Talk – April 2012 – © UCSD

Why so Expensive? T/R module dominates the cost!!

T/R d l b ilt i di t t (MMIC )• T/R module built using discrete components (MMICs)• Low level of integration used• Assembled “one by one” in highly isolated cavities• High power transmit functions increase the cost ($1000+/element)• High power transmit functions increase the cost ($1000+/element)• Phased arrays are used for radars onlyMust change T/R modules for low‐cost arrays!!!

5Phoenix Talk – April 2012 – © UCSD

More attempts at lowering the cost still DO NOT HELP(LM X-band Phased Array - IEEE PAS 2010)

•GaAs circuits are huge per function (except PA and low noise LNA)•GaAs circuits need a dedicated silicon

2-channel GaAs chip

•GaAs circuits need a dedicated silicon controller per chip!•Takes a lot of space between antennas

SiGe chip

6Phoenix Talk – April 2012 – © UCSD

SiGe chip

Jazz SBC18HA/2/3 and IBM 8HP Metal Stacks

2.81 m

2 m

1.59 m

29.65 m

2 m

0.62 m0.8 m

0.52 m

Transistors are here

Hi h f d f i• High ft and fmax transistors• SiGe and CMOS available• 7‐9 metal layers• Inductors, MIM capacitors, resistors

7Phoenix Talk – April 2012 – © UCSD

, p ,• extremely high yields

SiGe/CMOS Phased Array Backends

• High degree of complexity on a chip: multiple channels + controller

• Potential to greatly reduce complexity and cost of phased arrays

• Results in much more space for the PAs and power supplies

8Phoenix Talk – April 2012 – © UCSD

Results in much more space for the PAs and power supplies

Phased Arrays for Comm. and Low Power Radars

• When cost is reduced…

DBS links on planes (K/Ka band)‐DBS links on planes (K/Ka‐band)

‐Point‐to‐point links for base stations (20 GHz, 38 GHz, E‐band)

‐60 GHz systems for personal wireless (WPAN) – Lots of work

‐77 GHz Automotive radars

‐Weather radars

GOAL: Reduce phased array cost‐GOAL: Reduce phased array cost using silicon integration (SiGe, CMOS). Many application areas!!

9Phoenix Talk – April 2012 – © UCSD

Raytheon Single Panel X-Band SiGe Phased Array • Weather radar (100‐200 mW per element)( p )• All SiGe, plastic packaged, multi‐layer panels.• Raytheon got the 1‐10 M element AF ISSYS program based on SiGe.

10Phoenix Talk – April 2012 – © UCSD

All-RF Beamforming Architecture

(Traditional Architecture – since WWII)• Pattern synthesized before receiver. High SIR achieved.

RF phase shifter required and RF combiner required• RF phase shifter required, and RF combiner required• Most used architecture today by all defense systems• Most prevalent architecture even in commercial systems (SiBeam, IBM,

IMEC Intel MTK all defense companies etc )

11Phoenix Talk – April 2012 – © UCSD

IMEC, Intel, MTK, all defense companies, etc.).• Pioneered by UCSD using SiGe!!

InterfererPhase

Mixer-based Architectures (not used)

LNARF

Interferer

PhaseShifter VGA

RXPhase VGA

LNARF

InterfererShifter VGA

IF Phase ShiftingLO Phase Shifting

• Mixer “sees” all interferes. • Mixer is DSB bad for hetorodyne systems (interferers)• Mixer is DSB… bad for hetorodyne systems (interferers).• Cannot scale to large arrays!• Complicated for multiple beam systems (cannot place beams on same frequency).• Does not have the simplicity of All-RF or the advantages of digital beamforming.

12Phoenix Talk – April 2012 – © UCSD

Worse of both worlds!!!

12

TYPE 1: Communications Weather Radar Perimeter Detection

Three Types of Phased ArraysTYPE 1: Communications, Weather Radar, Perimeter Detection, Imaging radars, automotive radars, etc. (30‐100 mW per element on Tx): Can be done in SiGe + low power GaAs. Large number of panels. Large commercial interest. $30/element to $1/element (no GaAs)!! High degree of integration. LOTS OF COMPANIES HERE!!

TYPE 2: Communications on ships (medium linearity), ISR, etc: Can be done using SiGe + medium power GaAs. $50‐100/element. Need to take into account heat transfer Lots of companies tooto take into account heat transfer. Lots of companies too.

TYPE 3: Fire Control, High Power Per Element, High linearity, EW, ECM, (3‐10+W per element): Very costly. GaN is taking over. SiGemay help. Raytheon, LM, Boeing and NG. Much smaller market than Type 1 and Type 2! 

13Phoenix Talk – April 2012 – © UCSD

yp yp

• UoM started using GaAs and planar technology in the early 1990’s at W‐band in

Timeline for SiGe/CMOS Phased Array Development• UoM started using GaAs and planar technology in the early 1990 s at W‐band in Prof. Rebeiz group for IF beamforming. 4‐element arrays demonstrated.

• UoM (UCSD) and Boeing started using SiGe in 2002/2003 (Prof. Rebeiz group) for All RF beamforming Single element demonstrated in 2003 & 2004 at 12 GHzAll‐RF beamforming. Single‐element demonstrated in 2003 & 2004 at 12 GHz.

• Caltech started in 2003 on LO beamforming. 4‐element LO beamformingdemonstrated in 2004 and 2005 at 24 GHz and 77 GHz.

d d f l ll b f h d• UCSD demonstrated first 8‐element All‐RF beamforming phased array in 2006 and 2007 (6‐18 GHz).

• UCSD demonstrated first 16‐element All‐RF beamforming phased array in 2007 and 2008 (45 GHz).

• IBM, MTK, SiBeam, Intel followed with 16‐32 element phased arrays using All‐RF beamforming.

• Others (Toshiba, NEC, IMEC, ST, NTU, KAIST, etc.) followed with 4‐16 element phased array using All‐RF, LO and IF beamforming.

• UCSD demonstrated first 4‐element and 16‐element phased arrays at 80 GHz.

14Phoenix Talk – April 2012 – © UCSD

p y

• Today, All‐RF beamforming is the most common architecture used to‐date.

15Phoenix Talk – April 2012 – © UCSD

SiBeam 32Tx/4Rx 60 GHz Phased Array (CMOS)

16Phoenix Talk – April 2012 – © UCSD 16

IBM 16-Element 60 GHz Tx Phased Array (SiGe)

17Phoenix Talk – April 2012 – © UCSD

Intel 32-Element 60 GHz Tx/Rx Phased Array

• Based on work with UCSD (we helped them a lot)• Flip-chip packaging – CMOS from TSMC.

18Phoenix Talk – April 2012 – © UCSD

• Does not contain baseband circuitry for Gbps communications

Bosch paper MTT March 2012MTT March 2012

MRR (DBF)

19Phoenix Talk – April 2012 – © UCSD

Bosch is interested in phased arrays and looking at them with DICE/Infineon

SiGe/CMOS UCSD Phased Array Chips (8 to 85 GHz)

20Phoenix Talk – April 2012 – © UCSD

RF Architecture for the 6-18 GHz Silicon Receiver

21Phoenix Talk – April 2012 – © UCSD

Performance of UCSD 8‐Element Array Chip 

9 – 15 GHz

• 2.5 x 2.2 mm2

Ch l i 20 +/ 1 dB• Channel gain: 20 +/‐ 1 dB• NF: 4.2 – 4.7 dB (10‐14 GHz)• RMS phase & gain error : 

6° d 0 7 dB (6 18 GH )

22Phoenix Talk – April 2012 – © UCSD

< 6° and < 0.7 dB (6‐18 GHz)

Measured Mismatch between Channels(comparison of 8x16=128 S-Parameters!)

23Phoenix Talk – April 2012 – © UCSD

Measured Isolation between all Channels

24Phoenix Talk – April 2012 – © UCSD

8‐Element X/Ku‐Band Array on a Teflon Board

10 cm10 cm

6 cmDe-coupling R-C banksGnd plane 

edge

DummyElement50 Ω load

ESDstub

6 cm

Si-Chip

Silicon Chip

Output port Bias & Control Lines

Rogers RT58802 2 h 10 il

Output port Bias & Control Lines

25Phoenix Talk – April 2012 – © UCSD

εr = 2.2,  h = 10 mils

R C Supply DecouplingDigital Control

X/Ku‐Band Chip On‐Board Packaging

R‐C Supply DecouplingDigital Control

Ant # 1 Ant # 8

VCC5 mm

26Phoenix Talk – April 2012 – © UCSD

Output Port5 mm

X/Ku‐Band Chip On‐Board Packaging

Digital control lines

VCC VCC

Digital control lines

Ant # 4 Ant # 5

VCC VCC

Chip size :Ant # 3

Ant # 2

Ant # 6

Ant # 7

Chip size :2.5x2.2mm2

Ant # 1 Ant # 8

• >35 ground bondwires – Full HFSS simulations on 3‐D package

Output PortVCC

27Phoenix Talk – April 2012 – © UCSD

>35 ground bondwires  Full HFSS simulations on 3 D package

• 3 supply nodes with decoupling capacitors

Measured Patterns at 12 GHz

15°1519°

26°

• Element factor causes 3‐4 dB drop at 60°

28Phoenix Talk – April 2012 – © UCSD

• Excellent agreement with simulations

X‐Band Phased Array RX: 4 elements

29Phoenix Talk – April 2012 – © UCSD

Measured Gain and Phase Response

30Phoenix Talk – April 2012 – © UCSD

Measured Linearity (‐12 dBm P1dB)

• High linearity achieved P1dB= 11 to 12 dBm IIP3: 3 dBm to 4 dBm• P1dB=-11 to -12 dBm, IIP3: -3 dBm to -4 dBm

• Power is 36 mW per channel (only!!!)• NF is 3.5 dB (only!!)

31Phoenix Talk – April 2012 – © UCSD

Proposed receiver array implementation

• Single PCBSingle PCB integration for antenna arrays and active devicesactive devices

• Single RFIC for 4 RF channelschannels

• Antenna size5 8’ x 3 5’5.8  x 3.5Directivity ~ 22 dBHPBW ~ 25 deg HPBW ~ 12 5 degHPBW ~ 12.5 deg

• +/‐ 45 degrees l t i i

32Phoenix Talk – April 2012 – © UCSD

electronic scanning in azimuth plane

Hardware – Antenna Array (front)

”3.45”

4 15”4.15

33Phoenix Talk – April 2012 – © UCSD 5.8”

Hardware – Antenna Array (back)

Active array Passive arrayActive arraywith RFIC integration

Passive arrayfor verification

4‐way split network for dembedding its line

34Phoenix Talk – April 2012 – © UCSD

4 way split network, for dembedding its line losses from the passive array (1.6 dB losses)  

2- Antenna Quad-Beam Phased Array Receiver11-15 GHz Operation (Jazz SBC18HXL)

•This chip simultaneously receives incoming signals in 4 different directions and at four different frequencies (10 -16 GHz).

35Phoenix Talk – April 2012 – © UCSD

• Excellent for SATCOM. Replaces 8 GaAs chips and 4 silicon chips.

4-Simultaneous Beam Chip Photograph

Address EN DATA Bias GND VDD GNDVDD

LNAB

Array Decoder

2

Array Decoder

1

Ant. 1Input

2 CH

Ant. 2Input

Phase ShifterVGA

Single Channel 2-CH 1:4 Distribution network

• Jazz 0.18-μm BiCMOS, SBC18Hx• Power consumption: 3 5 V 520 mA

GNDVDD B4B1 B2B3 GND VDD

36Phoenix Talk – April 2012 – © UCSD

Power consumption: 3.5 V, 520 mA• Size: 2.4 x 4.3 mm2

On-Chip BIST for Low Cost Phased Arrays

• Half of the cost is testing cost Greatly reduce testing cost!Half of the cost is testing cost. Greatly reduce testing cost!• Use couplers on input and output to measure gain• Use integrated I/Q receivers on‐chip• Directional couplers < 0 1g with good directivity

37Phoenix Talk – April 2012 – © UCSD

• Directional couplers < 0.1g with good directivity.

X-band Phased Array Channel

38Phoenix Talk – April 2012 – © UCSD

• Standard X‐band 5‐bit phased array channel

Comparison of S-Parameter Data vs. BIST

39Phoenix Talk – April 2012 – © UCSD

f=10.25 GHz

More Comparison

• RMS gain and phase:• RMS gain and phase: Amazing agreement

• Frequency response at different states

40Phoenix Talk – April 2012 – © UCSD

Time Domain Measurements

• BIST can be done at 1 MHz rate with very high accuracy. Arrays can be tested at < 1 ms

41Phoenix Talk – April 2012 – © UCSD

16 Element Tx/Rx Array: 45-50 GHz

16-Elements T/R chip4 5x5 mm24.5x5 mm4-Bit Phase Control5-bit Gain Control (10 dB)Gain: ~6 dB (Tx), 3 dB (Rx)RMS Ph E 6RMS Phase Error: < 6o

RMS Gain Error: < 0.6 dBNF: 10 dBIP1dB: -10 dBm (Rx)( )OP1dB: +6 dBm (Rx)OIP3: +21 dBm (Rx)OPSAT: +6 dBm (Tx)Ch to Ch Isolation: < 35 dBCh-to-Ch Isolation: < -35 dBTx Power Cons: 1.1 WRx Power Cons: 0.9 W

42Phoenix Talk – April 2012 – © UCSD

16-Element Phased Array Chip Architecture

High linearity front-end

Bi-directional, passive 16:1 combiner/splitter for16:1 combiner/splitter for

high-linearity

Symmetrical chip architecture makes it easier for layout

43Phoenix Talk – April 2012 – © UCSD

Testing of Chip: DC Mounting/RF Probing

• Chip is mounted on a PC Board for DC/Bias

44Phoenix Talk – April 2012 – © UCSD

p• RF probes used for testing

VGA and rms Gain Error Reduction

VGA phase does not change with gain controlchange with gain control

VGA can be used to reduce rms gain error

45Phoenix Talk – April 2012 – © UCSD

Measured Phase Response

46Phoenix Talk – April 2012 – © UCSD

Same for Transmit and Receive. Frequency shift to ~50 GHz.

Measured 4 Channels

RX TXRX TX

Nearly identical results for the 4 channels vs. phase state and freq.

47Phoenix Talk – April 2012 – © UCSD

Teledyne/UCSD 44 GHz T/R Phased-Array Subarray Tile

• A photomicrograph of a Teledyne’s 44 GHz transmit and receive phased-array subarray tile.

• The λ/2 element spacing results in a very compact 13.6 x 13.6 mm2 size with a total fthickness including patch radiators of only 1100 μm.

Interposer with antenna attached0 15345 TX: SMART23-4F H-plane Gain te pose t a te a attac ed

-20

-10

0

0 1530

45

60300

315

330345

-40

-30 75

90

105255

270

285

-40

30

-135DEG -90DEG 105

120

135

150210

225

240

255-30

-20

-10

0

-45DEG 0DEG 45DEG 90DEG 135DEG

48Phoenix Talk – April 2012 – © UCSD

150165180195

210

Wafer Scale Approach

• Wafer‐scale arrays on silicon 

Q i i l bi i• Quasi‐optical power combining:

‐ No loss due to scaling 

‐ Can grow to 8x8 elements (>1.5 W)

Compatible with phased arrays and• Compatible with phased arrays and 

FMCW Radars

Copper heat sink

49Phoenix Talk – April 2012 – © UCSD

W‐Band High‐Efficiency RFIC Antennas

W = 690 μmL = 970 μm

91-99 GHz

50Phoenix Talk – April 2012 – © UCSD

3x3 W‐Band Power Amplifier Transmit ArrayAdditional Ground/Vcc pads

Si

Additional Ground/Vcc padsDC BIA

Size: 7.3 x 6.6 mm2

PADS / R

RF Input

RC BLOCCKS

Quartzalignment

51Phoenix Talk – April 2012 – © UCSD

gmarker

3x3 W‐Band Power Amplifier Transmit Array

Quartz DC BIA

Quartzedge

PADS / RRC BLO

C

RF Input

CKS

52Phoenix Talk – April 2012 – © UCSD

Array Pattern Measurements28° 28°94 GHz28 28

E l H lE‐plane H‐plane

SimulatedMeasured

• Excellent agreement with simulations

• HPBW = 28° (both E & H‐planes)

53Phoenix Talk – April 2012 – © UCSD

HPBW   28 (both E & H planes)

Measured EIRP – Array

2.0 V

1.7 V

22

PGPEIRPGGP RR

• EIRP > 34 dBm at 90 – 99 GHz (@ 2.0 V)

44

RG

GPEIRPR

GGP R

TTRTT

54Phoenix Talk – April 2012 – © UCSD

• Max EIRP = 35 dBm at 94‐96 GHz (@ 2.0 V)• Total Radiated power from array: 200 mW

Conclusions

•We are the leading group in phased array RFIC development .

•We have built ideal‐performance phased arrays on a single chip from 6 GHz to 120 GHz both in CMOS and SiGe BiCMOSfrom 6 GHz to 120 GHz both in CMOS and SiGe BiCMOS. 

• Several large DoD programs have been initiated due to our work. 

W k h t iti d t US D D i d th•Work has transitioned to many US DoD companies and they are building real phased arrays based on this technology.

•We continue to lead in this technology with wafer‐scale phasedWe continue to lead in this technology with wafer scale phased arrays and BIST systems.

•We are now investigating high linearity systems, lower cost packaging, more integration, etc. 

• It has been a good 6 years!!!!!

55Phoenix Talk – April 2012 – © UCSD

References– K. Koh and G. M. Rebeiz, “An X‐ and Ku‐Band 8‐Element Phased‐Array Receiver in 0.18‐μm SiGe BiCMOS

Technology,” IEEE J. Solid State Circuits, Vol. 43, No. 6 (June 2008), pp. 1360‐1371. – T. Yu and G. M. Rebeiz, “A 22‐24 GHz Phased Array Receiver with On‐Chip Coupling Characterization,” IEEE J. Solid , y p p g ,

State Circuits, Vol. 43, No. 9 (September 2008), pp. 2134‐2142. – B. Min and G. M. Rebeiz, “Single‐Ended and Differential Ka‐Band BiCMOS Phased Array Front‐Ends,” IEEE J. Solid 

State Circuits, Vol. 43, No. 10 (October 2008), pp. 2239‐2250. – K. Koh and G. M. Rebeiz, “A Millimeter‐Wave (40‐45 GHz) 16‐Element Phased‐Array Transmitter in 0.18‐μm SiGe

BiCMOS Technology ” IEEE J Solid State Circuits Vol 44 No 5 (May 2009) pp 1498 1509BiCMOS Technology,  IEEE J. Solid State Circuits, Vol. 44, No. 5 (May 2009), pp. 1498‐1509.– D. W. Kang and G. M. Rebeiz, “Single and 4‐Element Ka‐Band Transmit/Receive Phased Array Silicon RFICs with 5‐Bit 

Amplitude and Phase Control,” IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 12 (December 2009), pp. 3534‐3543.

– D. W. Kang, K. J. Koh and G. M. Rebeiz, “A Ku‐Band 2‐Antenna 4‐Simultaneous Beams SiGe BiCMOS Phased Array Receiver,” IEEE Transactions on Microwave Theory and Techniques, Vol. 58, No. 4, pp. 771‐780, April 2010.

– B. Cetinoneri, Y. Atesal and G. M. Rebeiz, “An 8x8 Butler Matrix in 0.13um CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 2, pp.295‐310, Feb. 2011.

– Y. Atesal, B. Cetinoneri and G. M. Rebeiz, “A Two‐Channel 8‐20 GHz SiGe BiCMOS Receiver with Selectable Intermediate Frequencies for Phased‐Array Digital Beamforming Applications ” IEEE Transactions on MicrowaveIntermediate Frequencies for Phased Array Digital Beamforming Applications,  IEEE Transactions on Microwave Theory and Techniques, vol. 29, no. 3, pp. 716‐726, March 2011.

– Y. Atesal, B. Cetinoneri, M. Chang, R. Alhalabi and G. M. Rebeiz, “Millimeter‐Wave Wafer‐Scale Silicon BiCMOSPower Amplifiers Using Free‐Space Power Combining,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 4, pp. 645‐655, April 2011.

h d b “ h d l h d h d– D. Shin and G. M. Rebeiz, “A Low‐Power High‐Linearity X‐Band 4‐Element Phased Array Receiver: CMOS Chip and Packaging,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 8, pp. 2064‐2072, August 2011.

– O. Inac, D. Shin and G. M. Rebeiz, “A Phased Array Chip with Built‐In Self‐Test Capabilities,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 1, pp. 139‐148, Jan. 2012. 

– S. Y. Kim and G. M. Rebeiz, “A Low Power Silicon BiCMOS Phased Array Receiver for 76‐84 GHz Radar and

56Phoenix Talk – April 2012 – © UCSD

S. Y. Kim and G. M. Rebeiz,  A Low Power Silicon BiCMOS Phased Array Receiver for 76 84 GHz Radar and Communication Systems,” IEEE J. Solid‐State Circuits, vol. 47, no. 2, pp. 359‐367, February 2012.

– C. Y Kim, D. W. Kang, and G. M. Rebeiz, “A 42‐50 GHz 16‐Element SiGe BiCMOS High‐Linearity Transmit/Receive Phased Array,” IEEE Trans.s on Microwave Theory and Techniques, vol. 60, no. 3, pp. 730‐742, March 2012.