reconfigurable architectures ese 566. outline static and dynamic configurable systems –static...
DESCRIPTION
Static vs. Dynamic Configurable Systems Static: –Improves performance for a given task (coprocessor) –Optimize the utilization of the resources (task division) Dynamic –To adapt to changing/incomplete specifications –Eliminate human designTRANSCRIPT
Reconfigurable architecturesReconfigurable architectures
ESE 566
OutlineOutline
• Static and Dynamic Configurable Systems– Static
• SPYDER, RENCO– Dynamic
• FIREFLY, BIOWATCH
• PipeRench: Reconfigurable Architecture and Compiler
Static vs. Dynamic Static vs. Dynamic Configurable SystemsConfigurable Systems
• Static: – Improves performance for a given task
(coprocessor)– Optimize the utilization of the resources (task
division)• Dynamic
– To adapt to changing/incomplete specifications– Eliminate human design
SPYDER: reconfigurable SPYDER: reconfigurable processor development systemprocessor development system
• Static (performance) reconfigurable coprocessor
• Fixed control unit• Reconfigurable processing unit• Compiler:
– Generates FPGA configuration from user-described operators
– User writes application
SPYDER architectureSPYDER architecture
Speed improvementSpeed improvement
• Conway’s Game of Life– SPYDER, 8MHz:SPYDER, 8MHz:
• 115 mill. cells/sec115 mill. cells/sec– SPARC, 85MHz:SPARC, 85MHz:
• 6.5 mill. cells/sec6.5 mill. cells/sec
RENCO: reconfigurable RENCO: reconfigurable network computernetwork computer
• Static (performance)• DOWNLOAD:
– Application– Optimal Processor Configuration
RENCO architectureRENCO architecture
FIREFLY machineFIREFLY machine
• Dynamic• Evolutionary algorithms <=> evolvable
hardware (evolware)• Cellular automata:
– Array of cells (1D, 2D, 3D);– Interaction rule: state of one cell determined by
neighbors states => rule table
FIREFLY machine (cont’d)FIREFLY machine (cont’d)
• 1-D cell array, 56 cells• 1 cell : D Flip-Flop + combinational logic• Cell n state = f(Cell n-1, Cell n , Cell n+1)• f= reconfigurable
FIREFLY machine: ImplementationFIREFLY machine: Implementation
PerformancePerformance
• Task: synchronization starting from random configuration
• Workstation: 60 configs/s• FIREFLY: 13,000 configs/s @ 1MHz
BioWatchBioWatch• Embryonic electronics: self repair, self
replication circuits• BioWatch: seconds/minutes• Cells: modulo-6, modulo-10• Gene: subprogram of the cell• Genome: the set of genes• Each cell stores the entire genome, but uses
only 1 gene => can replace another cell
Self replication
Self repair
PipeRenchPipeRench
• Reconfigurable datapath for accelerating numerically intensive applications
• Virtualized hardware• Dynamic reconfiguration• Application portability and scalability
without redesign or recompilation
Types of RHTypes of RH
• FPGAs: bit-level logic functionality(the basic processing elements compute on 1 bit)
• word-based architectures: PipeRench (CMU)(basic PE operates on 8 bits)(basic PE is a small ALU)
• coarse architectures: RAW (MIT)(basic PE is a MIPS 2000 core)
What is pipeline What is pipeline reconfiguration?reconfiguration?
• Split application in N pipelined stages• Use one piece of reconfigurable hardware
for all N stages• Reconfigure and feedback at each clock
cycle (extreme case)
Pipeline reconfigurationPipeline reconfiguration
Hardware VirtualizationHardware Virtualization
Instructionscurrently in hardware
Instructions paged out
Actual availablehardware
Prog
ram
PipeRench architecturePipeRench architecture
Processing Element Processing Element ArchitectureArchitecture
Speed Improvement Speed Improvement @100MHZ@100MHZ
Speed Improvement (cont’d)Speed Improvement (cont’d)
BibliographyBibliography• E. Sanchez et al., “Static and Dynamic
Configurable Systems”, IEEE Transactions on Computers, June 1999, pp. 556- 564
• Seth Copen Goldstein et al., “PipeRench: A Reconfigurable Architecture and Compiler”, IEEE Computer, 2000, pp. 70-76
• H. Schmit et al., “PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology”, IEEE 2002 Custom Integrated Circuits Conference Proc., pp. 5-3-1- 5-3-4