reconfigurable, high density, gigahertz speed low power … · 2007. 11. 24. · reconfigurable,...
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Reconfigurable, High Density, Gigahertz Speed Low Power Radiation Hardened FPGA Technology
Rajit Manohar1, Clinton W. Kelly1, IV, John Lofton Holt1, Chris Liu1, Dan Elftmann1
Leonard Rockett2, Dinu Patel2, Steven Danziger2, S. Ramaswamy2
Ken Label3, Melanie Berg3
1Achronix Semiconductor Corporation, 95 Brown Road, Suite 120, Ithaca, NY, 14850, USA 2BAE SYSTEMS, 9300 Wellington Road, Manassas, VA, 20110, USA
3National Aeronautical and Space Agency (NASA/GSFC), Greenbelt, MD, 20771, USA
27- 29 November 2007
1
BAE/Achronix RHFPGA Program
• Background• Introduction
• Achronix Company • Achronix FPGA Overview
• BAE/Achronix Radiation Hardened Test Chip Data• BAE/Achronix RHFPGA Program Overview
• Product Features• Product Development Strategy
• Summary
RHFPGA Roadmap
LegacyONO Antifuse
Based RHFPGA
Next GenerationM2M Antifuse
Based RHFPGA
• 5V Legacy Product: Actel RH1020 and RH1280 FPGA’s • Production stopped in 2002; Build-out Inventory - exhausted• Significant product demand continues• Actions being taken: Re-install FPGA process into recently
modernized foundry; Restart production.
• Actel RTAX FPGA’s are being used in space missions• Rad Hard (RHAX) FPGA’s are better suited for certain missions• Actions being taken: Migrate RTAX FPGA designs to RH foundry
to build RHAX FPGA equivalents; Start flight-qualified production.
• Critical need exists for re-configurable/ re-programmable, rad hard FPGA’s
• Actions being taken: Develop & demonstrate Multi-million gateRHFPGA using Achronix fabric built on radiation hardened process/designs.
ReconfigurableReprogrammable
RHFPGA
3
Program History – Investigated Achronix Base Technology Starting in 2006– Test chips fabricated & successfully tested for SEU in 2007– BAE/Achronix Joint Development Program started under government
funding in 2007
Program Goal– Develop a SRAM based Multimillion Gate Reconfigurable Radiation
Hardened FPGA based on Achronix architecture using BAE’s Radiation Hardened Process Technology
Background
4
Introduction
4
Well funded, privately held fabless semiconductor company
Founded in New York in 2004
Headquarters moved to San Jose in 2006, retained New York
R&D lab
Working 90nm and 180nm prototype silicon
Series of Patents protect key IP
Partnerships with Major Fabs, IP and EDA vendors
Well funded, privately held fabless semiconductor company
Founded in New York in 2004
Headquarters moved to San Jose in 2006, retained New York
R&D lab
Working 90nm and 180nm prototype silicon
Series of Patents protect key IP
Partnerships with Major Fabs, IP and EDA vendors
Achronix Company Overview
5
Achronix Commercial FPGAsStandard SRAM-based FPGA fabric
Embedded multipliers and memory blocks
Pipelined implementation for high frequency operation ( > 1 GHz)
Pipelining is transparent to designers– Designers write standard VHDL/Verilog
Industry-standard I/Os
6
Familiar Silicon & Familiar ToolsFamiliar SiliconFamiliar Silicon
Traditional 4-input LUT architecture– With GHz performance
SRAM-based reprogrammable FPGA
Requires no knowledge of underlying technology
Traditional 4-input LUT architecture– With GHz performance
SRAM-based reprogrammable FPGA
Requires no knowledge of underlying technology
Familiar ToolsFamiliar ToolsSYNP Synplify-Pro and Mentor Precision Synthesis Flows
Full compatibility with existing third party simulation, debug, and verification tools
SYNP Synplify-Pro and Mentor Precision Synthesis Flows
Full compatibility with existing third party simulation, debug, and verification tools
Achronix FPGA Architecture
7
Achronix CAD Environment (ACE) RTL design description
Mapped netlist
Synthesis
Simulation
Place & Route
Post P&R netlist
Bitstream download
ACENetlist
Prepare
88
180 nm prototype (Sep 2005)
– 674 MHz–World’s fastest CMOS FPGA by 2x
90 nm prototype (Apr 2006)
–1.93 GHz–World’s fastest CMOS FPGA by 5x
180 nm prototype (Sep 2005)
– 674 MHz–World’s fastest CMOS FPGA by 2x
90 nm prototype (Apr 2006)
–1.93 GHz–World’s fastest CMOS FPGA by 5x
Achronix FPGA History
9
Achronix 90nm FPGA SummaryAchronix STM 90nm Performance Data - Wide Tempterature and Voltage Operation
0
500
1000
1500
2000
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3000
3500
4000
4500
5000
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80
Supply Voltage
Mea
sure
d Th
roug
hput
(MH
z)
+21C
-196C
Achronix STM 90nm Performance Data - High Temperature Burn In
0.00
200.00
400.00
600.00
800.00
1000.00
1200.00
1400.00
1600.00
1800.00
2000.00
26.67
32.22
37.78
43.33
48.89
54.44
60.00
65.56
71.11
76.67
82.22
87.78
93.33
98.89
104.4
411
0.00
115.5
612
1.11
126.6
7
Degrees C
Mea
sure
d Th
roug
hput
(MH
z)
10
Achronix patented Redundancy Voting Circuits (RVC) SEU mitigation
Local voting waits until both copies agreeno SEU, no delayIf SEU on either, circuit resolves to the correct value after event energy dissipates
Redundancy Voting Circuits (RVC)Two copies of all circuits implementedCopies are non-adjacent avoiding the risk of a single upset affecting bothEvery stage (combinatorial and state) has local voting mechanism
Copy 1
Copy 2
Distance avoids both being affected
by same event
SEU Mitigation
BAE/Achronix RHFPGA Test Chip
12
RHFPGA Test Site
BAE-Achronix 54 mm2
RADHARD FPGA
Low density design, 27K gate, 250 MHz,
reconfigurable
BAE-Achronix 9 mm2
RADHARD FPGA with BAE hard SRAM cells
Low density design, 4K gates, 250 MHz
reconfigurable
BAE-Achronix 9 mm2
RADHARD FPGA with Achronix hard SRAM cells
Low density design, 4K gates, 250 MHz
reconfigurable
13
BAE-Achronix 3x3 RADHARD Testsite
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BAE RADHARD FPGA Test Site Results
14
Design SPICE results predicted 275 MHZ – We averaged 289.3 MHz
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
MH
z
BAE-A9
BAE-A8
BAE-A10
BAE-A10
BAE-A6
BAE-A2
BAE-A7
BAE-A4
BAE-A3
BAE-A5
BAE-A1
BAE A-Series Preliminary Test Results
Vdd
OverdriveVdd
Overdrive
Die Serial Number
15
Test Site Performance and Power Summary
15
0.0
50.0
100.0
150.0
200.0
250.0
300.0
MHz
1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5
Vdd
Speed Test Results (Running Program) - Serial#BAE-A9
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0.01
0.02
0.03
0.04
0.05
0.06
Pow
er (W
)
1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5
Vdd
Core Power Test Results (Running Program) - Serial#BAE-A9
16
Radiation Test Overview
The Test Chip contained a 4x4 array of FPGA Tiles implemented with RVC
One dedicated tile had an 8 bit counter (implemented in RVC) on output acknowledge to observe the functioning of the various FPGA configurations at a reasonable frequency with standard I/O
Five different FPGA patterns were utilized during testing running at different frequencies (37 MHz to 290MHz)
17
SEU Test SummaryTesting completed at Texas A&M Cyclotron with Argon (0°), Krypton(0° and 45°), and Xenon (45°) did not cause any of the 5 patterns to lock-up or fail
No observed SET or SEU events in SEE testing up to an effective LET threshold of 58 MeV-cm²/mg
This testing validates that the Achronix Redundancy Voting Circuits (RVC) are achieving the intended goals
BAE/Achronix RHFPGA Product
19
BAE RH15Radiation Hardened
Technology
Reconfigurable Radiation Hardened
FPGA
AchronixFPGA
Architecture
RHFPGA Product Approach
Final stages
• RH15 Radiation HardenedProcess
• RH15 RH SRAM • Configuration Memory• Block RAM (BRAM)• Registers
• Synchronous Frame• ESD resistant Programmable
I/Os• PLL
• FPGA Fabric• Reconfigurable Logic
Blocks• Redundancy Voting Circuits• Block RAM Wrapper• Multipliers• Routing Resources
• Synchronous/AsynchronousWrapper
PUBS-06- 20
50,772
132,935
208,333
380,069
050,000
100,000150,000200,000250,000300,000350,000400,000450,000
# tr
ansi
stor
s/sq
mm
1996 2004 2006 2007
RH SRAM Comparison - Transistor Density
Transistor Density
Magnum 4M
RH25 2.6X
Phoenix 4M
RH154.1X
16M RH15 7.5X
1M SRAM CMOS5XL
1.0X
16M SRAM Chip Statistics
> 113 Million Transistors; > 1 Billion Inter-Level Connects; 176 meters of Resistor16M SRAM is the highest density part built in Manassas
Transistors 113,070,511HVT NFETS 74,422,289HVT PFETS 38,645,756DGO NFETS 1,630DGO PFETS 836R2 Resistors 36,410,528
Q2 Capacitors 18,205,264
Total ILCs 1,063,783,005CA 298,967,451CT 226,146,395V1 212,067,749V2 242,233,858V3 82,209,612V4 1,011,258V5 506,746V6 639,936
RH15 Density Capabilities
RH15
PUBS-06- 21
RH15 Performance Capabilities
PDV3 Chiplet-1 Operation-Frequency versus Gamma-Dose [Vcore=Vdd+10%]
0
2000
4000
6000
8000
10000
12000
14000
10 100 1000 10000
Gamma-Dose krd(SiO2)
Ope
ratio
n Fr
eque
ncy
(MH
z)
Avg (5-Modules)
Chip 657D-6 C
pre-rd
Results confirm >1GHz performance both pre- and post-irradiation
(2 Mrd(SiO2))
Logic Representation of High Speed Signal Paths
PDV3 Chiplet-1 Idd(Q) Core-Current versus Gamma-Dose [Vcore=Vdd+10%]
0
1
2
3
4
5
6
7
8
10 100 1000 10000
Gamma-Dose krd(SiO2)
Idd(
Q) [
Cor
e-C
urre
nt] (
mA
)
Avg (5-Modules)
Chip 657D-5 C
pre-rd
ADDF>
14
>
DATA_IN_P/N(3:0)
CLK_IN_P/N DATA_OUT_P/N(3:0)
DFF_DATA_OUT_P/N
4-CMOSReceivers I/O Control
PTIPTO
RCV_ENDRV_EN
SEL
NAND4 NOR4 MUX2 XOR2DFFS MUX2Driver
Driver DFFS
No change in Iddq with
dose.
High Speed Circuit Testing to measure on-chip gate delay.
22
RHFPGA FeaturesReconfigurable Radiation Hardened FPGA for military, aerospace and industrial applications
Leverages standard RTL: Eliminates need for TMR design & tools
High Performance FPGA (Up to 350 MHz)
Total Dose Hardness through 1x106 rad(Si)
Single Event Error Rate of < 1x10 -11 upsets/bit day
Operating Temperature
– -55°C to 125°C (Ambient)– Extendable to Extreme Temperatures
Independently Configurable IO (PCI Compatible)– Low Voltage TTL/CMOS– LVDS– SSTL, HSTL
Existing FPGA EDA Tool Support (Synplicity & Mentor)
23
RHFPGA Product Development Strategy
Implement design using BAE Systems Radiation Hardened Process Technology Features
On-chip memory structures– Replace Standard SRAM with BAE Systems RADHARD SRAM
Circuit methodology– Use Achronix Redundancy Voting Circuit (RVC) and self-correction
capability to actively correct upsets and transients
Space apart critical nodes to reduce double-error probability
ACX RHFPGA Program OverviewAchronix:
⇒ Product Design⇒ Architecture Definition⇒ Reprogrammable Fabric⇒ Incorporate BAE RHSRAM
⇒ Final Design & Simulation⇒ Product Testing Support⇒ Sales/Marketing
BAE:⇒Design S-Frame, BRAM, IO, PLL
⇒ Integrate Design⇒ Wafer Processing/Characterization⇒ Wafer Sort and Packaging Tests
⇒ Packaging⇒ Radiation Testing
POC Ready 3Q09Start Qualification Option
Product design09/08
Fab at BAE in RH15 Process
03/09Package & Test
05/09
Radiation Test
07/09
25
RH15 CMOS Technology Features
Radiation Hardness Assurance Levels
1E-11SEU (errors/bit-day)120SEL (MeV-cm2/mg)
1E13Neutron Fluence (n/cm2)1E9Prompt Dose Upset (rad(Si)/s)1E12Prompt Dose Survival (rad(Si)/s)
Environment1MTotal Dose (rad(Si))
Key Features
Y/YC4 / WirebondYesResistorsYesCapacitors
7Metal Levels1.5 V / 1.8 V / 3.3 VVdd Options
26 Å / 70 ÅThin Oxide / DGO DevicesSTIIsolation
RH15Features:
26
RH15 Performance Parameters Test Results
RH15 KPP testing and verification successfully completedRH15 KPP testing and verification successfully completed
Goal level achieved.Complete1E121E121E12• Survivability
Threshold level achieved.Complete2.2E9>1E9>1E10• Upset
Dose Rate (rd(Si)/s)
Goal level achieved.Complete>1E13>1E12>1E13Neutron Radiation (n/cm2)
Goal level achieved.Complete>127>100>120• Latchup (MeV-cm2/mg)
Goal level achieved.Complete3.4E-11 S-ASIC, <<1E-12 SRAM<1E-10<1E-11• Upset (errors/bit-day)
Single Event
Goal level achieved.Complete> 2M= 500K= 1MTotal Ionizing Dose (rd(Si))
Worst Case and Post RadiationGoal level achieved.Complete> 3GHz500Mhz1GHz
Operating Speed
Complete-55 - 125C-55 - 125C-55 - 125C• FunctionalityGoal level achieved.
Complete0 - 80C0 - 80C0 - 80C• Full Performance
Operating Temp
Goal level achieved.Complete1.5, 1.8 and 2.5V1.5, 1.8 and 2.5V
1.5, 1.8 and 2.5VOperating Voltage
CommentsStatusTest ResultsThresholdGoalParameter
Goal level achieved.Complete1E121E121E12• Survivability
Threshold level achieved.Complete2.2E9>1E9>1E10• Upset
Dose Rate (rd(Si)/s)
Goal level achieved.Complete>1E13>1E12>1E13Neutron Radiation (n/cm2)
Goal level achieved.Complete>127>100>120• Latchup (MeV-cm2/mg)
Goal level achieved.Complete3.4E-11 S-ASIC, <<1E-12 SRAM<1E-10<1E-11• Upset (errors/bit-day)
Single Event
Goal level achieved.Complete> 2M= 500K= 1MTotal Ionizing Dose (rd(Si))
Worst Case and Post RadiationGoal level achieved.Complete> 3GHz500Mhz1GHz
Operating Speed
Complete-55 - 125C-55 - 125C-55 - 125C• FunctionalityGoal level achieved.
Complete0 - 80C0 - 80C0 - 80C• Full Performance
Operating Temp
Goal level achieved.Complete1.5, 1.8 and 2.5V1.5, 1.8 and 2.5V
1.5, 1.8 and 2.5VOperating Voltage
CommentsStatusTest ResultsThresholdGoalParameter
27
RHFPGA PackageBase Package: (Developed for FG-HPSC (OGA)
• Ceramic Column Grid Array• Flip Chip Ceramic Column Grid Substrate (CCGA)• Hermetic Seam Weld Sealing• Substrate: 35 x 35mm • 34 x 34 Column Array
• 1.0mm pitch • 1144 Total I/O
• 840 signal• 304 Vdd and Gnd
• Die site accommodates up to 20 mm Die
RHFPGA Package Plans:• Package Modeling – 10/08 – 12/08• Update Substrate Design & Verification – 12/08 – 2/09• Package Availability – 4/09
Package to be Modified to Accommodate Programmable I/O Features
28
SummaryTest Site
Electrical performance matches simulation (289 MHz)Preliminary SEU Radiation testing performed by NASAData shows no SEU observed up to LET of 58 at 0° & 45° angles of incidence
RHFPGA ProgramTechnical Goals of the Program Established
Build a multimillion reconfigurable RHFPGA using:– Achronix patented architecture– BAE’s RADHARD process technology
Preliminary Product Requirements definedProgram Plan in place
Design Activity underwayDefined Design Approach MethodologyDefined Specification details for BRAM, S-Frame, I/O, PLL.