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Reduction of Bitline to Control Gate leakage for improved 0.18 µm Embedded FLASH Yield and Reliability A.Cacciato, S. Nelson, M. Diekema, M. Hendriks, L. van Marwijk, C. Deuper, E. Gerritsen, R. Verhaar, and D. Dormans Philips Semiconductors, MOS4YOU, Nijmegen, The Netherlands

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  • Reduction of Bitline to Control Gate leakage for improved 0.18 µm Embedded FLASH Yield and

    Reliability

    A.Cacciato, S. Nelson, M. Diekema, M. Hendriks, L. van Marwijk, C.Deuper, E. Gerritsen, R. Verhaar, and D. Dormans

    Philips Semiconductors, MOS4YOU, Nijmegen, The Netherlands

  • Semiconductors 2

    OutlineOutline

    • Introduction

    • Goal• BL-CG isolation

    • Experimental •Results

    • Optimization of Contact and Pre-Metal Isolation modules

    • Reliability • Conclusions

  • Semiconductors 3

    Introduction: GoalIntroduction: Goal

    Development of a reliable 2T FN/FN flash memory embedded in a high-performance 0.18 µm CMOS

    logic process

    ⇓

    Modifications to the baseline logic process necessary to handle the double-poly topography of the stacked

    memory cell* and the high voltages during Write/Erase

    * ESSDERC 2001

  • Semiconductors 4

    Introduction: BitlineIntroduction: Bitline--Control Gate IsolationControl Gate Isolation

    BLCG

    FG

    Bitline (BL) to Control Gate (CG) isolation critical in non-volatile technology because of the high voltages during W/E

  • Semiconductors 5

    Introduction: BitlineIntroduction: Bitline--Control Gate IsolationControl Gate Isolation

    BLCG

    FG

    Bitline (BL) to Control Gate (CG) isolation critical in non-volatile technology because of the high voltages during W/E

    +10 V -5 V

  • Semiconductors 6

    Introduction: BitlineIntroduction: Bitline--Control Gate IsolationControl Gate Isolation

    BLCG

    FG

    Bitline (BL) to Control Gate (CG) isolation critical in non-volatile technology because of the high voltages during W/E

    Si3N4 borderless

    BL-CG distance

  • Semiconductors 7

    Introduction: BitlineIntroduction: Bitline--Control Gate IsolationControl Gate Isolation

    BLCG

    FG

    Bitline (BL) to Control Gate (CG) isolation critical in non-volatile technology because of the high voltages during W/E

    Si3N4 borderless

    BL-CG distance Yield loss + Endurance fails

  • Semiconductors 8

    Introduction: Endurance FailsIntroduction: Endurance Fails

    BL

    CGCross fail during 10k cycling @ 85C

  • Semiconductors 9

    ExperimentalExperimentalFlash cell

    •0.24/0.24, stacked. Thickness of Floating and Control Gate: 150 nm and 200 nm.

    •pre-metal isolation: 80 nm borderless Si3N4 followed by SACVD TEOS layer (350 nm) capped with PECVD TEOS. Nominal BL-CG distance and BL CD: 120 nm and 240 nm

    Test Structures

    •4 Mb and 256 Kb parallel arrays with different BL-CG distances

    Measurements

    •BL-CG leakage (CG = 15 V, BL = 0 V); •ramped Voltage-to-Breakdown (CG start voltage = 0 V, ramp rate = 0.25 V/step, BL voltage = 0 V).

  • Semiconductors 10

    Results: Results: BitlineBitline CD optimizationCD optimization

    0

    20

    40

    60

    80

    100

    120

    20 40 60 80 100 120

    BL-CG Misalignment (nm)

    BL

    -CG

    yie

    ld (%

    )

    BL-CG alignment to be controlled within ± 60 nm

    4 Mb BL-CG leakage yield

  • Semiconductors 11

    Binary versus phaseBinary versus phase--shiftshift

    Binary

    0

    10

    20

    30

    40

    50

    60

    0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3 0.31 0.32

    Bitline CD (µm)

    Freq

    uenc

    y Phase-Shift

    Bitline CD’s smaller for phase-shift contact mask

  • Semiconductors 12

    Binary versus phaseBinary versus phase--shiftshift

    BL-CG distance 100 nm

    0%

    20%

    40%

    60%

    80%

    100%

    -12 -10 -8 -6 -4 -2 0BL-CG Leakage (log(A))

    Cum

    . Per

    cent

    age

    (%)

    BinaryPhase-Shift

    BL-CG distance 120 nm

    0%

    20%

    40%

    60%

    80%

    100%

    -12 -10 -8 -6 -4 -2 0

    BL-CG Leakage (log(A))

    Cum

    . Per

    cent

    age

    (%)

    BinaryPhase-Shift

    a

    b

    BL-CG leakage on 256 Kb arrays for two BL-CG distances

    (a) 120 nm (b) 100 nm

    Smaller BL CD’s increase process-

    window

  • Semiconductors 13

    Results: Results: SiSi33NN44 optimizationoptimization

    SiN crack

    Single-frequency Dual-frequency

  • Semiconductors 14

    Single- versus Dual-frequency Nitride

    BL-CG leakage on 256 Kb arrays.

    (a) 120 nm (b) 100 nm

    A more conformal nitride increases process-window

    Binary, BL-CG distance 120 nm

    0%

    20%

    40%

    60%

    80%

    100%

    -12 -10 -8 -6 -4 -2 0

    BL-CG leakage (log(A))

    Cum

    . Per

    cent

    age

    (%)

    Single-Frequency SiNDual-Frequency SiN

    a

    Binary, BL-CG distance 100 nm

    0%

    20%

    40%

    60%

    80%

    100%

    -12 -10 -8 -6 -4 -2 0

    BL-CG leakage (log(A))

    Cum

    . Per

    cent

    age

    (%)

    Single-Frequency SiNDual-Frequency SiN

    b

  • Semiconductors 15

    Alignment-window Comparison Table

    BL-CGDistance

    Binary +Single SiN

    PSM +Single SiN

    Binary +Dual SiN

    PSM +Dual SiN

    120 nm OK OK OK OK100 nm - OK OK OK80 nm - - - OOOKKK

  • Semiconductors 16

    Reliability: Reliability: BLBL--CG breakdownCG breakdown

    0%

    10%

    20%

    30%

    40%

    50%

    60%

    70%

    80%

    90%

    100%

    0 10 20 30 40 50 60

    CG voltage @ 50nA [V]

    Cum

    . Per

    cent

    age

    (%)

    Before optimisationAfter optimisationW/E CG voltage

    The optimized process improves reliability

    BL-CG Voltage-to-Breakdown on 4 Mb arrays

  • Semiconductors 17

    ConclusionsConclusions

    • Contact and pre-metal isolation have to be modified to embed FLASH cells in a 0.18 µm logic process.

    • Phase-shift mask and conformal nitride guarantee reliable and manufacturable bitlineto control gate isolation and allow the further scalability of the FLASH cell

  • Reduction of Bitline to Control Gate leakage for improved 0.18 ?m Embedded FLASH Yield and ReliabilityOutlineIntroduction: GoalIntroduction: Bitline-Control Gate IsolationIntroduction: Bitline-Control Gate IsolationIntroduction: Bitline-Control Gate IsolationIntroduction: Bitline-Control Gate IsolationIntroduction: Endurance FailsExperimentalResults: Bitline CD optimizationBinary versus phase-shiftResults: Si3N4 optimizationReliability: BL-CG breakdownConclusions


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