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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO. 6, JUNE 2012 1215

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in90-nm CMOS for WLAN Receiver

Hwann-Kaeo Chiou, Member, IEEE, Kuei-Cheng Lin, Wei-Hsien Chen, and Ying-Zong Juang

AbstractA 5 GHz double balanced mixer (DBM) is imple-mented in standard 90 nm CMOS low-power technology. Anovel low-voltage self-bias current reuse technique is proposedin the RF transconductance stage to obtain better third-order

intermodulation intercept point (IIP ) and conversion gain (CG)when considering the process variations. The DBM achieves a CGof 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolationsof better than 50 dB. The input second-order (IIP ) and IIP

are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are thenintegrated with a differential low-noise amplifier (DLNA) and a

poly-phase filter, to from a direct-conversion receiver (DCR). TheDCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mWpower consumption from a 1 V supply voltage. The port-to-port

isolations are better than 50 dB. The IIP and the IIP of the DCRare 33 dBm and dBm, respectively.

Index TermsAC coupling, CMOS, current reuse, direct-con-version receiver, double balanced mixer, folded-switch mixer, lowvoltage.

I. INTRODUCTION

C MOS technology satisfies the requirements of the lowpower consumption, compact size, and high integrationlevel in multi-GHz radio frequency (RF) systems-on-a-chip

(SoC) designs. In particular, the direct-conversion receiver

(DCR) architecture has been chosen for the use in RF SoCsbecause of its relative simplicity and low cost [1], [2]. The

critical impacts of DCR are dc offset, IQ mismatch, even-order

intermodulation, LO leakage and radiation, flicker noise, and

dc power consumption. The dc offset which originates from

the self-mixing of the LO signal leakage, strong in-band in-

terferences and device mismatch, is the most critical design

issue in DCR. The dc offset associated with self-mixing effect

is mostly due to insufficient isolation between the LO and

RF ports [3], [4]. Therefore, increasing the isolation of the

mixer is a simple method of mitigating self-mixing effect. The

DBM naturally has high port-to-port isolations and directly

relieves the dc offset. The conventional Gilbert cell DBM

provides high port-to-port isolations with high CG, and is thusfavored for integrated circuit applications [5], [6]. However,

Manuscript received February 11, 2011; revised May 03, 2011; acceptedSeptember 13, 2011. Date of publication December 14, 2011; date of currentversion May 23, 2012. This work was supported by the National ScienceCouncil under Grant NSC 99-2221-E-008-100-MY3. This paper was recom-mended by Associate Editor P.-I. Mak.

H. K. Chiou and K. C. Lin are with the Department of Electrical Engineering,National Central University, Jhongli 320, Taiwan (e-mail: [email protected]).

W.-H. Chen and Y.-Z Juang are with the National Chip ImplementationCenter (CIC) of National Applied Research Laboratories, Hsinchu 300, Taiwan.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2011.2173399

the LO/RF and RF/LO isolations of conventional Gilbert cell

DBM are about 4050 dB, which are constrained by the device

mismatching and parasitic coupling from the lossy substrate.

Moreover, the Gilbert cell DBM needs three stacked transistors,

which wastes the voltage headroom and compresses the output

voltage amplitude and inevitably influences the linearity and

power consumption of the mixer. Since the input signal to the

mixer is higher than that to the LNA and no filter is placed

before LNA/mixer stages, a highly linear mixer is important

in DCR (i.e., high IIP and IIP ) to decrease the high order

distortions. This drawback becomes increasingly severe with

the shrinkage of the feature size in CMOS technology. Thelow-voltage operation requires fewer stacked battery cells to

reduce the power consumption and the battery weight. In the

past few years, several mixer designs have been published

using stacked cascode configuration. These designs achieve

low-power and low-voltage performance despite their relative

low CG and IIP due to the limited voltage swing across the

IF load [7][16]. Therefore, a folded-switch topology has been

proposed to reduce the supply voltage and power consump-

tion while keeps high CG, IIP and port-to-port isolations,

[17][23]. However, few studies discussed these important

features related to low-voltage operation.

Thefl

icker noise of the transistors strongly affects the base-band signal because the down-converted spectrum of DCR is

around zero frequency. Meanwhile, the flicker noise due to the

LO switch core must be considered in determining NF perfor-

mance. Therefore, a PMOS switch core is often preferred in low

flicker noise mixer [24][28].

This work proposes a low-voltage topology to achieve a

DBM with high CG, IIP , IIP , isolations and low NF simul-

taneously. A 5 GHz CMOS DBM operating at 0.7 and 1.0 V

supply voltages is designed to investigate the above mentioned

performance. Fig. 1 shows the block diagram of the designed

90 nm CMOS DCR. Two designed mixers are combined with

a differential low noise amplifier (DLNA), a poly-phase filter,

and two buffer amplifiers to form a 4.75.7 GHz DCR. The

DLNA amplifies the input RF signal which is then down-con-

verted to zero intermediate frequency (IF) by two quadrature

LO signals.

II. CIRCUIT DESIGNS FOR LOW VOLTAGE OPERATION

A. Self-Bias Current Reuse Technique and AC-Coupling

Folded-Switch Mixer

Fig. 2 shows the conceptual diagram of the proposed DBM

for low-voltage operation. The newly developed self-bias

current reuse technique has two advantages: 1) improves the

CG and IIP in the RF transconductance stage, and 2) uses

1549-8328/$26.00 2011 IEEE


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1216 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO. 6, JUNE 2012

Fig. 1. The block diagram of direct-conversion receiver.

Fig. 2. The conceptual diagram of the proposed ac-coupling, PMOS folded-switch DBM for low-voltage operation.

single PMOS folded-switch transistor with LC tank to allow

low-voltage operation. The resonant frequency of the LC tank

is designed around the RF and LO frequencies to prevent the

signals leakage through the power supply. Since the LC tank

requires no voltage headroom between the supply voltage rail

and ground, the voltage across the IF load can be maximized

and effectively increases the CG and IIP . Furthermore, the

PMOS transistor has lowerflicker noise than its NMOS coun-

terpart, and thus the NF is improved. The PMOS switch core

also has high linearity and low NF under low LO power at low

bias current. Fig. 3 shows the schematic diagram of the pro-posed mixer, which consists of an RF transconductance stage

, a self-bias current reuse bias circuit , a

PMOS LO folded-switch core , two ac-coupling

capacitors, two LC tanks , and two IF loads .

B. Conversion Gain, Noise Figure and Linearity

The ideal mixer multiplies the RF input signal by the LO

pumped signal to produce the sum or difference signal, i .e., in-

termediate-frequency (IF). If the LO signal is an ideal square

wave, then the CG of the mixer is given by (1).

(1)

Fig. 3. Schematic diagram of the proposed mixer.

The values of and are 210 and 0.032 (A/V)

in this design, the calculated CG is 12.7 dB. If the LO waveform

is a sinusoidal, then the CG is given by (2) [24].

(2)

where is the time interval of the positive and negative period

turning on simultaneously. isthe LO frequency.At high LO

amplitude, the LO waveform resembles a square waveform and

its fundamental coefficient of the power series is approximately

. At low LO power level, the higher LO power corresponds

to the higher CG. However, when the mixer is driven by too

much LO power, the harmonic distortion reduces the CG. In

practice, the optimum LO power level is set to maximize CG.

Fig. 4 shows the CG with respect to the LO power. The optimalLO power levels for the NMOS and the PMOS switch cores

are 0 and dBm, respectively. Although the PMOS switch

core has a lower CG than its NMOS counterpart, the CG of the

PMOS switch core exhibits a plateau response over an extended

LO power [24].

The PMOS switch core has a lower sensitivity to the LO

power level than the NMOS one. Thus, a mixer with a PMOS

switch core requires less LO power and relaxes the required

output power from the VCO design.

Flicker noise in CMOS mixer has been analyzed in detail

elsewhere [24][28]. Fig. 5 shows the simulated flicker noise of

the PMOS and the NMOS transistors use for the LO switch core

in tsmc 90 nm CMOS process. The PMOS transistor has a

lowerflicker noise than that in the NMOS transistor[24]. Hence,


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CHIOU et al.: A 1-V 5-GHZ SELF-BIAS FOLDED-SWITCH MIXER IN 90-NM CMOS FOR WLAN RECEIVER 1217

Fig. 4. The conversion gain versus the LO power using the PMOS and theNMOS switch cores.

the PMOS switch core exceeds NMOS in the flicker noise per-

formance. The total noisesof the direct-conversion mixer are the

sum of the flicker noise and the thermal noise associated with

the RF transconductance, the LO switch core, and IF load. The

MOSFET transistor is known to have significant flicker noise.

Equations (3)(6) show the thermal and flicker noise contribu-

tions to the NF of the proposed mixer.

(3)

(4)

(5)

(6)

where , and are the flicker noise, drain current of tran-

sistor, and the peak-to-peak voltage at the LO switch

core. and are the process-dependent constant, bias-de-

pendent factor and source resistor. is the drain current of the

RF transconductance stage. is the power gain of the mixer.

The flicker noise and thermal noise dominate the noise perfor-

mance of the mixer. According to (3) and (4), increasing the LOamplitude of the switch core improves the noise performance.

The PMOS LO switch core has better NF performance than the

NMOS switch core because the of PMOS transistor is

low. The process parameters in tsmc 90 nm CMOS process

are listed as follows: the of PMOS is 0.44 nV at 10 MHz,

and . The value for a short

channel device is about 1 [29]. The power gain is 12 dB. In

this design, the NF is 10.1 dB according to (6).

Equation (7) shows the power-series expansion of the voltage

transfer function that is adopted to evaluate the linearity [3],

[30].

(7)

Fig. 5. Comparison of the flicker noise of the PMOS and the NMOS switchcores.

The first four terms in (7) are sufficient to characterize the

nonlinearity in practical mixer. In tsmc 0.18 m CMOS

process, the short channel model of drain current is approx-

imately as (8) [31].

(8)

(9)

where is the field-limited electron mobility, is the gate

oxide capacitance per unit area, and is the velocity satu-

ration field strength. Equations (11) and (12) indicate the IIP

of the self-bias current reuse with ac-coupling folded-switch

mixer. is the overdrive voltage of the RF transconductance

stage. The terms of and are the (A/V ) of the NMOSand PMOS, respectively. The terms of and are the (V)

of the NMOS and PMOS, respectively. The values of and

in tsmc 90 nm CMOS process are 0.067 and 0.045. The

values of and in tsmc 90 nm CMOS process are 0.43

and 2. In this design, the IIP is 2.2 dBm according to (11)(12).

(10)

(11)

(12)

C. RF Transconductance for Low Voltage Operation

According to (2), the RF transconductance stage is mainly

responsible for the CG. Fig. 6 presents six possible topologies

of the RF transconductance stage for low-voltage operation.


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Fig. 6(a) shows a common source (CS) amplifier with a resis-

tive load for the RF transconductance stage. The resistive load

not only degrades the NF performance but also wastes the

voltage headroom. This drawback can be mitigated by using an

active current source load instead of the resistive load, as shown

in Fig. 6(b). Since the output impedance of the PMOS transistor

is sufficiently high, the NF and CG are improved. The PMOS

current source can be further used to amplify the RF signal and

the amplifier becomes a CMOS inverter, as shown in Fig. 6(c).

This inverter results in high gain and low-power performance

because it combines the transconductances of the parallel-con-

nected NP MOS transistors with current reuse topology [9].

When the input signal has positive-going swing, the PMOS tran-

sistor moves toward the cut-off region and provides an equiva-

lent load resistance forthe NMOS CS amplifier. On the contrary,

when the input signal has negative-going swing, the operation

region of the transistors is exchanged. The PMOS transistor is

used as a CS amplifier with an NMOS resistive load. The gain

of the CMOS inverter equals the sum of the gain of the NMOS

and PMOS CS amplifiers. The total transconductance of the RFtransconductance stage equals . The terms and

are the transconductances of the NMOS and PMOS, re-

spectively. Equation (13) presents the minimal required voltage

of the topology in Fig. 6(c).

(13)

where

and are the overdrive voltage of the NMOS and the

PMOS transistors, respectively. and are the threshold

voltage of the NMOS and the PMOS transistors. is

gate-source voltage of the PMOS transistor. and are

the bias voltages at gate of the NMOS and PMOS transistors.

As seen in (13), the overdrive voltage of the NMOS and PMOS

transistors determines the minimal required voltage of the

CMOS inverter. Fig. 6(d) shows a resistive feedback inverter as

the fourth topology for the RF transconductance stage. When

the feedback resistance exceeds 3 k , the gain is close to that

of the inverter without feedback. , is the same as (13).

In general, the value of in tsmc 90 nm CMOS process is

typically 210 mV. If the supply voltage is 1 V, then theresulting IIP is approximately dBm, which value limits

the dynamic range of the receiver. To overcome this limitation,

the topology of the CMOS inverter is modified as shown in

Fig. 6(e) [18]. The parallel-connected NP MOS transistors can

be separately biased by adding a capacitor at the gate node. The

of this topology is expressed as (14).

(14)

If is chosen to be greater than , then can

be reduced. In this way, the value of the IIP in tsmc 90

nm CMOS process is approximately 1 dBm, giving a 4.5 dB

in IIP improvement over the conventional CMOS inverter as

presented in Fig. 6(d). Although this biasing scheme reduces the

required supply voltage and increases IIP , it requires two inde-

pendent biases. Fig. 6(f) shows the proposed self-bias scheme

for the PMOS transistor to overcome this drawback. This self-

bias scheme enables the gate voltage of the PMOS transistor is

directly biased from the dc output which saves one bias path

compared with [18]. The self-bias condition of the PMOS tran-

sistor has less one bias in bias path. The minimal required

voltage can be set by selecting the value of according to

(15).

(15)

The transconductance stage of [18], as shown in Fig. 6(e),

requires two independent biases ( and ) for NMOS

and PMOS transistors. Fig. 6(f) shows the self-biased topology

in the RF transconductance stage which is a typical shunt-shunt

feedback configuration. Since the drain and the gate of the

PMOS transistor have the same voltage, the PMOS transistor

always operates in saturation. The advantages of this topology

compared with [18] are in four folds. First, the gate voltage ofthe PMOS transistor is directly biased from the output which

saves one bias path compared with [18]. Second, a smaller

feedback resistor is used for broad-band matching which

achieved the input return loss better than 10 dB. Third, the

proposed transconductance stage uses the resistive feedback

topology that improves the linearity and resists the PVT vari-

ations. The IIP of the transconductance stage compared with

that of [18] has less sensitivity to the process variations. Fourth,

the self-biased topology of the PMOS transistor always oper-

ates in saturation to achieve better IIP and transconductance

compared with those in [18] when considering the process

variations.The device mismatch model was applied in the simulations

to evaluate all performance of the proposed mixer, including

dc bias conditions, CG, NF, IIP , IIP , and isolations. The

mismatch model provides the device size-dependent mismatch

model to reflect the size-dependent mismatch behavior. The

random variations in Gaussian distribution of the process

parameters including / and of the transistors are

included in the model to account for the mismatch performance

of and parasitic capacitor effect.

Take tsmc 90 nm CMOS process as an example. Figs. 7

and 8 present the simulated transconductance and IIP of six

RF transconductance stages. As observed, the self-bias current

reuse topology achieves the smallest error of transconductance

and IIP performance among all possible topologies with de-

vice mismatch effect. As indicated in simulations, the proposed

topology decreases the errors in transconductance of 2.6 mS and

IIP of 3.5 dBm as compared with the topology in Fig. 6(e).

D. Isolation

The dc offset caused by self-mixing effect mostly comes from

insufficient LO/RF and RF/LO isolations of the mixer.

In a DBM as shown in Fig. 9(a), the non-ideal effects such

as device mismatch, layout asymmetry, substrate leakage,

radiation, and parasitic capacitor loading at the source of the

switching pair provide several leakage paths

from LO to RF port and thus reduce the isolations. Fig. 9(b)


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Fig. 6. Six possible topologies of the RF transconductance for low-voltage operation. (a) CS stage with the resistive load. (b) CS stage with the current source asactive load. (c) CMOS inverter. (d) CMOS inverter with the resistive feedback. (e) PMOS and NMOS transistors are separately biased. (f) CMOS inverter withthe PMOS self-bias current reuse technique.

Fig. 7. Simulated transconductance of six possible different topologies for theRF transconductance stage.

shows the equivalent half circuit around the RF feed-node

of the proposed mixer. The LO-to-RF leakage produced by

the drain-to-gate capacitor of the RF stage is partially

attenuated by the shunt feedback resistor that improves

LO-RF isolation.

(16)

Fig. 8. Simulated IIP of six possible different topologies for the RF transcon-ductance stages.

The value of is15 fF. Fig.10 shows the simulated LO-to-RF

isolation versus different value of . If is set to open cir-

cuit, thecircuit can be taken as a conventional Gilbert cell mixer.

When the value is increased gradually, the LO-to-RF isola-

tion is improved. As can be seen, when is 300 that im-

proves a 12-dB LO-to-RF isolation. Fig. 11 shows the simulated

LO-to-RF isolation of the conventional and proposed mixers

driven by the differential LO with a phase imbalance of 0 to


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Fig. 9. The ideal and actual differential models. (a) Double balanced. (b) LC tank ac-coupling folded-switch with self-bias current reuse technique.

Fig. 10. LO-to-RF isolation versus .

. As can be seen, the proposed mixer improves a 15 dB

LO-to-RF isolation.

E. Differential Variable Gain Low Noise Amplifier

Fig. 12 shows the schematic diagram of the DLNA with vari-

able gain control. The input match network uses a capacitor in

series with a bond-wire inductor. , and are

chosen to simultaneously match the minimal reflection and NF.

The inductors are realized by using on-chip spiral inductors.

The inductance with its parasitic capacitance is designed for

output matching to maximize the gain at the frequency band of

interest. A current-splitting technique is applied here for vari-

able gain control. The current-splitting transistors and

Fig. 11. LO-to-RF isolation.

are controlled by varying the control voltage . When

is set to 0 and are OFF and the DLNA

operates in high gain mode. When is set to 1

and are ON and the DLNA operates in low gain mode.

F. Poly-Phase Filter

The poly-phase filter is a symmetric RC network whose

outputs are with phase differences. The differential input

voltage is converted to quadrature phase of the LO signal by

a multi-order poly-phase circuit [32], [33]. Since unwanted

phase difference occurs due to the asymmetric interconnection

through the first stage, the capacitor value is optimized in

the second stage to achieve the best quadrature accuracy of

the ployphase filter. The optimized is 0.165 pF. Fig. 13(a)

presents the schematic diagram of the 5.19 GHz poly-phase

filter and output buffer amplifiers with their detail design


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Fig. 12. Schematic diagram of the fully differential LNA with variable gaincontrol.

Fig. 13. (a) Schematic diagram of the poly-phase filter. (pF, pF). (b) Output buffer (

m/0.1 m, pF, nH).

parameters. The output buffer followed by the second stage of

poly-phase filter is used to avoid the loading effect. Fig. 13(b)

shows the schematic diagram of the output buffer which adopts

a single stage differential cascode topology. The inductance

with its parasitic capacitance is designed for the output

matching to maximize the power to drive the next mixer stage.

III. MEASUREMENT RESULTS

A. Low-Voltage AC-Coupling Folded-Switch DBM

The circuit was simulated using Agilent Advanced Design

System (ADS) simulator. The self-bias current reuse mixer

and direct-conversion receiver were designed and fabricated

Fig. 14. Chip photo of the fabricated mixer.

using tsmc 90 nm CMOS 1P9M low-power technology.

The RF model included standard NMOS/PMOS, an MIM

capacitor with or without an underground metal, an MOS

varactor, a junction varactor, a resistor, an RTMOM and nine

metallization layers with a deep N-well (DNW)/P-substrate.

The model included three scalable inductor models, standard,

symmetric and symmetric with center tap. The and ofthe NMOS in the transconductance stage are 102 GHz and 85

GHz, respectively.

Fig. 14 shows the photo of the fabricated mixer. The chip size

is 0.545 mm . Fig. 15 shows the measured input return losses

of the RF and LO stages. The RF stage achieves the return loss

better than 10 dB from 4.7 to 5.8 GHz. Fig. 16 shows the CG

with respect to the LO power. The peak CG is obtained at an LO

power of dBm. When the LO power is less than dBm, the

CG declines because the switch core operates in the triode re-

gion and cannot perform good current commutation. When the

LO power is higher than dBm, the harmonic distortion re-

duces the CG. As can be seen, the simulated and the measuredresults agree closely with each other. Figs. 17 and 18 plot the

simulated, calculated and measured of CG and NF of the mixer,

respectively. Fig. 17 shows the frequency responses of CG and

the maximum CG is 12.3 dB at 4.8 GHz with 4.6-mW dc power

consumption. The CG is dB from 4 to 6.6 GHz. The

correspondent RF bandwidth is 2.6 GHz. The measured NF is

below 10.6 dB in Fig. 18. The measurements were performed at

a fixed IF frequency of 10 MHz. Fig. 19 shows the 1-dB com-

pression point measurement. The measured CG and the

input are 12 dB and dBm, respectively. Fig. 20 shows

the measured isolations at LO/RF power levels of and

dBm, respectively. The LO-to-IF and LO-to-RF isolations ex-ceed 52 dB at the LO frequencies from 4.5 to 8.5 GHz. The high

impedance of the LC tank at the RF and the LO frequencies pro-

vides good LO-to-RF isolation. The RF-to-IF isolation exceeds

60 dB.

Fig. 21(a), (b) plot the simulated and measured of IIP and

IIP , respectively. The two-tone intermodulation measurements

are performed using two signals with equal power at 5.189 and

5.191 GHz. The measured IIP and IIP are 48 dBm and 4

dBm, respectively. Fig. 22 plots the simulated and measured

CG and IIP as varied from 0.7 to 1.0 V. The pro-

posed topology functions properly at the of 0.7 V and

achieves a CG of 9 dB and an IIP of 0 dBm.

Table I summarizes the simulated and the measured perfor-

mance of the proposed mixer. Since the IIP of a balanced mixer


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Fig. 21. (a) The simulated and measured results of the IIP . (b) The simulatedand measured results of the IIP .

Fig. 22. The gain and IIP measurements with various .

Fig. 23. Benchmark of the low-voltage mixers.

TABLE IPERFORMANCE SUMMARY OF THE PROPOSED MIXER

B. Front-End Receiver

Fig. 24 shows the photo of the fabricated DCR. The chip area

is 2.24 mm . The dc pads are wire-bonded to the PCB to pro-

vide the dc bias. TheLO/RF signals are fed by on-wafer GSGSGprobes. The differential IF signal is buffered by a source fol-

lower output stage to match 50 termination. The receiver con-

sumes a dc power of 21 mW from a 1 V supply voltage. Fig. 25

shows that the measured input return loss is 16 dB at 5.2 GHz,

and remains better than 10 dB from 4.7 to 5.7 GHz. Fig. 26

plots the CG versus the LO power. The DCR obtains a flat CG

of 26 dB at LO power between to 0 dBm which is attributed

by the LO power insensitivity of the PMOS switch core. No-

tably, if the LO power is generated by an silicon-based VCO

at 1 V operation, the output power of VCO is unlikely to ex-

ceed 0 dBm, which power level corresponds to a of 633

mV at 50 load. This value of is very difficult to achievein low-voltage operation. Therefore the PMOS switch core is

adopted to relax the power requirement of VCO.

Fig. 27 shows the CG frequency responses of the receiver and

the maximum CG is 26.2 dB at 5.4 GHz. The CG is

dB from 4.6 to 6 GHz. The correspondent RF bandwidth is 1.4

GHz. Fig. 28 plots the simulated and the measured input

at RF and IF frequencies of 5.2 GHz and 10 MHz, respectively.

The measured input is dBm. Since the NF of DCR

is affected by its high noise power spectral density near dc fre-

quency, Fig. 29 shows the simulated and measuredNF as a func-

tion of the IF frequency to evaluate the flicker noise corner. As

seen, the corner frequency is about 600 KHz. The NF is 2.7 dBat 5.2 GHz RF frequency (IF = 10 MHz).

Fig. 30 shows the measured IIP and IIP based on two tone

test which is performed by applying two RF signals with the

equal power level at 5.189 and 5.191 GHz. The measured IIP

and IIP are 33 dBm and dBm, respectively. Since the

maximum signal handled by the receiver is dBm for both

WLAN and WiMAX standards, the obtained IIP meets the

specification. When the LO power is 0 dBm, the dc offset is

measured according the method developed in [40]. The induced

dc offset of the DCR are 2.2 mV and 0.5 mV at high gain and

low gain modes, respectively. Table III summaries the simu-

lated and the measured results of the DCR at high CG and low

CG mode, respectively. According to these experimental re-

sults, the designed DCR satisfies the requirements of WLAN


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TABLE IIPERFORMANCE SUMMARY OF THE RECENT CMOS MIXER DESIGNS

Fig. 24. Chip photo of the fabricated DCR.

Fig. 25. Measured the input return loss of the DCR.

and WiMAX standardsin 4.7 to 5.7GHz frequency band. Works

[41][43] adopted current driven passive mixer in direct conver-

sion receiver to obtain high linearity and low noise performance.

Table IV benchmarks the overall performance of recent works

and our proposed mixer [40][44].

Fig. 26. The conversion gain versus the LO power ( GHz,GHz).

Fig. 27. The simulated and measured results of the conversion gain of the re-ceiver ( MHz, RF dBm, LO dBm).


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Fig. 28. The simulated and the measured of the DCR ( MHz,LO dBm).

Fig. 29. Simulated and measured DCR NF versus IF bandwidth (GHz, LO dBm).

Fig. 30. Measurements of IIP and IIP .

IV. CONCLUSION

This work demonstrates a low-voltage self-bias folded-

switch mixer design, which maintains the performance of CG,

NF, linearity, and port-to-port isolations at low supply voltage.

In the RF transconductance stage, the self-bias current reuse

topology makes the supply voltage as low as possible and fa-

vors the CG and IIP . In the LO switch core design, the PMOS

folded-switch with the LC tank allows low-voltage operation,

and simultaneously provides low NF and high linearity. The

proposed mixer outperforms the conventional Gilbert cell

mixer by 3 dB in CG, 1.3 dB in NF, 7 dB in IIP and 10

dB in LO-to-RF isolation at the same power consumption of

4.6 mW. The measured mixer achieves very good FOM, as

compared with the overall performance of the CG, NF, IIP ,

TABLE IIIPERFORMANCE SUMMARY OF THE RECEIVER

TABLE IVPERFORMANCE SUMMARY OF THE RECENT CMOS RECEIVERDESIGNS

IIP , and power dissipation. The measured results for variouscharacteristics are all agreed with the simulations. This mixer

topology is suitable for low-voltage applications. A 1 V 4.7 to

5.7 GHz DCR has been successfully integrated and fabricated

in tsmc 90 nm CMOS low power technology. The DCR

performs very well and can be adopted in 4.7 to 5.7 GHz band

wireless products.

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Hwann-Kaeo Chiou (M05) was born in Taichung,Taiwan, in 1959. He received the B.S. degree in elec-trical physics from National Chiao Tung University,Hsinchu, Taiwan, in 1982, and the M.S.E.E. degreeand Ph.D. degrees in electrical engineering from Na-tional Taiwan University, Taipei, in 1985, and 1997,respectively.

From 1985 to 2000, he was an Associate Re-searcher with the Chung-Shan Institute of Scienceand Technology (CSIST), where he was in chargeof the development of microwave integrated circuits

(MICs), MMICs and microwave subsystems for mobile communication. From2000 to 2002, he was an Associate Vice President at BenQ Inc., where he was

in charge of the development of broadband wireless access technology. InAugust 2002, he joined the faculty of the Department of Electrical Engineering,


13/13


National Central University, Jhongli, Taiwan, where he is currently a Professorand Chair. His current research interests include RF integrated circuits (RFICs),MMICs, and millimeter-wave integrated circuits.

Kuei-Cheng Lin was born in Kaohsiung, Taiwan,in 1981. He received the M.S. degree from the De-

partment of Electrical Engineering, National CentralUniversity, Jhongli, Taiwan, in 2006. He is currentlyworking toward the Ph.D. degree in electrical engi-neering at National Central University, Jhongli.

In October 2006, he joined National Chip Imple-mentation Center, Hsinchu, Taiwan, as an AssociateResearcher, responsible for RF front-end transceivercircuit design. His current research interests are lowpower and high linearity design for RF front-end

transceiver circuit in CMOS, SiGe BiCMOS, and compound semiconductors.

Wei-Hsien Chen received the B.S. degree in elec-trical engineering from National Taiwan OceanUniversity, Keelung, in 2003, and the M.S. degree in

electronics engineering from National Chiao-TungUniversity (NCTU), Hsinchu, Taiwan, in 2005.In 2006, he joined the System-on-Chip (SoC)

Technology Center (STC), Industrial TechnologyResearch Institute (ITRI), Hsinchu. He was an RFdesign engineer and designed an ultra-low-powerRF receiver for hearing aids. From 2007 to 2008,he designed analog baseband circuits for ultra-wide-

band and DVB-H system. In 2009, he was designing a neural sensor appliedfor biotechnology in the human body. His research interests include analogcircuit design for wireless transceivers and biotechnology applications. In2010, he joined National Chip Implementation Center (CIC), Hsinchu, wherehe is currently a Researcher and a Deputy Department Manager in charge ofthe development of system-on-chip design environment and technologies.

Ying-Zong Juang received the M.S. and Ph.D.degrees in electrical engineering from the NationalCheng Kung University, Taiwan, in 1992 and 1998,respectively.

He joined the Institute of Chip ImplementationCenter, Science-Based Industrial Park, Hsinchu,Taiwan, in October 1998. At CIC, he has majoredin the RF circuit design and device modelingworks, furthermore, from 2001 to 2004, he joineda project to develop the CMOS MEMS platform.Now, he is the Researcher and Department M anager

of CISD/CIC and his interested topics include the technologies of wirelessmicro-sensing system. Therefore, he organized several projects including RFtop-down design, RFIP methodology for frequency synthesizer, RF SiP, and0.35 m/0.18 m CMOS MEMS/BioMEMS design environment.

ref[1] refered circuit

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