reflections on 10 years as a commercial on-chip interconnect provider drew wingard cto, sonics, inc
TRANSCRIPT
Reflections on 10 Years as a Commercial On-chip Interconnect Provider
Drew WingardCTO, Sonics, Inc.
10 Years as an Interconnect Provider (NOCS 2007)
25/8/2007
Agenda
• The Market Opportunity• The Technology• The Business
10 Years as an Interconnect Provider (NOCS 2007)
35/8/2007
Market Opportunity
September 1996– The Internet is hot
• Yahoo/Netscape/etc. newly public• Silicon Valley VC’s looking for anything network-related
– Convergence is hot• Want to mix data processing, communications, and content
– Many of the new applications are consumer-driven• Very sensitive to cost and form factor• Integration is key
– SoC’s seem like the only rational approach…
SONICS, INC.
“Systems on ICs”
SONICS, INC.
SONICS, INC.
Current Trends Digital Convergence
– consumer, computer & communications Moore’s Law continues
– single chip systems Architectural Convergence
– General purpose CPU with hardware assist Traditional design approaches failing
– Traditional vendors cannot meet “time-to-market” demands or cost targets
SONICS, INC.
The Battleground For Consumers
Networks Computers
PDA
PC
NCConsumer Electronics
Internet
SONICS, INC.
Systems-On-ICs: Applications
Consumer Electronics– Internet TV, Email Phones, DVD, Set-Top Box
Networking– Routers, Switches, Network Interface Devices
Communications– Wireless Phones, Wireless PDAs
Computing– Net Computers, PDAs
SONICS, INC.
Examples of Reference Platforms
SONICS, INC.
System Architectures
SONICS, INC.
Today Future
Networking
Communications
Consumer Info Appliance
SONICS, INC.
Sonics Integration Architecture
On-chipI/O
Ethernet Interface
Modem Interface
Graphics
Processor Core
Clocks
SRAM
OtherAudio
Interface
Sonics Integration Foundation
DRAM
Video
Memory
Processor
Communications
On-chipI/O
Ethernet Interface
Modem Interface
Graphics
Processor Core
Clocks
SRAM
OtherAudio
Interface
Sonics Integration Foundation
On-chipI/O
Ethernet Interface
Modem Interface
Graphics
Processor Core
Clocks
SRAM
OtherAudio
Interface
Sonics Integration Foundation
DRAM
Sil
icon
Bac
kP
lan
e
SONICS, INC.
Mission Statement
SONICS will be a leading manufacturer of single-chip systems for networking & communications applications.
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Rethinking the Market Opportunity
• Market needed high-function, inexpensive silicon to enable convergence applications
• Sonics had a novel approach to address the integration challenges, but…– No OEM’s would trust these markets to a start-up– No VC would fund a “fabless, chipless” IC company!
• “If our strategic value is in our ability to integrate, maybe we should package and license our integration technology…”
SONICS, INC.
IC Designer Challenges IC Designers become System Designers Performance Modeling Across Design Hierarchy Hardware/Software Partitioning and Co-design Mix-and-Match IP Validation/Test of Deeply-Embedded Systems Predictable Physical Design
The Sonics Integration Architecture is a systematic solution for these challenges
SONICS, INC.
IC Designers become System Designers
SemiconductorHouseIP Providers
ProductSpecification
SystemHouse
IntegrationArchitecture
ICDesigner
System LevelIntegration
Time-to-market will drive the need for IC Designers to develop a systematic approach to:– scalability over a wide-
range of applications– ready integration of
proven IP with newly designed IP
SONICS, INC.
The Sonics Solution
System Designer
Sonics Integration ArchitectureCores + Communications + Chips
Silicon Backplane Logic Backplane
ICDesigner
System
-Level T
ools
Display MemoryProcessor Communications
Systems Software
Core Developer
ASSP PLDFull Custom
SONICS, INC.
IPProvider
PLDASIC
SystemHouse
OS Provider
EDASoftware
ASSP
SONICS
Technology License - Up Front License Fee - Implementation - Royalty - SupportSoftware Tools
IPWorks License
Product SupportSonics Module Interface: Open Technology
Sonics Architecture API: Open Technology
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The Business Opportunity: Summary
• Since early 1997, Sonics has been a semiconductor IP supplier focused on selling interconnect networks for SoC applications
• Fortunately, fully half of the $68 Billion market for digital logic semiconductors is now classified as “SoC”– … and the rest seems to be on its way!
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The Technology
• Since Sonics’ original intent was to integrate IP from lots of sources (including customers!), we’ve always had a strong focus on interfacing
• Key elements of Sonics’ architecture (1997-now)– Flexible interface sockets– De-coupled agents offering data-flow services– Advanced internal fabrics
• While all of the names – and much of the underlying technology – have changed, we’re still on that same course…
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Flexible Sockets
SONICS, INC.
IC Designers become System Designers
SemiconductorHouseIP Providers
ProductSpecification
SystemHouse
IntegrationArchitecture
ICDesigner
System LevelIntegration
Time-to-market will drive the need for IC Designers to develop a systematic approach to:– scalability over a wide-
range of applications– ready integration of
proven IP with newly designed IP
SONICS, INC.
Background Sonics Module Interface is a Virtual Component
Interface specifically designed to:– Isolate VC’s from logical and physical bus requirements
(i.e be a bus wrapper)– Specify both basic and advanced functionality
» Minimize area overhead for simple VC’s
» Improve performance for complex VC’s
– Provide structure for user-defined enhancements– Allow “black box” verification and testing– Interface should be symmetric, so VC’s can also connect
directly to each other (i.e. without an on-chip bus)
SONICS, INC.
Silicon BackplaneProtocol
Physical Bus
VSIA Model and Sonics Integration Architecture
Transaction Protocol
Bus TransferProtocol
Sonics ModuleInterface
VSIA On-chipBus Model
SonicsIntegration
Architecture
Physical Bus
The Sonics Silicon Backplane is a proprietary communication protocol that facilitates connection of VC cores with widely-varying performance requirements
BusWrapper
VirtualComponent
SONICS, INC.
Sonics Module Interface
VirtualComponent
VirtualComponent
VirtualComponent
On-Chip Bus
Slave
Master SlaveSlave
Slave
Master
Master MasterInitiator Target
ModuleInterface Request
Response
SONICS, INC.
Additions: Threads A thread is a sequence of transfers that must occur in-order with
respect to one another Transfers in different threads may occur out-of-order Threads can represent:
– Separate, independent streams– Separate operation types– Combinations of the above
Thread Identifiers are Layer 2 (Point-to-point) Additional signals to support threads
– Master passes ReqThreadID as tag with request ( 4 bits)– Slave returns RespThreadID with response– Optional ThreadBusy bit vectors for thread status Non-blocking
flow control
SONICS, INC.
Test Bench Example
ConnID ThreadID Cmd Addr (Length) (Data)
0x1F 0x2 bfill32 0x1000 8 0x12345678
0x1F 0x2 bread32 0x1FFF 8
0x10 0x1 read8 0x8
0x10 0x1 write8 0x2008 0xFF
Perl-based assembler / disassembler Behavioral Verilog VC cores Protocol checker at interface
Transaction-basedverification
SONICS, INC.
Conclusions Wide adoption of any standardized VC interface
depends on two technical measures– Area efficiency for simple/low-performance VC’s– Performance capability for complex/high-performance VC’s
Sonics Module Interface defines:– Small core of mandatory signals– Wide range of optional signals– Structure method for extension– Logical and electrical protocols
» Necessary for validation» Allows true “black box” VC-based design and testing
Highlyconfigurable
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What happened to SMI?
• Re-christened “Open Core Protocol” in 1999• OCP-IP announced 2001
– Original GSC: MIPS, Nokia, Sonics, TI, UMC– Currently over 170 members
• Basic OCP protocol is the same as SMI– OCP 2.0 added significant improvements to burst
model
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Agents and Fabrics
• Sonics’ interconnects have always been highly configurable– Originally based on intuition about required flexibility– Now based on customer demand
• Biggest input into configuration decision is based on chip-level data flow
Characteristics: Wide performance range Increasing real-time
multimedia/networking traffic
Shared memory requirements
Complex interactions Challenging Design
System-on-a-Chip CommunicationsSystem-on-a-Chip Communications
PCI
IP Core Communications Bandwidth
DSP
ATM
CPU
3D
Video/2D
LAN
4M 16M 64M 256M 1G 4G 16G 64G 256GBandwidth (bits/sec)
P1394
Real-Time
Performance-Driven
Sonics Integration ArchitectureSonics Integration Architecture
Conventional Sonics IntegrationArchitecture
DMA CPU DSP
A
B
Bridge
C I O O Sonics Module Interface
PeripheralBus
System Bus
Custom Interfaces
DSPCPUDMA A
C B I O O
Sonics Silicon Backplane
Allows unification of allon-chip communication
Integration Architecture Aspects*Integration Architecture Aspects*
Tunable Communications Subsystems– Silicon BackplaneTM
– Logic BackplaneTM
Configurable IP Core Interface– Sonics Module Interface
Design Software– Backplane Compiler
* Patent Pending
DSPCPUDMA A
C MEM I O
Sonics Module Interface
Initiator Module
Target Module
Logic Backplane Bridge
Silicon Backplane
Agents
Bus Bandwidth RequirementsBus Bandwidth Requirements
Must satisfy sum of sustained BW
Total bus BW >peak BW of any IP Core
Bandwidth mismatch between Bus and IP Cores
Need de-coupled Bus performance
SOC Data Flow
DSPCPUDMA A
C MEM I O O
< 10 Mbits/sec
< 100 Mbits/sec
> 100 Mbits/sec
Except DRAM
Computer Bus ApproachComputer Bus Approach
IPCore
IPCore
IPCore
IPCore
ComputerBus
Transmit FIFO Receive FIFO
Time
Data
Arbiter Address
Communication Bus ApproachCommunication Bus Approach
IPCore
IPCore
IPCore
IPCore
CommunicationsBus
Transmit FIFO Receive FIFO
Time
Data
TDMA TDMA
Guaranteed Bandwidth ArbitrationGuaranteed Bandwidth Arbitration
Independent arbitration for every cycle Two phases
– Distributed TDMA– Round robin
Gives SOC designer fine control oversystem bandwidth
CurrentSlot
Arbitration
Command
Pipeline DiagramPipeline Diagram
Cycle 1 2 3 4 5 6 7 8
Arbitration
Command WR WR
Address A1 A2
Data D1 D2
Response
Integrated Signaling MechanismIntegrated Signaling Mechanism
Dedicated Backplane wires (Flags) support:– Bus-style Out-of-Band Signaling (Interrupts)– Point-to-Point Communications (Flow control)– Dynamic point-to-point (Retry mechanism)
Integral part of Integration Architecture– Same design flow, timing, flexibility as address/data part
Retry Mechanism:RD1 RD1
RTRY Valid
7
Command
Response
FlagNum
Flag[7]
Target Module Block DiagramTarget Module Block Diagram
Silicon Backplane Interface
Sonics Module Interface
Address Decoder
CLOCK
Configuration Registers
Address/Data Flow
Synchronizer (Optional)
Clock
Address /Control
Data
Define System SpecificationsDefine System Specifications
Partition SystemPartition System
Analyze PerformanceAnalyze Performance
Select / DesignIP Cores
Select / DesignIP Cores
Simulate / Integrate SOCSimulate / Integrate SOC
Bandwidth EngineeringBandwidth Engineering
BackplaneCompiler
BackplaneCompiler
System Bandwidth & Latency Constraints
IP Core
Requirements
IP Cores Silicon Backplane
soccomp
MicroNetwork DefinitionMicroNetwork Definition
Network: A heterogeneous integrated network that unifies, decouples, and manages all of the communication between processors, memories, and input/output devices
SOC Integration FlowSOC Integration Flow
1. Pre-characterize the MicroNetwork physical design
2. Determine base architecture
3. Choose MicroNetwork data flow parameters
4. Build SOC data flow model (behavioral + traces)
5. Improve the model
6. Test the physical design
7. Integrate actual IP Cores and verify functionality
8. Map the control flow
9. Verify system functionality
10.Map manufacturing test and complete physical design
IP Core IntegrationIP Core Integration
IP Core IntegrationIP Core Integration
IP Core IntegrationIP Core Integration
IP Core IntegrationIP Core Integration
Configuring MicroNetwork ParametersConfiguring MicroNetwork Parameters
Select Address Map
Configure Arbitration
Choose Data Width& Pipeline Depth
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Today’s Sonics Technology
10 Years as an Interconnect Provider (NOCS 2007)
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NetworkNetwork
DRAM ControllerDRAM ControllerCPUCPU DMADMADMADMA DRAM ControllerDRAM ControllerCPUCPU
Network-based SoC: Active Decoupling
• Separation• Abstraction• Optimization• Independence
MasterMaster
SlaveSlave
SlaveSlave
MasterMaster
Socket
MasterMaster SlaveSlave
MasterMasterSlaveSlave
16 128
BusAdapter
BusAdapter
BusAdapter
BusAdapter
BusAdapter
BusAdapter
BusAdapter
BusAdapter
Core Function
Communication
Core Function
Communication
Core Function
Communication
AgentAgent AgentAgent AgentAgent AgentAgent
Internal FabricInternal Fabric
SMART Interconnect
10 Years as an Interconnect Provider (NOCS 2007)
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Fabric
The Intelligence is in the Agents
• Agents provide…– Protocol conversion
• Agent adapts to IP core
– Decoupling of IP cores from fabric• Provide local, isolated environment
– Layered services
• Agent services– Power management– Security management– Error management– QoS– Burst, width, and command conversion
I
T
I
T
I
T
I
T
I
T
INITIATOR SOCKETS
TARGET SOCKETS
Target Agents (TA)
Initiator Agents (IA)
10 Years as an Interconnect Provider (NOCS 2007)
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Global Interconnect Responsibilities• Routing
– Getting requests, responses and data to the desired destination
• Access control– Managing contention for shared resources (ensuring QoS)– Ensuring requested access is allowed (security and protection)
• Error management– Detection, reporting, and SW recovery support
• Power management– Activity detection, clock and voltage removal support
• Connectivity– Protocol conversion– Data width / clock frequency conversion
• Spanning distance– Connecting endpoints at required frequency and latency
Full Support
Partial Support
Other approaches
10 Years as an Interconnect Provider (NOCS 2007)
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Interconnect Fabric Options
• SoC data flow requirements must be satisfied by internal interconnect fabric– Big challenge in current SoC designs!
• Choices in interconnect fabric design– Unified vs. split transactions– Shared vs. separate physical links– Combinational vs. pipelined– Single vs. multiple outstanding transactions
(transaction pipelining)– In-order vs. out-of-order completion and response– Blocking vs. non-blocking flow control
10 Years as an Interconnect Provider (NOCS 2007)
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Blocking vs. Non-blocking Flow Control
• Sharing in SoC’s creates many opportunities for contention– Arbitration determines who wins– Flow control determines when the winner gets to go
• Blocking flow control systems allow resource shortages along some paths to prevent other paths from progressing
• Non-blocking flow control systems ensure that points of sharing never stall if any data flow could progress– Leads to both higher efficiency and greater predictability– Allows more resource sharing
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SMX
SonicsMX Basic Architecture
• Hybrid topologies– Full / partial cross-bar– Shared bus
• Pipelined, multi-threaded, non-blocking fabric
• Fully split (dual) request / response
• Distributed QoS arbiter– Spans cycle, frequency, and
data width boundaries– Supports flexible thread
merging tree topologies
I
SMX
CPU
DSP
GFX
ROM
SRAM
FlashCtl.
DRAMCtl.
I I I I
T
T
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The Business
• “Architectures take about 10 years to pay off. I’m not sure that I have another architecture company in me”
Bill DavidowLead VC/Chair, Rambus1998
• 10+ years old• > $60 Million capital investment• > 200 Million units shipped• 2 years of profits
10 Years as an Interconnect Provider (NOCS 2007)
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Where’s SonicsSonics?