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Reliability of Reliability of Ovonic Ovonic Unified MemoryUnified Memory

Neal Mielke Neal Mielke Intel CorporationIntel CorporationStephen Hudgens Stephen Hudgens Ovonyx IncOvonyx Inc

Brian Johnson Brian Johnson Intel CorporationIntel CorporationTyler Tyler Lowrey Lowrey Ovonyx IncOvonyx Inc

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AgendaAgenda

•• Introduction: OUM MemoryIntroduction: OUM Memory•• Reliability CapabilityReliability Capability•• Degradation MechanismsDegradation Mechanisms•• Future workFuture work•• ConclusionsConclusions

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Chalcogenide MaterialChalcogenide Material•• Chalcogenide is the general class of Chalcogenide is the general class of

switching media in CDswitching media in CD--RW and DVDRW and DVD--RWRW–– In high volume production and low costIn high volume production and low cost

•• Laser beam energy is used to control the Laser beam energy is used to control the switching between crystalline and switching between crystalline and amorphous phasesamorphous phases–– Higher energy Higher energy --> amorphous> amorphous–– Medium energy Medium energy --> crystalline> crystalline

•• Low energy laser beam to readLow energy laser beam to read

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AmorphousPhase

CrystallinePhase

Short Range Atomic Order

Low Free Electron Density

High Activation Energy

High Resistivity

Long Range Atomic Order

High Free Electron Density

Low Activation Energy

Low Resistivity

0.2 microns

Electron Diffraction Patterns

Material Characteristics

Scale:

Amorphous vs Crystalline PhasesAmorphous vs Crystalline Phases

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Ovonics Unified Memory (OUM)Ovonics Unified Memory (OUM)•• Instead of using laser beam, use Instead of using laser beam, use

electric current to heat the materialelectric current to heat the material–– High current, high temperature: High current, high temperature:

amorphous phase, high resistanceamorphous phase, high resistance–– Medium current, lower temperature: Medium current, lower temperature:

crystalline phase, low resistancecrystalline phase, low resistance•• Low current to sense resistanceLow current to sense resistance

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Amorphous or Crystalline Chalcogenide

Crystalline Chalcogenide

Memory StructureMemory Structure

Res

istiv

e H

eate

r

Thermal Insulator

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Bit line

Word line

Array Element: Junction Diode selection

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Memory array operation showing select and deselect conditions

BL n-1 BL n+1

WL n

WL n+1

WL n-1

BL n

BLnBLn-1BLn+1WLnWLn-1WLn+1

Ireset0V0V0VVddVdd

Iset0V0V0VVddVdd

Iread0V0V0VVddVdd

Reset Set Read

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Time

Tem

pera

ture

Ta

T

T

m

x

AmorphizingRESET Pulse

Crystallizing(SET) Pulse

t1

t2

Basic Device Operation: Basic Device Operation: Set/Reset PulsesSet/Reset PulsesC

urre

nt

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IV Curve of Chalcogenide ElementIV Curve of Chalcogenide Element

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RRsetset and Rand Rreset reset as Function of Cell Currentas Function of Cell Current

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Reliability Considerations

• Endurance: Withstand set/reset cycles• Data retention: Retain data over

time/temperature• Disturb Immunity: Ability of cell to

retain data in face of voltage transients

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AgendaAgenda

•• Introduction: OUM MemoryIntroduction: OUM Memory•• Reliability CapabilityReliability Capability•• Degradation MechanismsDegradation Mechanisms•• Future workFuture work•• ConclusionsConclusions

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RRsetset and Rand Rresetreset as Function of Cyclesas Function of Cycles

• Capability: Stable window beyond 1012 cycles

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Endurance

• Capability: Stable programming characteristics

1.E+03

1.E+04

1.E+05

1.E+06

0 0.2 0.4 0.6 0.8 1

Pulse Current (A.U.)

Dev

ice

Res

ista

nce

(Ohm

s)

1E2 Cycles1E9 Cycles

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Retention CharacteristicsRetention Characteristics

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Retention at 70Retention at 70ººC after 10C after 1077 CyclesCycles

• Capability: Many years data retention

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Disturb Immunity

• Concern (left): Heat in cycled cell could spread to adjacent cell, converting reset to set

• Capability (right): No disturb over > 109 pulses• “Ah, but what about scaling?”

BL n-1 BL n+1

WL n

WL n+1

WL n-1

BL n

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Disturb Scaling• Heat spread limited by:1. Diffusion: 2. Steady State:

– Radial: 1/R– 3-D “resistive divider”

• Main limit is steady state: . >0.3-5 µm in previous example (0.18 µm tech)

• Heat equation scales: adjacent cell temperature unchanged with scaling

• Capability: Disturb not an issue with future scaling

Dt

Dt

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AgendaAgenda

•• Introduction: OUM MemoryIntroduction: OUM Memory•• Reliability CapabilityReliability Capability•• Degradation MechanismsDegradation Mechanisms•• Future workFuture work•• ConclusionsConclusions

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Endurance: Reset Migration

• Walk-in of R-I characteristic with cycles• Some migration always present in 1st two cycles

(virgin chal has slightly different microstructure)• Severe migration (above) occurs with non-

optimized electrodes & interface quality

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

0.0 0.5 1.0Current (A.U.)

Res

ista

nce

1E5 Cycles3E7 Cycles0 Cycles

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Endurance: Stuck Reset

• Often caused by physical separation of chal from electrode in non-optimized devices

• Example above is unpassivated cell

0

1

10

100

1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

Cycles

Res

ista

nce

(KO

hms)

ResetSet

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Endurance: Stuck Set

• Stuck set is more common failure mode (above)• Endurance scales with energy per pulse• Can occur when chal intermixes with adjacent

materials– Strongly dependent on electrode & dielectric materials

1.0E+031.0E+041.0E+051.0E+061.0E+071.0E+081.0E+091.0E+101.0E+111.0E+121.0E+13

1 10 100 1000

Energy per Pulse (A.U.)

Cyc

les

Unt

il Fa

ilure

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Retention for Non-Optimized Device

• Retention can fall short of capability with non-optimized processes

Post-Bake:Process B

Post-Bake:Process A

Pre-Bake

Equiv 106 years

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Future Work• Atomic-level models for effects of continued

high-J stressing of chalcogenide • Dynamics of crystallization: seeding,

nucleation, etc.• Chalcogenide-electrode interactions:

Chemical/mechanical stability, effect on electrical characteristics

• Dependence of above effects on stoichiometry of the chalcogenide

• Improved reliability acceleration models for endurance degradation mechanisms

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Conclusions• Optimized OUM can possess strong

endurance, retention, and disturb capability

• Degradation mechanisms clearly observable on non-optimized devices– Window and reset-current instability with

endurance cycling– Degraded retention (reset to set)

• All mechanisms depend on purity and compatibility of the chalcogenide and surrounding materials

• Detailed acceleration and atomic-level models are areas for future work